1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # !! 2 config MIPS
3 # For a description of the syntax of this conf !! 3 bool
4 # see Documentation/kbuild/kconfig-language.rs !! 4 default y
5 # !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 config OPENRISC !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 def_bool y !! 8 select ARCH_HAS_FORTIFY_SOURCE
9 select ARCH_32BIT_OFF_T !! 9 select ARCH_HAS_KCOV
10 select ARCH_HAS_DMA_SET_UNCACHED !! 10 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
11 select ARCH_HAS_DMA_CLEAR_UNCACHED !! 11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE !! 12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
13 select COMMON_CLK !! 13 select ARCH_HAS_UBSAN_SANITIZE_ALL
14 select OF !! 14 select ARCH_SUPPORTS_UPROBES
15 select OF_EARLY_FLATTREE !! 15 select ARCH_USE_BUILTIN_BSWAP
16 select IRQ_DOMAIN !! 16 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
17 select GPIOLIB !! 17 select ARCH_USE_QUEUED_RWLOCKS
18 select HAVE_ARCH_TRACEHOOK !! 18 select ARCH_USE_QUEUED_SPINLOCKS
19 select SPARSE_IRQ !! 19 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
20 select GENERIC_IRQ_CHIP !! 20 select ARCH_WANT_IPC_PARSE_VERSION
>> 21 select BUILDTIME_TABLE_SORT
>> 22 select CLONE_BACKWARDS
>> 23 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
>> 24 select CPU_PM if CPU_IDLE
>> 25 select GENERIC_ATOMIC64 if !64BIT
>> 26 select GENERIC_CLOCKEVENTS
>> 27 select GENERIC_CMOS_UPDATE
>> 28 select GENERIC_CPU_AUTOPROBE
>> 29 select GENERIC_GETTIMEOFDAY
>> 30 select GENERIC_IOMAP
21 select GENERIC_IRQ_PROBE 31 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW 32 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP !! 33 select GENERIC_ISA_DMA if EISA
24 select GENERIC_IOREMAP !! 34 select GENERIC_LIB_ASHLDI3
25 select GENERIC_CPU_DEVICES !! 35 select GENERIC_LIB_ASHRDI3
26 select HAVE_PCI !! 36 select GENERIC_LIB_CMPDI2
27 select HAVE_UID16 !! 37 select GENERIC_LIB_LSHRDI3
28 select HAVE_PAGE_SIZE_8KB !! 38 select GENERIC_LIB_UCMPDI2
29 select GENERIC_ATOMIC64 !! 39 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
30 select GENERIC_CLOCKEVENTS_BROADCAST <<
31 select GENERIC_SMP_IDLE_THREAD 40 select GENERIC_SMP_IDLE_THREAD
32 select MODULES_USE_ELF_RELA !! 41 select GENERIC_TIME_VSYSCALL
>> 42 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
>> 43 select HANDLE_DOMAIN_IRQ
>> 44 select HAVE_ARCH_COMPILER_H
>> 45 select HAVE_ARCH_JUMP_LABEL
>> 46 select HAVE_ARCH_KGDB
>> 47 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 48 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
>> 49 select HAVE_ARCH_SECCOMP_FILTER
>> 50 select HAVE_ARCH_TRACEHOOK
>> 51 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
>> 52 select HAVE_ASM_MODVERSIONS
>> 53 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 54 select HAVE_CONTEXT_TRACKING
>> 55 select HAVE_TIF_NOHZ
>> 56 select HAVE_C_RECORDMCOUNT
>> 57 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DEBUG_STACKOVERFLOW 58 select HAVE_DEBUG_STACKOVERFLOW
34 select OR1K_PIC !! 59 select HAVE_DMA_CONTIGUOUS
35 select CPU_NO_EFFICIENT_FFS if !OPENRI !! 60 select HAVE_DYNAMIC_FTRACE
36 select ARCH_USE_QUEUED_RWLOCKS !! 61 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
37 select OMPIC if SMP !! 62 select HAVE_EXIT_THREAD
38 select PCI_DOMAINS_GENERIC if PCI !! 63 select HAVE_FAST_GUP
39 select PCI_MSI if PCI !! 64 select HAVE_FTRACE_MCOUNT_RECORD
40 select ARCH_WANT_FRAME_POINTERS !! 65 select HAVE_FUNCTION_GRAPH_TRACER
41 select GENERIC_IRQ_MULTI_HANDLER !! 66 select HAVE_FUNCTION_TRACER
42 select MMU_GATHER_NO_RANGE if MMU !! 67 select HAVE_GCC_PLUGINS
43 select TRACE_IRQFLAGS_SUPPORT !! 68 select HAVE_GENERIC_VDSO
>> 69 select HAVE_IDE
>> 70 select HAVE_IOREMAP_PROT
>> 71 select HAVE_IRQ_EXIT_ON_IRQ_STACK
>> 72 select HAVE_IRQ_TIME_ACCOUNTING
>> 73 select HAVE_KPROBES
>> 74 select HAVE_KRETPROBES
>> 75 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 76 select HAVE_MOD_ARCH_SPECIFIC
>> 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
>> 79 select HAVE_PERF_EVENTS
>> 80 select HAVE_REGS_AND_STACK_ACCESS_API
>> 81 select HAVE_RSEQ
>> 82 select HAVE_SPARSE_SYSCALL_NR
>> 83 select HAVE_STACKPROTECTOR
>> 84 select HAVE_SYSCALL_TRACEPOINTS
>> 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
>> 86 select IRQ_FORCED_THREADING
>> 87 select ISA if EISA
>> 88 select MODULES_USE_ELF_REL if MODULES
>> 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
>> 90 select PERF_USE_VMALLOC
>> 91 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 92 select RTC_LIB
>> 93 select SET_FS
>> 94 select SYSCTL_EXCEPTION_TRACE
>> 95 select VIRT_TO_BUS
>> 96
>> 97 config MIPS_FIXUP_BIGPHYS_ADDR
>> 98 bool
>> 99
>> 100 config MIPS_GENERIC
>> 101 bool
>> 102
>> 103 config MACH_INGENIC
>> 104 bool
>> 105 select SYS_SUPPORTS_32BIT_KERNEL
>> 106 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 107 select SYS_SUPPORTS_ZBOOT
>> 108 select DMA_NONCOHERENT
>> 109 select IRQ_MIPS_CPU
>> 110 select PINCTRL
>> 111 select GPIOLIB
>> 112 select COMMON_CLK
>> 113 select GENERIC_IRQ_CHIP
>> 114 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 115 select USE_OF
>> 116 select CPU_SUPPORTS_CPUFREQ
>> 117 select MIPS_EXTERNAL_TIMER
44 118
45 config CPU_BIG_ENDIAN !! 119 menu "Machine selection"
46 def_bool y <<
47 120
48 config MMU !! 121 choice
49 def_bool y !! 122 prompt "System type"
>> 123 default MIPS_GENERIC_KERNEL
>> 124
>> 125 config MIPS_GENERIC_KERNEL
>> 126 bool "Generic board-agnostic MIPS kernel"
>> 127 select MIPS_GENERIC
>> 128 select BOOT_RAW
>> 129 select BUILTIN_DTB
>> 130 select CEVT_R4K
>> 131 select CLKSRC_MIPS_GIC
>> 132 select COMMON_CLK
>> 133 select CPU_MIPSR2_IRQ_EI
>> 134 select CPU_MIPSR2_IRQ_VI
>> 135 select CSRC_R4K
>> 136 select DMA_PERDEV_COHERENT
>> 137 select HAVE_PCI
>> 138 select IRQ_MIPS_CPU
>> 139 select MIPS_AUTO_PFN_OFFSET
>> 140 select MIPS_CPU_SCACHE
>> 141 select MIPS_GIC
>> 142 select MIPS_L1_CACHE_SHIFT_7
>> 143 select NO_EXCEPT_FILL
>> 144 select PCI_DRIVERS_GENERIC
>> 145 select SMP_UP if SMP
>> 146 select SWAP_IO_SPACE
>> 147 select SYS_HAS_CPU_MIPS32_R1
>> 148 select SYS_HAS_CPU_MIPS32_R2
>> 149 select SYS_HAS_CPU_MIPS32_R6
>> 150 select SYS_HAS_CPU_MIPS64_R1
>> 151 select SYS_HAS_CPU_MIPS64_R2
>> 152 select SYS_HAS_CPU_MIPS64_R6
>> 153 select SYS_SUPPORTS_32BIT_KERNEL
>> 154 select SYS_SUPPORTS_64BIT_KERNEL
>> 155 select SYS_SUPPORTS_BIG_ENDIAN
>> 156 select SYS_SUPPORTS_HIGHMEM
>> 157 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 158 select SYS_SUPPORTS_MICROMIPS
>> 159 select SYS_SUPPORTS_MIPS16
>> 160 select SYS_SUPPORTS_MIPS_CPS
>> 161 select SYS_SUPPORTS_MULTITHREADING
>> 162 select SYS_SUPPORTS_RELOCATABLE
>> 163 select SYS_SUPPORTS_SMARTMIPS
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select UHI_BOOT
>> 166 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 167 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 168 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 169 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 170 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 171 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 172 select USE_OF
>> 173 help
>> 174 Select this to build a kernel which aims to support multiple boards,
>> 175 generally using a flattened device tree passed from the bootloader
>> 176 using the boot protocol defined in the UHI (Unified Hosting
>> 177 Interface) specification.
>> 178
>> 179 config MIPS_ALCHEMY
>> 180 bool "Alchemy processor based machines"
>> 181 select PHYS_ADDR_T_64BIT
>> 182 select CEVT_R4K
>> 183 select CSRC_R4K
>> 184 select IRQ_MIPS_CPU
>> 185 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 186 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 187 select SYS_HAS_CPU_MIPS32_R1
>> 188 select SYS_SUPPORTS_32BIT_KERNEL
>> 189 select SYS_SUPPORTS_APM_EMULATION
>> 190 select GPIOLIB
>> 191 select SYS_SUPPORTS_ZBOOT
>> 192 select COMMON_CLK
>> 193
>> 194 config AR7
>> 195 bool "Texas Instruments AR7"
>> 196 select BOOT_ELF32
>> 197 select DMA_NONCOHERENT
>> 198 select CEVT_R4K
>> 199 select CSRC_R4K
>> 200 select IRQ_MIPS_CPU
>> 201 select NO_EXCEPT_FILL
>> 202 select SWAP_IO_SPACE
>> 203 select SYS_HAS_CPU_MIPS32_R1
>> 204 select SYS_HAS_EARLY_PRINTK
>> 205 select SYS_SUPPORTS_32BIT_KERNEL
>> 206 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 207 select SYS_SUPPORTS_MIPS16
>> 208 select SYS_SUPPORTS_ZBOOT_UART16550
>> 209 select GPIOLIB
>> 210 select VLYNQ
>> 211 select HAVE_LEGACY_CLK
>> 212 help
>> 213 Support for the Texas Instruments AR7 System-on-a-Chip
>> 214 family: TNETD7100, 7200 and 7300.
>> 215
>> 216 config ATH25
>> 217 bool "Atheros AR231x/AR531x SoC support"
>> 218 select CEVT_R4K
>> 219 select CSRC_R4K
>> 220 select DMA_NONCOHERENT
>> 221 select IRQ_MIPS_CPU
>> 222 select IRQ_DOMAIN
>> 223 select SYS_HAS_CPU_MIPS32_R1
>> 224 select SYS_SUPPORTS_BIG_ENDIAN
>> 225 select SYS_SUPPORTS_32BIT_KERNEL
>> 226 select SYS_HAS_EARLY_PRINTK
>> 227 help
>> 228 Support for Atheros AR231x and Atheros AR531x based boards
>> 229
>> 230 config ATH79
>> 231 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 232 select ARCH_HAS_RESET_CONTROLLER
>> 233 select BOOT_RAW
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select DMA_NONCOHERENT
>> 237 select GPIOLIB
>> 238 select PINCTRL
>> 239 select COMMON_CLK
>> 240 select IRQ_MIPS_CPU
>> 241 select SYS_HAS_CPU_MIPS32_R2
>> 242 select SYS_HAS_EARLY_PRINTK
>> 243 select SYS_SUPPORTS_32BIT_KERNEL
>> 244 select SYS_SUPPORTS_BIG_ENDIAN
>> 245 select SYS_SUPPORTS_MIPS16
>> 246 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 247 select USE_OF
>> 248 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 249 help
>> 250 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 251
>> 252 config BMIPS_GENERIC
>> 253 bool "Broadcom Generic BMIPS kernel"
>> 254 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 255 select ARCH_HAS_PHYS_TO_DMA
>> 256 select BOOT_RAW
>> 257 select NO_EXCEPT_FILL
>> 258 select USE_OF
>> 259 select CEVT_R4K
>> 260 select CSRC_R4K
>> 261 select SYNC_R4K
>> 262 select COMMON_CLK
>> 263 select BCM6345_L1_IRQ
>> 264 select BCM7038_L1_IRQ
>> 265 select BCM7120_L2_IRQ
>> 266 select BRCMSTB_L2_IRQ
>> 267 select IRQ_MIPS_CPU
>> 268 select DMA_NONCOHERENT
>> 269 select SYS_SUPPORTS_32BIT_KERNEL
>> 270 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 271 select SYS_SUPPORTS_BIG_ENDIAN
>> 272 select SYS_SUPPORTS_HIGHMEM
>> 273 select SYS_HAS_CPU_BMIPS32_3300
>> 274 select SYS_HAS_CPU_BMIPS4350
>> 275 select SYS_HAS_CPU_BMIPS4380
>> 276 select SYS_HAS_CPU_BMIPS5000
>> 277 select SWAP_IO_SPACE
>> 278 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 279 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 280 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 281 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 282 select HARDIRQS_SW_RESEND
>> 283 help
>> 284 Build a generic DT-based kernel image that boots on select
>> 285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 287 must be set appropriately for your board.
>> 288
>> 289 config BCM47XX
>> 290 bool "Broadcom BCM47XX based boards"
>> 291 select BOOT_RAW
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select HAVE_PCI
>> 296 select IRQ_MIPS_CPU
>> 297 select SYS_HAS_CPU_MIPS32_R1
>> 298 select NO_EXCEPT_FILL
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 301 select SYS_SUPPORTS_MIPS16
>> 302 select SYS_SUPPORTS_ZBOOT
>> 303 select SYS_HAS_EARLY_PRINTK
>> 304 select USE_GENERIC_EARLY_PRINTK_8250
>> 305 select GPIOLIB
>> 306 select LEDS_GPIO_REGISTER
>> 307 select BCM47XX_NVRAM
>> 308 select BCM47XX_SPROM
>> 309 select BCM47XX_SSB if !BCM47XX_BCMA
>> 310 help
>> 311 Support for BCM47XX based boards
>> 312
>> 313 config BCM63XX
>> 314 bool "Broadcom BCM63XX based boards"
>> 315 select BOOT_RAW
>> 316 select CEVT_R4K
>> 317 select CSRC_R4K
>> 318 select SYNC_R4K
>> 319 select DMA_NONCOHERENT
>> 320 select IRQ_MIPS_CPU
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_HAS_EARLY_PRINTK
>> 324 select SYS_HAS_CPU_BMIPS32_3300
>> 325 select SYS_HAS_CPU_BMIPS4350
>> 326 select SYS_HAS_CPU_BMIPS4380
>> 327 select SWAP_IO_SPACE
>> 328 select GPIOLIB
>> 329 select MIPS_L1_CACHE_SHIFT_4
>> 330 select CLKDEV_LOOKUP
>> 331 select HAVE_LEGACY_CLK
>> 332 help
>> 333 Support for BCM63XX based boards
>> 334
>> 335 config MIPS_COBALT
>> 336 bool "Cobalt Server"
>> 337 select CEVT_R4K
>> 338 select CSRC_R4K
>> 339 select CEVT_GT641XX
>> 340 select DMA_NONCOHERENT
>> 341 select FORCE_PCI
>> 342 select I8253
>> 343 select I8259
>> 344 select IRQ_MIPS_CPU
>> 345 select IRQ_GT641XX
>> 346 select PCI_GT64XXX_PCI0
>> 347 select SYS_HAS_CPU_NEVADA
>> 348 select SYS_HAS_EARLY_PRINTK
>> 349 select SYS_SUPPORTS_32BIT_KERNEL
>> 350 select SYS_SUPPORTS_64BIT_KERNEL
>> 351 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 352 select USE_GENERIC_EARLY_PRINTK_8250
>> 353
>> 354 config MACH_DECSTATION
>> 355 bool "DECstations"
>> 356 select BOOT_ELF32
>> 357 select CEVT_DS1287
>> 358 select CEVT_R4K if CPU_R4X00
>> 359 select CSRC_IOASIC
>> 360 select CSRC_R4K if CPU_R4X00
>> 361 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 362 select CPU_R4000_WORKAROUNDS if 64BIT
>> 363 select CPU_R4400_WORKAROUNDS if 64BIT
>> 364 select DMA_NONCOHERENT
>> 365 select NO_IOPORT_MAP
>> 366 select IRQ_MIPS_CPU
>> 367 select SYS_HAS_CPU_R3000
>> 368 select SYS_HAS_CPU_R4X00
>> 369 select SYS_SUPPORTS_32BIT_KERNEL
>> 370 select SYS_SUPPORTS_64BIT_KERNEL
>> 371 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 372 select SYS_SUPPORTS_128HZ
>> 373 select SYS_SUPPORTS_256HZ
>> 374 select SYS_SUPPORTS_1024HZ
>> 375 select MIPS_L1_CACHE_SHIFT_4
>> 376 help
>> 377 This enables support for DEC's MIPS based workstations. For details
>> 378 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 379 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 380
>> 381 If you have one of the following DECstation Models you definitely
>> 382 want to choose R4xx0 for the CPU Type:
>> 383
>> 384 DECstation 5000/50
>> 385 DECstation 5000/150
>> 386 DECstation 5000/260
>> 387 DECsystem 5900/260
>> 388
>> 389 otherwise choose R3000.
>> 390
>> 391 config MACH_JAZZ
>> 392 bool "Jazz family of machines"
>> 393 select ARC_MEMORY
>> 394 select ARC_PROMLIB
>> 395 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 396 select ARCH_MIGHT_HAVE_PC_SERIO
>> 397 select DMA_OPS
>> 398 select FW_ARC
>> 399 select FW_ARC32
>> 400 select ARCH_MAY_HAVE_PC_FDC
>> 401 select CEVT_R4K
>> 402 select CSRC_R4K
>> 403 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 404 select GENERIC_ISA_DMA
>> 405 select HAVE_PCSPKR_PLATFORM
>> 406 select IRQ_MIPS_CPU
>> 407 select I8253
>> 408 select I8259
>> 409 select ISA
>> 410 select SYS_HAS_CPU_R4X00
>> 411 select SYS_SUPPORTS_32BIT_KERNEL
>> 412 select SYS_SUPPORTS_64BIT_KERNEL
>> 413 select SYS_SUPPORTS_100HZ
>> 414 help
>> 415 This a family of machines based on the MIPS R4030 chipset which was
>> 416 used by several vendors to build RISC/os and Windows NT workstations.
>> 417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 418 Olivetti M700-10 workstations.
>> 419
>> 420 config MACH_INGENIC_SOC
>> 421 bool "Ingenic SoC based machines"
>> 422 select MIPS_GENERIC
>> 423 select MACH_INGENIC
>> 424 select SYS_SUPPORTS_ZBOOT_UART16550
>> 425 select CPU_SUPPORTS_CPUFREQ
>> 426 select MIPS_EXTERNAL_TIMER
>> 427
>> 428 config LANTIQ
>> 429 bool "Lantiq based platforms"
>> 430 select DMA_NONCOHERENT
>> 431 select IRQ_MIPS_CPU
>> 432 select CEVT_R4K
>> 433 select CSRC_R4K
>> 434 select SYS_HAS_CPU_MIPS32_R1
>> 435 select SYS_HAS_CPU_MIPS32_R2
>> 436 select SYS_SUPPORTS_BIG_ENDIAN
>> 437 select SYS_SUPPORTS_32BIT_KERNEL
>> 438 select SYS_SUPPORTS_MIPS16
>> 439 select SYS_SUPPORTS_MULTITHREADING
>> 440 select SYS_SUPPORTS_VPE_LOADER
>> 441 select SYS_HAS_EARLY_PRINTK
>> 442 select GPIOLIB
>> 443 select SWAP_IO_SPACE
>> 444 select BOOT_RAW
>> 445 select CLKDEV_LOOKUP
>> 446 select HAVE_LEGACY_CLK
>> 447 select USE_OF
>> 448 select PINCTRL
>> 449 select PINCTRL_LANTIQ
>> 450 select ARCH_HAS_RESET_CONTROLLER
>> 451 select RESET_CONTROLLER
>> 452
>> 453 config MACH_LOONGSON32
>> 454 bool "Loongson 32-bit family of machines"
>> 455 select SYS_SUPPORTS_ZBOOT
>> 456 help
>> 457 This enables support for the Loongson-1 family of machines.
>> 458
>> 459 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 460 the Institute of Computing Technology (ICT), Chinese Academy of
>> 461 Sciences (CAS).
>> 462
>> 463 config MACH_LOONGSON2EF
>> 464 bool "Loongson-2E/F family of machines"
>> 465 select SYS_SUPPORTS_ZBOOT
>> 466 help
>> 467 This enables the support of early Loongson-2E/F family of machines.
>> 468
>> 469 config MACH_LOONGSON64
>> 470 bool "Loongson 64-bit family of machines"
>> 471 select ARCH_SPARSEMEM_ENABLE
>> 472 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 473 select ARCH_MIGHT_HAVE_PC_SERIO
>> 474 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 475 select BOOT_ELF32
>> 476 select BOARD_SCACHE
>> 477 select CSRC_R4K
>> 478 select CEVT_R4K
>> 479 select CPU_HAS_WB
>> 480 select FORCE_PCI
>> 481 select ISA
>> 482 select I8259
>> 483 select IRQ_MIPS_CPU
>> 484 select NO_EXCEPT_FILL
>> 485 select NR_CPUS_DEFAULT_64
>> 486 select USE_GENERIC_EARLY_PRINTK_8250
>> 487 select PCI_DRIVERS_GENERIC
>> 488 select SYS_HAS_CPU_LOONGSON64
>> 489 select SYS_HAS_EARLY_PRINTK
>> 490 select SYS_SUPPORTS_SMP
>> 491 select SYS_SUPPORTS_HOTPLUG_CPU
>> 492 select SYS_SUPPORTS_NUMA
>> 493 select SYS_SUPPORTS_64BIT_KERNEL
>> 494 select SYS_SUPPORTS_HIGHMEM
>> 495 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 496 select SYS_SUPPORTS_ZBOOT
>> 497 select ZONE_DMA32
>> 498 select NUMA
>> 499 select SMP
>> 500 select COMMON_CLK
>> 501 select USE_OF
>> 502 select BUILTIN_DTB
>> 503 select PCI_HOST_GENERIC
>> 504 help
>> 505 This enables the support of Loongson-2/3 family of machines.
>> 506
>> 507 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 508 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 509 and Loongson-2F which will be removed), developed by the Institute
>> 510 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 511
>> 512 config MACH_PISTACHIO
>> 513 bool "IMG Pistachio SoC based boards"
>> 514 select BOOT_ELF32
>> 515 select BOOT_RAW
>> 516 select CEVT_R4K
>> 517 select CLKSRC_MIPS_GIC
>> 518 select COMMON_CLK
>> 519 select CSRC_R4K
>> 520 select DMA_NONCOHERENT
>> 521 select GPIOLIB
>> 522 select IRQ_MIPS_CPU
>> 523 select MFD_SYSCON
>> 524 select MIPS_CPU_SCACHE
>> 525 select MIPS_GIC
>> 526 select PINCTRL
>> 527 select REGULATOR
>> 528 select SYS_HAS_CPU_MIPS32_R2
>> 529 select SYS_SUPPORTS_32BIT_KERNEL
>> 530 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 531 select SYS_SUPPORTS_MIPS_CPS
>> 532 select SYS_SUPPORTS_MULTITHREADING
>> 533 select SYS_SUPPORTS_RELOCATABLE
>> 534 select SYS_SUPPORTS_ZBOOT
>> 535 select SYS_HAS_EARLY_PRINTK
>> 536 select USE_GENERIC_EARLY_PRINTK_8250
>> 537 select USE_OF
>> 538 help
>> 539 This enables support for the IMG Pistachio SoC platform.
>> 540
>> 541 config MIPS_MALTA
>> 542 bool "MIPS Malta board"
>> 543 select ARCH_MAY_HAVE_PC_FDC
>> 544 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 545 select ARCH_MIGHT_HAVE_PC_SERIO
>> 546 select BOOT_ELF32
>> 547 select BOOT_RAW
>> 548 select BUILTIN_DTB
>> 549 select CEVT_R4K
>> 550 select CLKSRC_MIPS_GIC
>> 551 select COMMON_CLK
>> 552 select CSRC_R4K
>> 553 select DMA_MAYBE_COHERENT
>> 554 select GENERIC_ISA_DMA
>> 555 select HAVE_PCSPKR_PLATFORM
>> 556 select HAVE_PCI
>> 557 select I8253
>> 558 select I8259
>> 559 select IRQ_MIPS_CPU
>> 560 select MIPS_BONITO64
>> 561 select MIPS_CPU_SCACHE
>> 562 select MIPS_GIC
>> 563 select MIPS_L1_CACHE_SHIFT_6
>> 564 select MIPS_MSC
>> 565 select PCI_GT64XXX_PCI0
>> 566 select SMP_UP if SMP
>> 567 select SWAP_IO_SPACE
>> 568 select SYS_HAS_CPU_MIPS32_R1
>> 569 select SYS_HAS_CPU_MIPS32_R2
>> 570 select SYS_HAS_CPU_MIPS32_R3_5
>> 571 select SYS_HAS_CPU_MIPS32_R5
>> 572 select SYS_HAS_CPU_MIPS32_R6
>> 573 select SYS_HAS_CPU_MIPS64_R1
>> 574 select SYS_HAS_CPU_MIPS64_R2
>> 575 select SYS_HAS_CPU_MIPS64_R6
>> 576 select SYS_HAS_CPU_NEVADA
>> 577 select SYS_HAS_CPU_RM7000
>> 578 select SYS_SUPPORTS_32BIT_KERNEL
>> 579 select SYS_SUPPORTS_64BIT_KERNEL
>> 580 select SYS_SUPPORTS_BIG_ENDIAN
>> 581 select SYS_SUPPORTS_HIGHMEM
>> 582 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 583 select SYS_SUPPORTS_MICROMIPS
>> 584 select SYS_SUPPORTS_MIPS16
>> 585 select SYS_SUPPORTS_MIPS_CMP
>> 586 select SYS_SUPPORTS_MIPS_CPS
>> 587 select SYS_SUPPORTS_MULTITHREADING
>> 588 select SYS_SUPPORTS_RELOCATABLE
>> 589 select SYS_SUPPORTS_SMARTMIPS
>> 590 select SYS_SUPPORTS_VPE_LOADER
>> 591 select SYS_SUPPORTS_ZBOOT
>> 592 select USE_OF
>> 593 select WAR_ICACHE_REFILLS
>> 594 select ZONE_DMA32 if 64BIT
>> 595 help
>> 596 This enables support for the MIPS Technologies Malta evaluation
>> 597 board.
>> 598
>> 599 config MACH_PIC32
>> 600 bool "Microchip PIC32 Family"
>> 601 help
>> 602 This enables support for the Microchip PIC32 family of platforms.
>> 603
>> 604 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 605 microcontrollers.
>> 606
>> 607 config MACH_VR41XX
>> 608 bool "NEC VR4100 series based machines"
>> 609 select CEVT_R4K
>> 610 select CSRC_R4K
>> 611 select SYS_HAS_CPU_VR41XX
>> 612 select SYS_SUPPORTS_MIPS16
>> 613 select GPIOLIB
>> 614
>> 615 config RALINK
>> 616 bool "Ralink based machines"
>> 617 select CEVT_R4K
>> 618 select CSRC_R4K
>> 619 select BOOT_RAW
>> 620 select DMA_NONCOHERENT
>> 621 select IRQ_MIPS_CPU
>> 622 select USE_OF
>> 623 select SYS_HAS_CPU_MIPS32_R1
>> 624 select SYS_HAS_CPU_MIPS32_R2
>> 625 select SYS_SUPPORTS_32BIT_KERNEL
>> 626 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 627 select SYS_SUPPORTS_MIPS16
>> 628 select SYS_SUPPORTS_ZBOOT
>> 629 select SYS_HAS_EARLY_PRINTK
>> 630 select CLKDEV_LOOKUP
>> 631 select ARCH_HAS_RESET_CONTROLLER
>> 632 select RESET_CONTROLLER
>> 633
>> 634 config SGI_IP22
>> 635 bool "SGI IP22 (Indy/Indigo2)"
>> 636 select ARC_MEMORY
>> 637 select ARC_PROMLIB
>> 638 select FW_ARC
>> 639 select FW_ARC32
>> 640 select ARCH_MIGHT_HAVE_PC_SERIO
>> 641 select BOOT_ELF32
>> 642 select CEVT_R4K
>> 643 select CSRC_R4K
>> 644 select DEFAULT_SGI_PARTITION
>> 645 select DMA_NONCOHERENT
>> 646 select HAVE_EISA
>> 647 select I8253
>> 648 select I8259
>> 649 select IP22_CPU_SCACHE
>> 650 select IRQ_MIPS_CPU
>> 651 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 652 select SGI_HAS_I8042
>> 653 select SGI_HAS_INDYDOG
>> 654 select SGI_HAS_HAL2
>> 655 select SGI_HAS_SEEQ
>> 656 select SGI_HAS_WD93
>> 657 select SGI_HAS_ZILOG
>> 658 select SWAP_IO_SPACE
>> 659 select SYS_HAS_CPU_R4X00
>> 660 select SYS_HAS_CPU_R5000
>> 661 select SYS_HAS_EARLY_PRINTK
>> 662 select SYS_SUPPORTS_32BIT_KERNEL
>> 663 select SYS_SUPPORTS_64BIT_KERNEL
>> 664 select SYS_SUPPORTS_BIG_ENDIAN
>> 665 select WAR_R4600_V1_INDEX_ICACHEOP
>> 666 select WAR_R4600_V1_HIT_CACHEOP
>> 667 select WAR_R4600_V2_HIT_CACHEOP
>> 668 select MIPS_L1_CACHE_SHIFT_7
>> 669 help
>> 670 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 671 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 672 that runs on these, say Y here.
>> 673
>> 674 config SGI_IP27
>> 675 bool "SGI IP27 (Origin200/2000)"
>> 676 select ARCH_HAS_PHYS_TO_DMA
>> 677 select ARCH_SPARSEMEM_ENABLE
>> 678 select FW_ARC
>> 679 select FW_ARC64
>> 680 select ARC_CMDLINE_ONLY
>> 681 select BOOT_ELF64
>> 682 select DEFAULT_SGI_PARTITION
>> 683 select SYS_HAS_EARLY_PRINTK
>> 684 select HAVE_PCI
>> 685 select IRQ_MIPS_CPU
>> 686 select IRQ_DOMAIN_HIERARCHY
>> 687 select NR_CPUS_DEFAULT_64
>> 688 select PCI_DRIVERS_GENERIC
>> 689 select PCI_XTALK_BRIDGE
>> 690 select SYS_HAS_CPU_R10000
>> 691 select SYS_SUPPORTS_64BIT_KERNEL
>> 692 select SYS_SUPPORTS_BIG_ENDIAN
>> 693 select SYS_SUPPORTS_NUMA
>> 694 select SYS_SUPPORTS_SMP
>> 695 select WAR_R10000_LLSC
>> 696 select MIPS_L1_CACHE_SHIFT_7
>> 697 select NUMA
>> 698 help
>> 699 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 700 workstations. To compile a Linux kernel that runs on these, say Y
>> 701 here.
>> 702
>> 703 config SGI_IP28
>> 704 bool "SGI IP28 (Indigo2 R10k)"
>> 705 select ARC_MEMORY
>> 706 select ARC_PROMLIB
>> 707 select FW_ARC
>> 708 select FW_ARC64
>> 709 select ARCH_MIGHT_HAVE_PC_SERIO
>> 710 select BOOT_ELF64
>> 711 select CEVT_R4K
>> 712 select CSRC_R4K
>> 713 select DEFAULT_SGI_PARTITION
>> 714 select DMA_NONCOHERENT
>> 715 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 716 select IRQ_MIPS_CPU
>> 717 select HAVE_EISA
>> 718 select I8253
>> 719 select I8259
>> 720 select SGI_HAS_I8042
>> 721 select SGI_HAS_INDYDOG
>> 722 select SGI_HAS_HAL2
>> 723 select SGI_HAS_SEEQ
>> 724 select SGI_HAS_WD93
>> 725 select SGI_HAS_ZILOG
>> 726 select SWAP_IO_SPACE
>> 727 select SYS_HAS_CPU_R10000
>> 728 select SYS_HAS_EARLY_PRINTK
>> 729 select SYS_SUPPORTS_64BIT_KERNEL
>> 730 select SYS_SUPPORTS_BIG_ENDIAN
>> 731 select WAR_R10000_LLSC
>> 732 select MIPS_L1_CACHE_SHIFT_7
>> 733 help
>> 734 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 735 kernel that runs on these, say Y here.
>> 736
>> 737 config SGI_IP30
>> 738 bool "SGI IP30 (Octane/Octane2)"
>> 739 select ARCH_HAS_PHYS_TO_DMA
>> 740 select FW_ARC
>> 741 select FW_ARC64
>> 742 select BOOT_ELF64
>> 743 select CEVT_R4K
>> 744 select CSRC_R4K
>> 745 select SYNC_R4K if SMP
>> 746 select ZONE_DMA32
>> 747 select HAVE_PCI
>> 748 select IRQ_MIPS_CPU
>> 749 select IRQ_DOMAIN_HIERARCHY
>> 750 select NR_CPUS_DEFAULT_2
>> 751 select PCI_DRIVERS_GENERIC
>> 752 select PCI_XTALK_BRIDGE
>> 753 select SYS_HAS_EARLY_PRINTK
>> 754 select SYS_HAS_CPU_R10000
>> 755 select SYS_SUPPORTS_64BIT_KERNEL
>> 756 select SYS_SUPPORTS_BIG_ENDIAN
>> 757 select SYS_SUPPORTS_SMP
>> 758 select WAR_R10000_LLSC
>> 759 select MIPS_L1_CACHE_SHIFT_7
>> 760 select ARC_MEMORY
>> 761 help
>> 762 These are the SGI Octane and Octane2 graphics workstations. To
>> 763 compile a Linux kernel that runs on these, say Y here.
>> 764
>> 765 config SGI_IP32
>> 766 bool "SGI IP32 (O2)"
>> 767 select ARC_MEMORY
>> 768 select ARC_PROMLIB
>> 769 select ARCH_HAS_PHYS_TO_DMA
>> 770 select FW_ARC
>> 771 select FW_ARC32
>> 772 select BOOT_ELF32
>> 773 select CEVT_R4K
>> 774 select CSRC_R4K
>> 775 select DMA_NONCOHERENT
>> 776 select HAVE_PCI
>> 777 select IRQ_MIPS_CPU
>> 778 select R5000_CPU_SCACHE
>> 779 select RM7000_CPU_SCACHE
>> 780 select SYS_HAS_CPU_R5000
>> 781 select SYS_HAS_CPU_R10000 if BROKEN
>> 782 select SYS_HAS_CPU_RM7000
>> 783 select SYS_HAS_CPU_NEVADA
>> 784 select SYS_SUPPORTS_64BIT_KERNEL
>> 785 select SYS_SUPPORTS_BIG_ENDIAN
>> 786 select WAR_ICACHE_REFILLS
>> 787 help
>> 788 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 789
>> 790 config SIBYTE_CRHINE
>> 791 bool "Sibyte BCM91120C-CRhine"
>> 792 select BOOT_ELF32
>> 793 select SIBYTE_BCM1120
>> 794 select SWAP_IO_SPACE
>> 795 select SYS_HAS_CPU_SB1
>> 796 select SYS_SUPPORTS_BIG_ENDIAN
>> 797 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 798
>> 799 config SIBYTE_CARMEL
>> 800 bool "Sibyte BCM91120x-Carmel"
>> 801 select BOOT_ELF32
>> 802 select SIBYTE_BCM1120
>> 803 select SWAP_IO_SPACE
>> 804 select SYS_HAS_CPU_SB1
>> 805 select SYS_SUPPORTS_BIG_ENDIAN
>> 806 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 807
>> 808 config SIBYTE_CRHONE
>> 809 bool "Sibyte BCM91125C-CRhone"
>> 810 select BOOT_ELF32
>> 811 select SIBYTE_BCM1125
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_HIGHMEM
>> 816 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 817
>> 818 config SIBYTE_RHONE
>> 819 bool "Sibyte BCM91125E-Rhone"
>> 820 select BOOT_ELF32
>> 821 select SIBYTE_BCM1125H
>> 822 select SWAP_IO_SPACE
>> 823 select SYS_HAS_CPU_SB1
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 826
>> 827 config SIBYTE_SWARM
>> 828 bool "Sibyte BCM91250A-SWARM"
>> 829 select BOOT_ELF32
>> 830 select HAVE_PATA_PLATFORM
>> 831 select SIBYTE_SB1250
>> 832 select SWAP_IO_SPACE
>> 833 select SYS_HAS_CPU_SB1
>> 834 select SYS_SUPPORTS_BIG_ENDIAN
>> 835 select SYS_SUPPORTS_HIGHMEM
>> 836 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 837 select ZONE_DMA32 if 64BIT
>> 838 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 839
>> 840 config SIBYTE_LITTLESUR
>> 841 bool "Sibyte BCM91250C2-LittleSur"
>> 842 select BOOT_ELF32
>> 843 select HAVE_PATA_PLATFORM
>> 844 select SIBYTE_SB1250
>> 845 select SWAP_IO_SPACE
>> 846 select SYS_HAS_CPU_SB1
>> 847 select SYS_SUPPORTS_BIG_ENDIAN
>> 848 select SYS_SUPPORTS_HIGHMEM
>> 849 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 850 select ZONE_DMA32 if 64BIT
>> 851
>> 852 config SIBYTE_SENTOSA
>> 853 bool "Sibyte BCM91250E-Sentosa"
>> 854 select BOOT_ELF32
>> 855 select SIBYTE_SB1250
>> 856 select SWAP_IO_SPACE
>> 857 select SYS_HAS_CPU_SB1
>> 858 select SYS_SUPPORTS_BIG_ENDIAN
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 861
>> 862 config SIBYTE_BIGSUR
>> 863 bool "Sibyte BCM91480B-BigSur"
>> 864 select BOOT_ELF32
>> 865 select NR_CPUS_DEFAULT_4
>> 866 select SIBYTE_BCM1x80
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_HIGHMEM
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select ZONE_DMA32 if 64BIT
>> 873 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 874
>> 875 config SNI_RM
>> 876 bool "SNI RM200/300/400"
>> 877 select ARC_MEMORY
>> 878 select ARC_PROMLIB
>> 879 select FW_ARC if CPU_LITTLE_ENDIAN
>> 880 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 881 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 882 select ARCH_MAY_HAVE_PC_FDC
>> 883 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 884 select ARCH_MIGHT_HAVE_PC_SERIO
>> 885 select BOOT_ELF32
>> 886 select CEVT_R4K
>> 887 select CSRC_R4K
>> 888 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 889 select DMA_NONCOHERENT
>> 890 select GENERIC_ISA_DMA
>> 891 select HAVE_EISA
>> 892 select HAVE_PCSPKR_PLATFORM
>> 893 select HAVE_PCI
>> 894 select IRQ_MIPS_CPU
>> 895 select I8253
>> 896 select I8259
>> 897 select ISA
>> 898 select MIPS_L1_CACHE_SHIFT_6
>> 899 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 900 select SYS_HAS_CPU_R4X00
>> 901 select SYS_HAS_CPU_R5000
>> 902 select SYS_HAS_CPU_R10000
>> 903 select R5000_CPU_SCACHE
>> 904 select SYS_HAS_EARLY_PRINTK
>> 905 select SYS_SUPPORTS_32BIT_KERNEL
>> 906 select SYS_SUPPORTS_64BIT_KERNEL
>> 907 select SYS_SUPPORTS_BIG_ENDIAN
>> 908 select SYS_SUPPORTS_HIGHMEM
>> 909 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 910 select WAR_R4600_V2_HIT_CACHEOP
>> 911 help
>> 912 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 913 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 914 Technology and now in turn merged with Fujitsu. Say Y here to
>> 915 support this machine type.
>> 916
>> 917 config MACH_TX39XX
>> 918 bool "Toshiba TX39 series based machines"
>> 919
>> 920 config MACH_TX49XX
>> 921 bool "Toshiba TX49 series based machines"
>> 922 select WAR_TX49XX_ICACHE_INDEX_INV
>> 923
>> 924 config MIKROTIK_RB532
>> 925 bool "Mikrotik RB532 boards"
>> 926 select CEVT_R4K
>> 927 select CSRC_R4K
>> 928 select DMA_NONCOHERENT
>> 929 select HAVE_PCI
>> 930 select IRQ_MIPS_CPU
>> 931 select SYS_HAS_CPU_MIPS32_R1
>> 932 select SYS_SUPPORTS_32BIT_KERNEL
>> 933 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 934 select SWAP_IO_SPACE
>> 935 select BOOT_RAW
>> 936 select GPIOLIB
>> 937 select MIPS_L1_CACHE_SHIFT_4
>> 938 help
>> 939 Support the Mikrotik(tm) RouterBoard 532 series,
>> 940 based on the IDT RC32434 SoC.
>> 941
>> 942 config CAVIUM_OCTEON_SOC
>> 943 bool "Cavium Networks Octeon SoC based boards"
>> 944 select CEVT_R4K
>> 945 select ARCH_HAS_PHYS_TO_DMA
>> 946 select HAVE_RAPIDIO
>> 947 select PHYS_ADDR_T_64BIT
>> 948 select SYS_SUPPORTS_64BIT_KERNEL
>> 949 select SYS_SUPPORTS_BIG_ENDIAN
>> 950 select EDAC_SUPPORT
>> 951 select EDAC_ATOMIC_SCRUB
>> 952 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 953 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 954 select SYS_HAS_EARLY_PRINTK
>> 955 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 956 select HAVE_PCI
>> 957 select HAVE_PLAT_DELAY
>> 958 select HAVE_PLAT_FW_INIT_CMDLINE
>> 959 select HAVE_PLAT_MEMCPY
>> 960 select ZONE_DMA32
>> 961 select HOLES_IN_ZONE
>> 962 select GPIOLIB
>> 963 select USE_OF
>> 964 select ARCH_SPARSEMEM_ENABLE
>> 965 select SYS_SUPPORTS_SMP
>> 966 select NR_CPUS_DEFAULT_64
>> 967 select MIPS_NR_CPU_NR_MAP_1024
>> 968 select BUILTIN_DTB
>> 969 select MTD_COMPLEX_MAPPINGS
>> 970 select SWIOTLB
>> 971 select SYS_SUPPORTS_RELOCATABLE
>> 972 help
>> 973 This option supports all of the Octeon reference boards from Cavium
>> 974 Networks. It builds a kernel that dynamically determines the Octeon
>> 975 CPU type and supports all known board reference implementations.
>> 976 Some of the supported boards are:
>> 977 EBT3000
>> 978 EBH3000
>> 979 EBH3100
>> 980 Thunder
>> 981 Kodama
>> 982 Hikari
>> 983 Say Y here for most Octeon reference boards.
>> 984
>> 985 config NLM_XLR_BOARD
>> 986 bool "Netlogic XLR/XLS based systems"
>> 987 select BOOT_ELF32
>> 988 select NLM_COMMON
>> 989 select SYS_HAS_CPU_XLR
>> 990 select SYS_SUPPORTS_SMP
>> 991 select HAVE_PCI
>> 992 select SWAP_IO_SPACE
>> 993 select SYS_SUPPORTS_32BIT_KERNEL
>> 994 select SYS_SUPPORTS_64BIT_KERNEL
>> 995 select PHYS_ADDR_T_64BIT
>> 996 select SYS_SUPPORTS_BIG_ENDIAN
>> 997 select SYS_SUPPORTS_HIGHMEM
>> 998 select NR_CPUS_DEFAULT_32
>> 999 select CEVT_R4K
>> 1000 select CSRC_R4K
>> 1001 select IRQ_MIPS_CPU
>> 1002 select ZONE_DMA32 if 64BIT
>> 1003 select SYNC_R4K
>> 1004 select SYS_HAS_EARLY_PRINTK
>> 1005 select SYS_SUPPORTS_ZBOOT
>> 1006 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1007 help
>> 1008 Support for systems based on Netlogic XLR and XLS processors.
>> 1009 Say Y here if you have a XLR or XLS based board.
>> 1010
>> 1011 config NLM_XLP_BOARD
>> 1012 bool "Netlogic XLP based systems"
>> 1013 select BOOT_ELF32
>> 1014 select NLM_COMMON
>> 1015 select SYS_HAS_CPU_XLP
>> 1016 select SYS_SUPPORTS_SMP
>> 1017 select HAVE_PCI
>> 1018 select SYS_SUPPORTS_32BIT_KERNEL
>> 1019 select SYS_SUPPORTS_64BIT_KERNEL
>> 1020 select PHYS_ADDR_T_64BIT
>> 1021 select GPIOLIB
>> 1022 select SYS_SUPPORTS_BIG_ENDIAN
>> 1023 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1024 select SYS_SUPPORTS_HIGHMEM
>> 1025 select NR_CPUS_DEFAULT_32
>> 1026 select CEVT_R4K
>> 1027 select CSRC_R4K
>> 1028 select IRQ_MIPS_CPU
>> 1029 select ZONE_DMA32 if 64BIT
>> 1030 select SYNC_R4K
>> 1031 select SYS_HAS_EARLY_PRINTK
>> 1032 select USE_OF
>> 1033 select SYS_SUPPORTS_ZBOOT
>> 1034 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1035 help
>> 1036 This board is based on Netlogic XLP Processor.
>> 1037 Say Y here if you have a XLP based board.
>> 1038
>> 1039 endchoice
>> 1040
>> 1041 source "arch/mips/alchemy/Kconfig"
>> 1042 source "arch/mips/ath25/Kconfig"
>> 1043 source "arch/mips/ath79/Kconfig"
>> 1044 source "arch/mips/bcm47xx/Kconfig"
>> 1045 source "arch/mips/bcm63xx/Kconfig"
>> 1046 source "arch/mips/bmips/Kconfig"
>> 1047 source "arch/mips/generic/Kconfig"
>> 1048 source "arch/mips/ingenic/Kconfig"
>> 1049 source "arch/mips/jazz/Kconfig"
>> 1050 source "arch/mips/lantiq/Kconfig"
>> 1051 source "arch/mips/pic32/Kconfig"
>> 1052 source "arch/mips/pistachio/Kconfig"
>> 1053 source "arch/mips/ralink/Kconfig"
>> 1054 source "arch/mips/sgi-ip27/Kconfig"
>> 1055 source "arch/mips/sibyte/Kconfig"
>> 1056 source "arch/mips/txx9/Kconfig"
>> 1057 source "arch/mips/vr41xx/Kconfig"
>> 1058 source "arch/mips/cavium-octeon/Kconfig"
>> 1059 source "arch/mips/loongson2ef/Kconfig"
>> 1060 source "arch/mips/loongson32/Kconfig"
>> 1061 source "arch/mips/loongson64/Kconfig"
>> 1062 source "arch/mips/netlogic/Kconfig"
>> 1063
>> 1064 endmenu
50 1065
51 config GENERIC_HWEIGHT 1066 config GENERIC_HWEIGHT
52 def_bool y !! 1067 bool
>> 1068 default y
>> 1069
>> 1070 config GENERIC_CALIBRATE_DELAY
>> 1071 bool
>> 1072 default y
>> 1073
>> 1074 config SCHED_OMIT_FRAME_POINTER
>> 1075 bool
>> 1076 default y
>> 1077
>> 1078 #
>> 1079 # Select some configuration options automatically based on user selections.
>> 1080 #
>> 1081 config FW_ARC
>> 1082 bool
>> 1083
>> 1084 config ARCH_MAY_HAVE_PC_FDC
>> 1085 bool
>> 1086
>> 1087 config BOOT_RAW
>> 1088 bool
>> 1089
>> 1090 config CEVT_BCM1480
>> 1091 bool
>> 1092
>> 1093 config CEVT_DS1287
>> 1094 bool
>> 1095
>> 1096 config CEVT_GT641XX
>> 1097 bool
>> 1098
>> 1099 config CEVT_R4K
>> 1100 bool
>> 1101
>> 1102 config CEVT_SB1250
>> 1103 bool
>> 1104
>> 1105 config CEVT_TXX9
>> 1106 bool
>> 1107
>> 1108 config CSRC_BCM1480
>> 1109 bool
>> 1110
>> 1111 config CSRC_IOASIC
>> 1112 bool
>> 1113
>> 1114 config CSRC_R4K
>> 1115 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1116 bool
>> 1117
>> 1118 config CSRC_SB1250
>> 1119 bool
>> 1120
>> 1121 config MIPS_CLOCK_VSYSCALL
>> 1122 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1123
>> 1124 config GPIO_TXX9
>> 1125 select GPIOLIB
>> 1126 bool
>> 1127
>> 1128 config FW_CFE
>> 1129 bool
>> 1130
>> 1131 config ARCH_SUPPORTS_UPROBES
>> 1132 bool
>> 1133
>> 1134 config DMA_MAYBE_COHERENT
>> 1135 select ARCH_HAS_DMA_COHERENCE_H
>> 1136 select DMA_NONCOHERENT
>> 1137 bool
>> 1138
>> 1139 config DMA_PERDEV_COHERENT
>> 1140 bool
>> 1141 select ARCH_HAS_SETUP_DMA_OPS
>> 1142 select DMA_NONCOHERENT
>> 1143
>> 1144 config DMA_NONCOHERENT
>> 1145 bool
>> 1146 #
>> 1147 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1148 # Attribute bits. It is believed that the uncached access through
>> 1149 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1150 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1151 # significant advantages.
>> 1152 #
>> 1153 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1154 select ARCH_HAS_DMA_PREP_COHERENT
>> 1155 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1156 select ARCH_HAS_DMA_SET_UNCACHED
>> 1157 select DMA_NONCOHERENT_MMAP
>> 1158 select NEED_DMA_MAP_STATE
>> 1159
>> 1160 config SYS_HAS_EARLY_PRINTK
>> 1161 bool
>> 1162
>> 1163 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1164 bool
>> 1165
>> 1166 config MIPS_BONITO64
>> 1167 bool
>> 1168
>> 1169 config MIPS_MSC
>> 1170 bool
>> 1171
>> 1172 config SYNC_R4K
>> 1173 bool
53 1174
54 config NO_IOPORT_MAP 1175 config NO_IOPORT_MAP
55 def_bool y !! 1176 def_bool n
56 1177
57 # For now, use generic checksum functions <<
58 #These can be reimplemented in assembly later <<
59 config GENERIC_CSUM 1178 config GENERIC_CSUM
60 def_bool y !! 1179 def_bool CPU_NO_LOAD_STORE_LR
61 1180
62 config STACKTRACE_SUPPORT !! 1181 config GENERIC_ISA_DMA
>> 1182 bool
>> 1183 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1184 select ISA_DMA_API
>> 1185
>> 1186 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1187 bool
>> 1188 select GENERIC_ISA_DMA
>> 1189
>> 1190 config HAVE_PLAT_DELAY
>> 1191 bool
>> 1192
>> 1193 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1194 bool
>> 1195
>> 1196 config HAVE_PLAT_MEMCPY
>> 1197 bool
>> 1198
>> 1199 config ISA_DMA_API
>> 1200 bool
>> 1201
>> 1202 config HOLES_IN_ZONE
>> 1203 bool
>> 1204
>> 1205 config SYS_SUPPORTS_RELOCATABLE
>> 1206 bool
>> 1207 help
>> 1208 Selected if the platform supports relocating the kernel.
>> 1209 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1210 to allow access to command line and entropy sources.
>> 1211
>> 1212 config MIPS_CBPF_JIT
63 def_bool y 1213 def_bool y
>> 1214 depends on BPF_JIT && HAVE_CBPF_JIT
64 1215
65 config LOCKDEP_SUPPORT !! 1216 config MIPS_EBPF_JIT
66 def_bool y !! 1217 def_bool y
>> 1218 depends on BPF_JIT && HAVE_EBPF_JIT
67 1219
68 menu "Processor type and features" <<
69 1220
>> 1221 #
>> 1222 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1223 # answer,so we try hard to limit the available choices. Also the use of a
>> 1224 # choice statement should be more obvious to the user.
>> 1225 #
70 choice 1226 choice
71 prompt "Subarchitecture" !! 1227 prompt "Endianness selection"
72 default OR1K_1200 <<
73 <<
74 config OR1K_1200 <<
75 bool "OR1200" <<
76 help 1228 help
77 Generic OpenRISC 1200 architecture !! 1229 Some MIPS machines can be configured for either little or big endian
>> 1230 byte order. These modes require different kernels and a different
>> 1231 Linux distribution. In general there is one preferred byteorder for a
>> 1232 particular system but some systems are just as commonly used in the
>> 1233 one or the other endianness.
>> 1234
>> 1235 config CPU_BIG_ENDIAN
>> 1236 bool "Big endian"
>> 1237 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1238
>> 1239 config CPU_LITTLE_ENDIAN
>> 1240 bool "Little endian"
>> 1241 depends on SYS_SUPPORTS_LITTLE_ENDIAN
78 1242
79 endchoice 1243 endchoice
80 1244
81 config DCACHE_WRITETHROUGH !! 1245 config EXPORT_UASM
82 bool "Have write through data caches" !! 1246 bool
>> 1247
>> 1248 config SYS_SUPPORTS_APM_EMULATION
>> 1249 bool
>> 1250
>> 1251 config SYS_SUPPORTS_BIG_ENDIAN
>> 1252 bool
>> 1253
>> 1254 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1255 bool
>> 1256
>> 1257 config SYS_SUPPORTS_HUGETLBFS
>> 1258 bool
>> 1259 depends on CPU_SUPPORTS_HUGEPAGES
>> 1260 default y
>> 1261
>> 1262 config MIPS_HUGE_TLB_SUPPORT
>> 1263 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1264
>> 1265 config IRQ_CPU_RM7K
>> 1266 bool
>> 1267
>> 1268 config IRQ_MSP_SLP
>> 1269 bool
>> 1270
>> 1271 config IRQ_MSP_CIC
>> 1272 bool
>> 1273
>> 1274 config IRQ_TXX9
>> 1275 bool
>> 1276
>> 1277 config IRQ_GT641XX
>> 1278 bool
>> 1279
>> 1280 config PCI_GT64XXX_PCI0
>> 1281 bool
>> 1282
>> 1283 config PCI_XTALK_BRIDGE
>> 1284 bool
>> 1285
>> 1286 config NO_EXCEPT_FILL
>> 1287 bool
>> 1288
>> 1289 config MIPS_SPRAM
>> 1290 bool
>> 1291
>> 1292 config SWAP_IO_SPACE
>> 1293 bool
>> 1294
>> 1295 config SGI_HAS_INDYDOG
>> 1296 bool
>> 1297
>> 1298 config SGI_HAS_HAL2
>> 1299 bool
>> 1300
>> 1301 config SGI_HAS_SEEQ
>> 1302 bool
>> 1303
>> 1304 config SGI_HAS_WD93
>> 1305 bool
>> 1306
>> 1307 config SGI_HAS_ZILOG
>> 1308 bool
>> 1309
>> 1310 config SGI_HAS_I8042
>> 1311 bool
>> 1312
>> 1313 config DEFAULT_SGI_PARTITION
>> 1314 bool
>> 1315
>> 1316 config FW_ARC32
>> 1317 bool
>> 1318
>> 1319 config FW_SNIPROM
>> 1320 bool
>> 1321
>> 1322 config BOOT_ELF32
>> 1323 bool
>> 1324
>> 1325 config MIPS_L1_CACHE_SHIFT_4
>> 1326 bool
>> 1327
>> 1328 config MIPS_L1_CACHE_SHIFT_5
>> 1329 bool
>> 1330
>> 1331 config MIPS_L1_CACHE_SHIFT_6
>> 1332 bool
>> 1333
>> 1334 config MIPS_L1_CACHE_SHIFT_7
>> 1335 bool
>> 1336
>> 1337 config MIPS_L1_CACHE_SHIFT
>> 1338 int
>> 1339 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1340 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1341 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1342 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1343 default "5"
>> 1344
>> 1345 config ARC_CMDLINE_ONLY
>> 1346 bool
>> 1347
>> 1348 config ARC_CONSOLE
>> 1349 bool "ARC console support"
>> 1350 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1351
>> 1352 config ARC_MEMORY
>> 1353 bool
>> 1354
>> 1355 config ARC_PROMLIB
>> 1356 bool
>> 1357
>> 1358 config FW_ARC64
>> 1359 bool
>> 1360
>> 1361 config BOOT_ELF64
>> 1362 bool
>> 1363
>> 1364 menu "CPU selection"
>> 1365
>> 1366 choice
>> 1367 prompt "CPU type"
>> 1368 default CPU_R4X00
>> 1369
>> 1370 config CPU_LOONGSON64
>> 1371 bool "Loongson 64-bit CPU"
>> 1372 depends on SYS_HAS_CPU_LOONGSON64
>> 1373 select ARCH_HAS_PHYS_TO_DMA
>> 1374 select CPU_MIPSR2
>> 1375 select CPU_HAS_PREFETCH
>> 1376 select CPU_SUPPORTS_64BIT_KERNEL
>> 1377 select CPU_SUPPORTS_HIGHMEM
>> 1378 select CPU_SUPPORTS_HUGEPAGES
>> 1379 select CPU_SUPPORTS_MSA
>> 1380 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1381 select CPU_MIPSR2_IRQ_VI
>> 1382 select WEAK_ORDERING
>> 1383 select WEAK_REORDERING_BEYOND_LLSC
>> 1384 select MIPS_ASID_BITS_VARIABLE
>> 1385 select MIPS_PGD_C0_CONTEXT
>> 1386 select MIPS_L1_CACHE_SHIFT_6
>> 1387 select MIPS_FP_SUPPORT
>> 1388 select GPIOLIB
>> 1389 select SWIOTLB
>> 1390 select HAVE_KVM
>> 1391 help
>> 1392 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1393 cores implements the MIPS64R2 instruction set with many extensions,
>> 1394 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1395 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1396 Loongson-2E/2F is not covered here and will be removed in future.
>> 1397
>> 1398 config LOONGSON3_ENHANCEMENT
>> 1399 bool "New Loongson-3 CPU Enhancements"
83 default n 1400 default n
>> 1401 depends on CPU_LOONGSON64
84 help 1402 help
85 Select this if your implementation f !! 1403 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
86 Selecting 'N' here will allow the ke !! 1404 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
87 caches at relevant times. Most OpenR !! 1405 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
88 through data caches. !! 1406 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1407 Fast TLB refill support, etc.
>> 1408
>> 1409 This option enable those enhancements which are not probed at run
>> 1410 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1411 please say 'N' here. If you want a high-performance kernel to run on
>> 1412 new Loongson-3 machines only, please say 'Y' here.
89 1413
90 If unsure say N here !! 1414 config CPU_LOONGSON3_WORKAROUNDS
>> 1415 bool "Old Loongson-3 LLSC Workarounds"
>> 1416 default y if SMP
>> 1417 depends on CPU_LOONGSON64
>> 1418 help
>> 1419 Loongson-3 processors have the llsc issues which require workarounds.
>> 1420 Without workarounds the system may hang unexpectedly.
91 1421
92 config OPENRISC_BUILTIN_DTB !! 1422 Newer Loongson-3 will fix these issues and no workarounds are needed.
93 string "Builtin DTB" !! 1423 The workarounds have no significant side effect on them but may
94 default "" !! 1424 decrease the performance of the system so this option should be
>> 1425 disabled unless the kernel is intended to be run on old systems.
95 1426
96 menu "Class II Instructions" !! 1427 If unsure, please say Y.
97 1428
98 config OPENRISC_HAVE_INST_FF1 !! 1429 config CPU_LOONGSON3_CPUCFG_EMULATION
99 bool "Have instruction l.ff1" !! 1430 bool "Emulate the CPUCFG instruction on older Loongson cores"
100 default y 1431 default y
>> 1432 depends on CPU_LOONGSON64
>> 1433 help
>> 1434 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1435 userland to query CPU capabilities, much like CPUID on x86. This
>> 1436 option provides emulation of the instruction on older Loongson
>> 1437 cores, back to Loongson-3A1000.
>> 1438
>> 1439 If unsure, please say Y.
>> 1440
>> 1441 config CPU_LOONGSON2E
>> 1442 bool "Loongson 2E"
>> 1443 depends on SYS_HAS_CPU_LOONGSON2E
>> 1444 select CPU_LOONGSON2EF
>> 1445 help
>> 1446 The Loongson 2E processor implements the MIPS III instruction set
>> 1447 with many extensions.
>> 1448
>> 1449 It has an internal FPGA northbridge, which is compatible to
>> 1450 bonito64.
>> 1451
>> 1452 config CPU_LOONGSON2F
>> 1453 bool "Loongson 2F"
>> 1454 depends on SYS_HAS_CPU_LOONGSON2F
>> 1455 select CPU_LOONGSON2EF
>> 1456 select GPIOLIB
>> 1457 help
>> 1458 The Loongson 2F processor implements the MIPS III instruction set
>> 1459 with many extensions.
>> 1460
>> 1461 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1462 have a similar programming interface with FPGA northbridge used in
>> 1463 Loongson2E.
>> 1464
>> 1465 config CPU_LOONGSON1B
>> 1466 bool "Loongson 1B"
>> 1467 depends on SYS_HAS_CPU_LOONGSON1B
>> 1468 select CPU_LOONGSON32
>> 1469 select LEDS_GPIO_REGISTER
>> 1470 help
>> 1471 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1472 Release 1 instruction set and part of the MIPS32 Release 2
>> 1473 instruction set.
>> 1474
>> 1475 config CPU_LOONGSON1C
>> 1476 bool "Loongson 1C"
>> 1477 depends on SYS_HAS_CPU_LOONGSON1C
>> 1478 select CPU_LOONGSON32
>> 1479 select LEDS_GPIO_REGISTER
>> 1480 help
>> 1481 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1482 Release 1 instruction set and part of the MIPS32 Release 2
>> 1483 instruction set.
>> 1484
>> 1485 config CPU_MIPS32_R1
>> 1486 bool "MIPS32 Release 1"
>> 1487 depends on SYS_HAS_CPU_MIPS32_R1
>> 1488 select CPU_HAS_PREFETCH
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_HIGHMEM
>> 1491 help
>> 1492 Choose this option to build a kernel for release 1 or later of the
>> 1493 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1494 MIPS processor are based on a MIPS32 processor. If you know the
>> 1495 specific type of processor in your system, choose those that one
>> 1496 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1497 Release 2 of the MIPS32 architecture is available since several
>> 1498 years so chances are you even have a MIPS32 Release 2 processor
>> 1499 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1500 performance.
>> 1501
>> 1502 config CPU_MIPS32_R2
>> 1503 bool "MIPS32 Release 2"
>> 1504 depends on SYS_HAS_CPU_MIPS32_R2
>> 1505 select CPU_HAS_PREFETCH
>> 1506 select CPU_SUPPORTS_32BIT_KERNEL
>> 1507 select CPU_SUPPORTS_HIGHMEM
>> 1508 select CPU_SUPPORTS_MSA
>> 1509 select HAVE_KVM
>> 1510 help
>> 1511 Choose this option to build a kernel for release 2 or later of the
>> 1512 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1513 MIPS processor are based on a MIPS32 processor. If you know the
>> 1514 specific type of processor in your system, choose those that one
>> 1515 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1516
>> 1517 config CPU_MIPS32_R5
>> 1518 bool "MIPS32 Release 5"
>> 1519 depends on SYS_HAS_CPU_MIPS32_R5
>> 1520 select CPU_HAS_PREFETCH
>> 1521 select CPU_SUPPORTS_32BIT_KERNEL
>> 1522 select CPU_SUPPORTS_HIGHMEM
>> 1523 select CPU_SUPPORTS_MSA
>> 1524 select HAVE_KVM
>> 1525 select MIPS_O32_FP64_SUPPORT
>> 1526 help
>> 1527 Choose this option to build a kernel for release 5 or later of the
>> 1528 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1529 family, are based on a MIPS32r5 processor. If you own an older
>> 1530 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1531
>> 1532 config CPU_MIPS32_R6
>> 1533 bool "MIPS32 Release 6"
>> 1534 depends on SYS_HAS_CPU_MIPS32_R6
>> 1535 select CPU_HAS_PREFETCH
>> 1536 select CPU_NO_LOAD_STORE_LR
>> 1537 select CPU_SUPPORTS_32BIT_KERNEL
>> 1538 select CPU_SUPPORTS_HIGHMEM
>> 1539 select CPU_SUPPORTS_MSA
>> 1540 select HAVE_KVM
>> 1541 select MIPS_O32_FP64_SUPPORT
>> 1542 help
>> 1543 Choose this option to build a kernel for release 6 or later of the
>> 1544 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1545 family, are based on a MIPS32r6 processor. If you own an older
>> 1546 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1547
>> 1548 config CPU_MIPS64_R1
>> 1549 bool "MIPS64 Release 1"
>> 1550 depends on SYS_HAS_CPU_MIPS64_R1
>> 1551 select CPU_HAS_PREFETCH
>> 1552 select CPU_SUPPORTS_32BIT_KERNEL
>> 1553 select CPU_SUPPORTS_64BIT_KERNEL
>> 1554 select CPU_SUPPORTS_HIGHMEM
>> 1555 select CPU_SUPPORTS_HUGEPAGES
>> 1556 help
>> 1557 Choose this option to build a kernel for release 1 or later of the
>> 1558 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1559 MIPS processor are based on a MIPS64 processor. If you know the
>> 1560 specific type of processor in your system, choose those that one
>> 1561 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1562 Release 2 of the MIPS64 architecture is available since several
>> 1563 years so chances are you even have a MIPS64 Release 2 processor
>> 1564 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1565 performance.
>> 1566
>> 1567 config CPU_MIPS64_R2
>> 1568 bool "MIPS64 Release 2"
>> 1569 depends on SYS_HAS_CPU_MIPS64_R2
>> 1570 select CPU_HAS_PREFETCH
>> 1571 select CPU_SUPPORTS_32BIT_KERNEL
>> 1572 select CPU_SUPPORTS_64BIT_KERNEL
>> 1573 select CPU_SUPPORTS_HIGHMEM
>> 1574 select CPU_SUPPORTS_HUGEPAGES
>> 1575 select CPU_SUPPORTS_MSA
>> 1576 select HAVE_KVM
>> 1577 help
>> 1578 Choose this option to build a kernel for release 2 or later of the
>> 1579 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1580 MIPS processor are based on a MIPS64 processor. If you know the
>> 1581 specific type of processor in your system, choose those that one
>> 1582 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1583
>> 1584 config CPU_MIPS64_R5
>> 1585 bool "MIPS64 Release 5"
>> 1586 depends on SYS_HAS_CPU_MIPS64_R5
>> 1587 select CPU_HAS_PREFETCH
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HIGHMEM
>> 1591 select CPU_SUPPORTS_HUGEPAGES
>> 1592 select CPU_SUPPORTS_MSA
>> 1593 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1594 select HAVE_KVM
>> 1595 help
>> 1596 Choose this option to build a kernel for release 5 or later of the
>> 1597 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1598 release partly implementing release 6 features. Though there is no
>> 1599 any hardware known to be based on this release.
>> 1600
>> 1601 config CPU_MIPS64_R6
>> 1602 bool "MIPS64 Release 6"
>> 1603 depends on SYS_HAS_CPU_MIPS64_R6
>> 1604 select CPU_HAS_PREFETCH
>> 1605 select CPU_NO_LOAD_STORE_LR
>> 1606 select CPU_SUPPORTS_32BIT_KERNEL
>> 1607 select CPU_SUPPORTS_64BIT_KERNEL
>> 1608 select CPU_SUPPORTS_HIGHMEM
>> 1609 select CPU_SUPPORTS_HUGEPAGES
>> 1610 select CPU_SUPPORTS_MSA
>> 1611 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1612 select HAVE_KVM
>> 1613 help
>> 1614 Choose this option to build a kernel for release 6 or later of the
>> 1615 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1616 family, are based on a MIPS64r6 processor. If you own an older
>> 1617 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1618
>> 1619 config CPU_P5600
>> 1620 bool "MIPS Warrior P5600"
>> 1621 depends on SYS_HAS_CPU_P5600
>> 1622 select CPU_HAS_PREFETCH
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 select CPU_SUPPORTS_HIGHMEM
>> 1625 select CPU_SUPPORTS_MSA
>> 1626 select CPU_SUPPORTS_CPUFREQ
>> 1627 select CPU_MIPSR2_IRQ_VI
>> 1628 select CPU_MIPSR2_IRQ_EI
>> 1629 select HAVE_KVM
>> 1630 select MIPS_O32_FP64_SUPPORT
>> 1631 help
>> 1632 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1633 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1634 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1635 level features like up to six P5600 calculation cores, CM2 with L2
>> 1636 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1637 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1638 eJTAG and PDtrace.
>> 1639
>> 1640 config CPU_R3000
>> 1641 bool "R3000"
>> 1642 depends on SYS_HAS_CPU_R3000
>> 1643 select CPU_HAS_WB
>> 1644 select CPU_R3K_TLB
>> 1645 select CPU_SUPPORTS_32BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HIGHMEM
>> 1647 help
>> 1648 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1649 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1650 *not* work on R4000 machines and vice versa. However, since most
>> 1651 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1652 might be a safe bet. If the resulting kernel does not work,
>> 1653 try to recompile with R3000.
>> 1654
>> 1655 config CPU_TX39XX
>> 1656 bool "R39XX"
>> 1657 depends on SYS_HAS_CPU_TX39XX
>> 1658 select CPU_SUPPORTS_32BIT_KERNEL
>> 1659 select CPU_R3K_TLB
>> 1660
>> 1661 config CPU_VR41XX
>> 1662 bool "R41xx"
>> 1663 depends on SYS_HAS_CPU_VR41XX
>> 1664 select CPU_SUPPORTS_32BIT_KERNEL
>> 1665 select CPU_SUPPORTS_64BIT_KERNEL
>> 1666 help
>> 1667 The options selects support for the NEC VR4100 series of processors.
>> 1668 Only choose this option if you have one of these processors as a
>> 1669 kernel built with this option will not run on any other type of
>> 1670 processor or vice versa.
>> 1671
>> 1672 config CPU_R4X00
>> 1673 bool "R4x00"
>> 1674 depends on SYS_HAS_CPU_R4X00
>> 1675 select CPU_SUPPORTS_32BIT_KERNEL
>> 1676 select CPU_SUPPORTS_64BIT_KERNEL
>> 1677 select CPU_SUPPORTS_HUGEPAGES
>> 1678 help
>> 1679 MIPS Technologies R4000-series processors other than 4300, including
>> 1680 the R4000, R4400, R4600, and 4700.
>> 1681
>> 1682 config CPU_TX49XX
>> 1683 bool "R49XX"
>> 1684 depends on SYS_HAS_CPU_TX49XX
>> 1685 select CPU_HAS_PREFETCH
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select CPU_SUPPORTS_64BIT_KERNEL
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689
>> 1690 config CPU_R5000
>> 1691 bool "R5000"
>> 1692 depends on SYS_HAS_CPU_R5000
>> 1693 select CPU_SUPPORTS_32BIT_KERNEL
>> 1694 select CPU_SUPPORTS_64BIT_KERNEL
>> 1695 select CPU_SUPPORTS_HUGEPAGES
>> 1696 help
>> 1697 MIPS Technologies R5000-series processors other than the Nevada.
>> 1698
>> 1699 config CPU_R5500
>> 1700 bool "R5500"
>> 1701 depends on SYS_HAS_CPU_R5500
>> 1702 select CPU_SUPPORTS_32BIT_KERNEL
>> 1703 select CPU_SUPPORTS_64BIT_KERNEL
>> 1704 select CPU_SUPPORTS_HUGEPAGES
>> 1705 help
>> 1706 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1707 instruction set.
>> 1708
>> 1709 config CPU_NEVADA
>> 1710 bool "RM52xx"
>> 1711 depends on SYS_HAS_CPU_NEVADA
>> 1712 select CPU_SUPPORTS_32BIT_KERNEL
>> 1713 select CPU_SUPPORTS_64BIT_KERNEL
>> 1714 select CPU_SUPPORTS_HUGEPAGES
>> 1715 help
>> 1716 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1717
>> 1718 config CPU_R10000
>> 1719 bool "R10000"
>> 1720 depends on SYS_HAS_CPU_R10000
>> 1721 select CPU_HAS_PREFETCH
>> 1722 select CPU_SUPPORTS_32BIT_KERNEL
>> 1723 select CPU_SUPPORTS_64BIT_KERNEL
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select CPU_SUPPORTS_HUGEPAGES
>> 1726 help
>> 1727 MIPS Technologies R10000-series processors.
>> 1728
>> 1729 config CPU_RM7000
>> 1730 bool "RM7000"
>> 1731 depends on SYS_HAS_CPU_RM7000
>> 1732 select CPU_HAS_PREFETCH
>> 1733 select CPU_SUPPORTS_32BIT_KERNEL
>> 1734 select CPU_SUPPORTS_64BIT_KERNEL
>> 1735 select CPU_SUPPORTS_HIGHMEM
>> 1736 select CPU_SUPPORTS_HUGEPAGES
>> 1737
>> 1738 config CPU_SB1
>> 1739 bool "SB1"
>> 1740 depends on SYS_HAS_CPU_SB1
>> 1741 select CPU_SUPPORTS_32BIT_KERNEL
>> 1742 select CPU_SUPPORTS_64BIT_KERNEL
>> 1743 select CPU_SUPPORTS_HIGHMEM
>> 1744 select CPU_SUPPORTS_HUGEPAGES
>> 1745 select WEAK_ORDERING
>> 1746
>> 1747 config CPU_CAVIUM_OCTEON
>> 1748 bool "Cavium Octeon processor"
>> 1749 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1750 select CPU_HAS_PREFETCH
>> 1751 select CPU_SUPPORTS_64BIT_KERNEL
>> 1752 select WEAK_ORDERING
>> 1753 select CPU_SUPPORTS_HIGHMEM
>> 1754 select CPU_SUPPORTS_HUGEPAGES
>> 1755 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1756 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1757 select MIPS_L1_CACHE_SHIFT_7
>> 1758 select HAVE_KVM
101 help 1759 help
102 Select this if your implementation h !! 1760 The Cavium Octeon processor is a highly integrated chip containing
>> 1761 many ethernet hardware widgets for networking tasks. The processor
>> 1762 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1763 Full details can be found at http://www.caviumnetworks.com.
>> 1764
>> 1765 config CPU_BMIPS
>> 1766 bool "Broadcom BMIPS"
>> 1767 depends on SYS_HAS_CPU_BMIPS
>> 1768 select CPU_MIPS32
>> 1769 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1770 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1771 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1772 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1773 select CPU_SUPPORTS_32BIT_KERNEL
>> 1774 select DMA_NONCOHERENT
>> 1775 select IRQ_MIPS_CPU
>> 1776 select SWAP_IO_SPACE
>> 1777 select WEAK_ORDERING
>> 1778 select CPU_SUPPORTS_HIGHMEM
>> 1779 select CPU_HAS_PREFETCH
>> 1780 select CPU_SUPPORTS_CPUFREQ
>> 1781 select MIPS_EXTERNAL_TIMER
>> 1782 help
>> 1783 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1784
>> 1785 config CPU_XLR
>> 1786 bool "Netlogic XLR SoC"
>> 1787 depends on SYS_HAS_CPU_XLR
>> 1788 select CPU_SUPPORTS_32BIT_KERNEL
>> 1789 select CPU_SUPPORTS_64BIT_KERNEL
>> 1790 select CPU_SUPPORTS_HIGHMEM
>> 1791 select CPU_SUPPORTS_HUGEPAGES
>> 1792 select WEAK_ORDERING
>> 1793 select WEAK_REORDERING_BEYOND_LLSC
>> 1794 help
>> 1795 Netlogic Microsystems XLR/XLS processors.
>> 1796
>> 1797 config CPU_XLP
>> 1798 bool "Netlogic XLP SoC"
>> 1799 depends on SYS_HAS_CPU_XLP
>> 1800 select CPU_SUPPORTS_32BIT_KERNEL
>> 1801 select CPU_SUPPORTS_64BIT_KERNEL
>> 1802 select CPU_SUPPORTS_HIGHMEM
>> 1803 select WEAK_ORDERING
>> 1804 select WEAK_REORDERING_BEYOND_LLSC
>> 1805 select CPU_HAS_PREFETCH
>> 1806 select CPU_MIPSR2
>> 1807 select CPU_SUPPORTS_HUGEPAGES
>> 1808 select MIPS_ASID_BITS_VARIABLE
>> 1809 help
>> 1810 Netlogic Microsystems XLP processors.
>> 1811 endchoice
103 1812
104 config OPENRISC_HAVE_INST_FL1 !! 1813 config CPU_MIPS32_3_5_FEATURES
105 bool "Have instruction l.fl1" !! 1814 bool "MIPS32 Release 3.5 Features"
>> 1815 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1816 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1817 CPU_P5600
>> 1818 help
>> 1819 Choose this option to build a kernel for release 2 or later of the
>> 1820 MIPS32 architecture including features from the 3.5 release such as
>> 1821 support for Enhanced Virtual Addressing (EVA).
>> 1822
>> 1823 config CPU_MIPS32_3_5_EVA
>> 1824 bool "Enhanced Virtual Addressing (EVA)"
>> 1825 depends on CPU_MIPS32_3_5_FEATURES
>> 1826 select EVA
106 default y 1827 default y
107 help 1828 help
108 Select this if your implementation h !! 1829 Choose this option if you want to enable the Enhanced Virtual
>> 1830 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1831 One of its primary benefits is an increase in the maximum size
>> 1832 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1833
>> 1834 config CPU_MIPS32_R5_FEATURES
>> 1835 bool "MIPS32 Release 5 Features"
>> 1836 depends on SYS_HAS_CPU_MIPS32_R5
>> 1837 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1838 help
>> 1839 Choose this option to build a kernel for release 2 or later of the
>> 1840 MIPS32 architecture including features from release 5 such as
>> 1841 support for Extended Physical Addressing (XPA).
>> 1842
>> 1843 config CPU_MIPS32_R5_XPA
>> 1844 bool "Extended Physical Addressing (XPA)"
>> 1845 depends on CPU_MIPS32_R5_FEATURES
>> 1846 depends on !EVA
>> 1847 depends on !PAGE_SIZE_4KB
>> 1848 depends on SYS_SUPPORTS_HIGHMEM
>> 1849 select XPA
>> 1850 select HIGHMEM
>> 1851 select PHYS_ADDR_T_64BIT
>> 1852 default n
>> 1853 help
>> 1854 Choose this option if you want to enable the Extended Physical
>> 1855 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1856 benefit is to increase physical addressing equal to or greater
>> 1857 than 40 bits. Note that this has the side effect of turning on
>> 1858 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1859 If unsure, say 'N' here.
>> 1860
>> 1861 if CPU_LOONGSON2F
>> 1862 config CPU_NOP_WORKAROUNDS
>> 1863 bool
109 1864
110 config OPENRISC_HAVE_INST_MUL !! 1865 config CPU_JUMP_WORKAROUNDS
111 bool "Have instruction l.mul for hardw !! 1866 bool
>> 1867
>> 1868 config CPU_LOONGSON2F_WORKAROUNDS
>> 1869 bool "Loongson 2F Workarounds"
112 default y 1870 default y
>> 1871 select CPU_NOP_WORKAROUNDS
>> 1872 select CPU_JUMP_WORKAROUNDS
>> 1873 help
>> 1874 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1875 require workarounds. Without workarounds the system may hang
>> 1876 unexpectedly. For more information please refer to the gas
>> 1877 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1878
>> 1879 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1880 are needed. The workarounds have no significant side effect on them
>> 1881 but may decrease the performance of the system so this option should
>> 1882 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1883 systems.
>> 1884
>> 1885 If unsure, please say Y.
>> 1886 endif # CPU_LOONGSON2F
>> 1887
>> 1888 config SYS_SUPPORTS_ZBOOT
>> 1889 bool
>> 1890 select HAVE_KERNEL_GZIP
>> 1891 select HAVE_KERNEL_BZIP2
>> 1892 select HAVE_KERNEL_LZ4
>> 1893 select HAVE_KERNEL_LZMA
>> 1894 select HAVE_KERNEL_LZO
>> 1895 select HAVE_KERNEL_XZ
>> 1896 select HAVE_KERNEL_ZSTD
>> 1897
>> 1898 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1899 bool
>> 1900 select SYS_SUPPORTS_ZBOOT
>> 1901
>> 1902 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1903 bool
>> 1904 select SYS_SUPPORTS_ZBOOT
>> 1905
>> 1906 config CPU_LOONGSON2EF
>> 1907 bool
>> 1908 select CPU_SUPPORTS_32BIT_KERNEL
>> 1909 select CPU_SUPPORTS_64BIT_KERNEL
>> 1910 select CPU_SUPPORTS_HIGHMEM
>> 1911 select CPU_SUPPORTS_HUGEPAGES
>> 1912 select ARCH_HAS_PHYS_TO_DMA
>> 1913
>> 1914 config CPU_LOONGSON32
>> 1915 bool
>> 1916 select CPU_MIPS32
>> 1917 select CPU_MIPSR2
>> 1918 select CPU_HAS_PREFETCH
>> 1919 select CPU_SUPPORTS_32BIT_KERNEL
>> 1920 select CPU_SUPPORTS_HIGHMEM
>> 1921 select CPU_SUPPORTS_CPUFREQ
>> 1922
>> 1923 config CPU_BMIPS32_3300
>> 1924 select SMP_UP if SMP
>> 1925 bool
>> 1926
>> 1927 config CPU_BMIPS4350
>> 1928 bool
>> 1929 select SYS_SUPPORTS_SMP
>> 1930 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1931
>> 1932 config CPU_BMIPS4380
>> 1933 bool
>> 1934 select MIPS_L1_CACHE_SHIFT_6
>> 1935 select SYS_SUPPORTS_SMP
>> 1936 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1937 select CPU_HAS_RIXI
>> 1938
>> 1939 config CPU_BMIPS5000
>> 1940 bool
>> 1941 select MIPS_CPU_SCACHE
>> 1942 select MIPS_L1_CACHE_SHIFT_7
>> 1943 select SYS_SUPPORTS_SMP
>> 1944 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1945 select CPU_HAS_RIXI
>> 1946
>> 1947 config SYS_HAS_CPU_LOONGSON64
>> 1948 bool
>> 1949 select CPU_SUPPORTS_CPUFREQ
>> 1950 select CPU_HAS_RIXI
>> 1951
>> 1952 config SYS_HAS_CPU_LOONGSON2E
>> 1953 bool
>> 1954
>> 1955 config SYS_HAS_CPU_LOONGSON2F
>> 1956 bool
>> 1957 select CPU_SUPPORTS_CPUFREQ
>> 1958 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1959
>> 1960 config SYS_HAS_CPU_LOONGSON1B
>> 1961 bool
>> 1962
>> 1963 config SYS_HAS_CPU_LOONGSON1C
>> 1964 bool
>> 1965
>> 1966 config SYS_HAS_CPU_MIPS32_R1
>> 1967 bool
>> 1968
>> 1969 config SYS_HAS_CPU_MIPS32_R2
>> 1970 bool
>> 1971
>> 1972 config SYS_HAS_CPU_MIPS32_R3_5
>> 1973 bool
>> 1974
>> 1975 config SYS_HAS_CPU_MIPS32_R5
>> 1976 bool
>> 1977 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1978
>> 1979 config SYS_HAS_CPU_MIPS32_R6
>> 1980 bool
>> 1981 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1982
>> 1983 config SYS_HAS_CPU_MIPS64_R1
>> 1984 bool
>> 1985
>> 1986 config SYS_HAS_CPU_MIPS64_R2
>> 1987 bool
>> 1988
>> 1989 config SYS_HAS_CPU_MIPS64_R5
>> 1990 bool
>> 1991 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1992
>> 1993 config SYS_HAS_CPU_MIPS64_R6
>> 1994 bool
>> 1995 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1996
>> 1997 config SYS_HAS_CPU_P5600
>> 1998 bool
>> 1999 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2000
>> 2001 config SYS_HAS_CPU_R3000
>> 2002 bool
>> 2003
>> 2004 config SYS_HAS_CPU_TX39XX
>> 2005 bool
>> 2006
>> 2007 config SYS_HAS_CPU_VR41XX
>> 2008 bool
>> 2009
>> 2010 config SYS_HAS_CPU_R4X00
>> 2011 bool
>> 2012
>> 2013 config SYS_HAS_CPU_TX49XX
>> 2014 bool
>> 2015
>> 2016 config SYS_HAS_CPU_R5000
>> 2017 bool
>> 2018
>> 2019 config SYS_HAS_CPU_R5500
>> 2020 bool
>> 2021
>> 2022 config SYS_HAS_CPU_NEVADA
>> 2023 bool
>> 2024
>> 2025 config SYS_HAS_CPU_R10000
>> 2026 bool
>> 2027 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2028
>> 2029 config SYS_HAS_CPU_RM7000
>> 2030 bool
>> 2031
>> 2032 config SYS_HAS_CPU_SB1
>> 2033 bool
>> 2034
>> 2035 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2036 bool
>> 2037
>> 2038 config SYS_HAS_CPU_BMIPS
>> 2039 bool
>> 2040
>> 2041 config SYS_HAS_CPU_BMIPS32_3300
>> 2042 bool
>> 2043 select SYS_HAS_CPU_BMIPS
>> 2044
>> 2045 config SYS_HAS_CPU_BMIPS4350
>> 2046 bool
>> 2047 select SYS_HAS_CPU_BMIPS
>> 2048
>> 2049 config SYS_HAS_CPU_BMIPS4380
>> 2050 bool
>> 2051 select SYS_HAS_CPU_BMIPS
>> 2052
>> 2053 config SYS_HAS_CPU_BMIPS5000
>> 2054 bool
>> 2055 select SYS_HAS_CPU_BMIPS
>> 2056 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2057
>> 2058 config SYS_HAS_CPU_XLR
>> 2059 bool
>> 2060
>> 2061 config SYS_HAS_CPU_XLP
>> 2062 bool
>> 2063
>> 2064 #
>> 2065 # CPU may reorder R->R, R->W, W->R, W->W
>> 2066 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2067 #
>> 2068 config WEAK_ORDERING
>> 2069 bool
>> 2070
>> 2071 #
>> 2072 # CPU may reorder reads and writes beyond LL/SC
>> 2073 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2074 #
>> 2075 config WEAK_REORDERING_BEYOND_LLSC
>> 2076 bool
>> 2077 endmenu
>> 2078
>> 2079 #
>> 2080 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2081 #
>> 2082 config CPU_MIPS32
>> 2083 bool
>> 2084 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2085 CPU_MIPS32_R6 || CPU_P5600
>> 2086
>> 2087 config CPU_MIPS64
>> 2088 bool
>> 2089 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2090 CPU_MIPS64_R6
>> 2091
>> 2092 #
>> 2093 # These indicate the revision of the architecture
>> 2094 #
>> 2095 config CPU_MIPSR1
>> 2096 bool
>> 2097 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2098
>> 2099 config CPU_MIPSR2
>> 2100 bool
>> 2101 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2102 select CPU_HAS_RIXI
>> 2103 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2104 select MIPS_SPRAM
>> 2105
>> 2106 config CPU_MIPSR5
>> 2107 bool
>> 2108 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2109 select CPU_HAS_RIXI
>> 2110 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2111 select MIPS_SPRAM
>> 2112
>> 2113 config CPU_MIPSR6
>> 2114 bool
>> 2115 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2116 select CPU_HAS_RIXI
>> 2117 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2118 select HAVE_ARCH_BITREVERSE
>> 2119 select MIPS_ASID_BITS_VARIABLE
>> 2120 select MIPS_CRC_SUPPORT
>> 2121 select MIPS_SPRAM
>> 2122
>> 2123 config TARGET_ISA_REV
>> 2124 int
>> 2125 default 1 if CPU_MIPSR1
>> 2126 default 2 if CPU_MIPSR2
>> 2127 default 5 if CPU_MIPSR5
>> 2128 default 6 if CPU_MIPSR6
>> 2129 default 0
>> 2130 help
>> 2131 Reflects the ISA revision being targeted by the kernel build. This
>> 2132 is effectively the Kconfig equivalent of MIPS_ISA_REV.
>> 2133
>> 2134 config EVA
>> 2135 bool
>> 2136
>> 2137 config XPA
>> 2138 bool
>> 2139
>> 2140 config SYS_SUPPORTS_32BIT_KERNEL
>> 2141 bool
>> 2142 config SYS_SUPPORTS_64BIT_KERNEL
>> 2143 bool
>> 2144 config CPU_SUPPORTS_32BIT_KERNEL
>> 2145 bool
>> 2146 config CPU_SUPPORTS_64BIT_KERNEL
>> 2147 bool
>> 2148 config CPU_SUPPORTS_CPUFREQ
>> 2149 bool
>> 2150 config CPU_SUPPORTS_ADDRWINCFG
>> 2151 bool
>> 2152 config CPU_SUPPORTS_HUGEPAGES
>> 2153 bool
>> 2154 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2155 config MIPS_PGD_C0_CONTEXT
>> 2156 bool
>> 2157 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2158
>> 2159 #
>> 2160 # Set to y for ptrace access to watch registers.
>> 2161 #
>> 2162 config HARDWARE_WATCHPOINTS
>> 2163 bool
>> 2164 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2165
>> 2166 menu "Kernel type"
>> 2167
>> 2168 choice
>> 2169 prompt "Kernel code model"
>> 2170 help
>> 2171 You should only select this option if you have a workload that
>> 2172 actually benefits from 64-bit processing or if your machine has
>> 2173 large memory. You will only be presented a single option in this
>> 2174 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2175
>> 2176 config 32BIT
>> 2177 bool "32-bit kernel"
>> 2178 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2179 select TRAD_SIGNALS
>> 2180 help
>> 2181 Select this option if you want to build a 32-bit kernel.
>> 2182
>> 2183 config 64BIT
>> 2184 bool "64-bit kernel"
>> 2185 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2186 help
>> 2187 Select this option if you want to build a 64-bit kernel.
>> 2188
>> 2189 endchoice
>> 2190
>> 2191 config KVM_GUEST
>> 2192 bool "KVM Guest Kernel"
>> 2193 depends on CPU_MIPS32_R2
>> 2194 depends on BROKEN_ON_SMP
>> 2195 help
>> 2196 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2197 mode.
>> 2198
>> 2199 config KVM_GUEST_TIMER_FREQ
>> 2200 int "Count/Compare Timer Frequency (MHz)"
>> 2201 depends on KVM_GUEST
>> 2202 default 100
>> 2203 help
>> 2204 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2205 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2206 timer frequency is specified directly.
>> 2207
>> 2208 config MIPS_VA_BITS_48
>> 2209 bool "48 bits virtual memory"
>> 2210 depends on 64BIT
>> 2211 help
>> 2212 Support a maximum at least 48 bits of application virtual
>> 2213 memory. Default is 40 bits or less, depending on the CPU.
>> 2214 For page sizes 16k and above, this option results in a small
>> 2215 memory overhead for page tables. For 4k page size, a fourth
>> 2216 level of page tables is added which imposes both a memory
>> 2217 overhead as well as slower TLB fault handling.
>> 2218
>> 2219 If unsure, say N.
>> 2220
>> 2221 choice
>> 2222 prompt "Kernel page size"
>> 2223 default PAGE_SIZE_4KB
>> 2224
>> 2225 config PAGE_SIZE_4KB
>> 2226 bool "4kB"
>> 2227 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2228 help
>> 2229 This option select the standard 4kB Linux page size. On some
>> 2230 R3000-family processors this is the only available page size. Using
>> 2231 4kB page size will minimize memory consumption and is therefore
>> 2232 recommended for low memory systems.
>> 2233
>> 2234 config PAGE_SIZE_8KB
>> 2235 bool "8kB"
>> 2236 depends on CPU_CAVIUM_OCTEON
>> 2237 depends on !MIPS_VA_BITS_48
>> 2238 help
>> 2239 Using 8kB page size will result in higher performance kernel at
>> 2240 the price of higher memory consumption. This option is available
>> 2241 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2242 distribution to support this.
>> 2243
>> 2244 config PAGE_SIZE_16KB
>> 2245 bool "16kB"
>> 2246 depends on !CPU_R3000 && !CPU_TX39XX
>> 2247 help
>> 2248 Using 16kB page size will result in higher performance kernel at
>> 2249 the price of higher memory consumption. This option is available on
>> 2250 all non-R3000 family processors. Note that you will need a suitable
>> 2251 Linux distribution to support this.
>> 2252
>> 2253 config PAGE_SIZE_32KB
>> 2254 bool "32kB"
>> 2255 depends on CPU_CAVIUM_OCTEON
>> 2256 depends on !MIPS_VA_BITS_48
>> 2257 help
>> 2258 Using 32kB page size will result in higher performance kernel at
>> 2259 the price of higher memory consumption. This option is available
>> 2260 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2261 distribution to support this.
>> 2262
>> 2263 config PAGE_SIZE_64KB
>> 2264 bool "64kB"
>> 2265 depends on !CPU_R3000 && !CPU_TX39XX
>> 2266 help
>> 2267 Using 64kB page size will result in higher performance kernel at
>> 2268 the price of higher memory consumption. This option is available on
>> 2269 all non-R3000 family processor. Not that at the time of this
>> 2270 writing this option is still high experimental.
>> 2271
>> 2272 endchoice
>> 2273
>> 2274 config FORCE_MAX_ZONEORDER
>> 2275 int "Maximum zone order"
>> 2276 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2277 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2278 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2279 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2280 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2281 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2282 range 0 64
>> 2283 default "11"
113 help 2284 help
114 Select this if your implementation h !! 2285 The kernel memory allocator divides physically contiguous memory
>> 2286 blocks into "zones", where each zone is a power of two number of
>> 2287 pages. This option selects the largest power of two that the kernel
>> 2288 keeps in the memory allocator. If you need to allocate very large
>> 2289 blocks of physically contiguous memory, then you may need to
>> 2290 increase this value.
>> 2291
>> 2292 This config option is actually maximum order plus one. For example,
>> 2293 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2294
>> 2295 The page size is not necessarily 4KB. Keep this in mind
>> 2296 when choosing a value for this option.
>> 2297
>> 2298 config BOARD_SCACHE
>> 2299 bool
>> 2300
>> 2301 config IP22_CPU_SCACHE
>> 2302 bool
>> 2303 select BOARD_SCACHE
115 2304
116 config OPENRISC_HAVE_INST_DIV !! 2305 #
117 bool "Have instruction l.div for hardw !! 2306 # Support for a MIPS32 / MIPS64 style S-caches
>> 2307 #
>> 2308 config MIPS_CPU_SCACHE
>> 2309 bool
>> 2310 select BOARD_SCACHE
>> 2311
>> 2312 config R5000_CPU_SCACHE
>> 2313 bool
>> 2314 select BOARD_SCACHE
>> 2315
>> 2316 config RM7000_CPU_SCACHE
>> 2317 bool
>> 2318 select BOARD_SCACHE
>> 2319
>> 2320 config SIBYTE_DMA_PAGEOPS
>> 2321 bool "Use DMA to clear/copy pages"
>> 2322 depends on CPU_SB1
>> 2323 help
>> 2324 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2325 channel. These DMA channels are otherwise unused by the standard
>> 2326 SiByte Linux port. Seems to give a small performance benefit.
>> 2327
>> 2328 config CPU_HAS_PREFETCH
>> 2329 bool
>> 2330
>> 2331 config CPU_GENERIC_DUMP_TLB
>> 2332 bool
>> 2333 default y if !(CPU_R3000 || CPU_TX39XX)
>> 2334
>> 2335 config MIPS_FP_SUPPORT
>> 2336 bool "Floating Point support" if EXPERT
118 default y 2337 default y
119 help 2338 help
120 Select this if your implementation h !! 2339 Select y to include support for floating point in the kernel
>> 2340 including initialization of FPU hardware, FP context save & restore
>> 2341 and emulation of an FPU where necessary. Without this support any
>> 2342 userland program attempting to use floating point instructions will
>> 2343 receive a SIGILL.
>> 2344
>> 2345 If you know that your userland will not attempt to use floating point
>> 2346 instructions then you can say n here to shrink the kernel a little.
>> 2347
>> 2348 If unsure, say y.
>> 2349
>> 2350 config CPU_R2300_FPU
>> 2351 bool
>> 2352 depends on MIPS_FP_SUPPORT
>> 2353 default y if CPU_R3000 || CPU_TX39XX
>> 2354
>> 2355 config CPU_R3K_TLB
>> 2356 bool
>> 2357
>> 2358 config CPU_R4K_FPU
>> 2359 bool
>> 2360 depends on MIPS_FP_SUPPORT
>> 2361 default y if !CPU_R2300_FPU
>> 2362
>> 2363 config CPU_R4K_CACHE_TLB
>> 2364 bool
>> 2365 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
121 2366
122 config OPENRISC_HAVE_INST_CMOV !! 2367 config MIPS_MT_SMP
123 bool "Have instruction l.cmov for cond !! 2368 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2369 default y
>> 2370 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2371 select CPU_MIPSR2_IRQ_VI
>> 2372 select CPU_MIPSR2_IRQ_EI
>> 2373 select SYNC_R4K
>> 2374 select MIPS_MT
>> 2375 select SMP
>> 2376 select SMP_UP
>> 2377 select SYS_SUPPORTS_SMP
>> 2378 select SYS_SUPPORTS_SCHED_SMT
>> 2379 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2380 help
>> 2381 This is a kernel model which is known as SMVP. This is supported
>> 2382 on cores with the MT ASE and uses the available VPEs to implement
>> 2383 virtual processors which supports SMP. This is equivalent to the
>> 2384 Intel Hyperthreading feature. For further information go to
>> 2385 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2386
>> 2387 config MIPS_MT
>> 2388 bool
>> 2389
>> 2390 config SCHED_SMT
>> 2391 bool "SMT (multithreading) scheduler support"
>> 2392 depends on SYS_SUPPORTS_SCHED_SMT
124 default n 2393 default n
125 help 2394 help
126 This config enables gcc to generate !! 2395 SMT scheduler support improves the CPU scheduler's decision making
127 the kernel which in general will imp !! 2396 when dealing with MIPS MT enabled cores at a cost of slightly
128 binary size. !! 2397 increased overhead in some places. If unsure say N here.
129 2398
130 Select this if your implementation h !! 2399 config SYS_SUPPORTS_SCHED_SMT
131 l.cmov conistional move instruction. !! 2400 bool
132 2401
133 Say N if you are unsure. !! 2402 config SYS_SUPPORTS_MULTITHREADING
>> 2403 bool
>> 2404
>> 2405 config MIPS_MT_FPAFF
>> 2406 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2407 default y
>> 2408 depends on MIPS_MT_SMP
134 2409
135 config OPENRISC_HAVE_INST_ROR !! 2410 config MIPSR2_TO_R6_EMULATOR
136 bool "Have instruction l.ror for rotat !! 2411 bool "MIPS R2-to-R6 emulator"
>> 2412 depends on CPU_MIPSR6
>> 2413 depends on MIPS_FP_SUPPORT
>> 2414 default y
>> 2415 help
>> 2416 Choose this option if you want to run non-R6 MIPS userland code.
>> 2417 Even if you say 'Y' here, the emulator will still be disabled by
>> 2418 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2419 The only reason this is a build-time option is to save ~14K from the
>> 2420 final kernel image.
>> 2421
>> 2422 config SYS_SUPPORTS_VPE_LOADER
>> 2423 bool
>> 2424 depends on SYS_SUPPORTS_MULTITHREADING
>> 2425 help
>> 2426 Indicates that the platform supports the VPE loader, and provides
>> 2427 physical_memsize.
>> 2428
>> 2429 config MIPS_VPE_LOADER
>> 2430 bool "VPE loader support."
>> 2431 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2432 select CPU_MIPSR2_IRQ_VI
>> 2433 select CPU_MIPSR2_IRQ_EI
>> 2434 select MIPS_MT
>> 2435 help
>> 2436 Includes a loader for loading an elf relocatable object
>> 2437 onto another VPE and running it.
>> 2438
>> 2439 config MIPS_VPE_LOADER_CMP
>> 2440 bool
>> 2441 default "y"
>> 2442 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2443
>> 2444 config MIPS_VPE_LOADER_MT
>> 2445 bool
>> 2446 default "y"
>> 2447 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2448
>> 2449 config MIPS_VPE_LOADER_TOM
>> 2450 bool "Load VPE program into memory hidden from linux"
>> 2451 depends on MIPS_VPE_LOADER
>> 2452 default y
>> 2453 help
>> 2454 The loader can use memory that is present but has been hidden from
>> 2455 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2456 you to ensure the amount you put in the option and the space your
>> 2457 program requires is less or equal to the amount physically present.
>> 2458
>> 2459 config MIPS_VPE_APSP_API
>> 2460 bool "Enable support for AP/SP API (RTLX)"
>> 2461 depends on MIPS_VPE_LOADER
>> 2462
>> 2463 config MIPS_VPE_APSP_API_CMP
>> 2464 bool
>> 2465 default "y"
>> 2466 depends on MIPS_VPE_APSP_API && MIPS_CMP
>> 2467
>> 2468 config MIPS_VPE_APSP_API_MT
>> 2469 bool
>> 2470 default "y"
>> 2471 depends on MIPS_VPE_APSP_API && !MIPS_CMP
>> 2472
>> 2473 config MIPS_CMP
>> 2474 bool "MIPS CMP framework support (DEPRECATED)"
>> 2475 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2476 select SMP
>> 2477 select SYNC_R4K
>> 2478 select SYS_SUPPORTS_SMP
>> 2479 select WEAK_ORDERING
137 default n 2480 default n
138 help 2481 help
139 This config enables gcc to generate !! 2482 Select this if you are using a bootloader which implements the "CMP
140 the kernel which in general will imp !! 2483 framework" protocol (ie. YAMON) and want your kernel to make use of
141 binary size. !! 2484 its ability to start secondary CPUs.
>> 2485
>> 2486 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2487 instead of this.
>> 2488
>> 2489 config MIPS_CPS
>> 2490 bool "MIPS Coherent Processing System support"
>> 2491 depends on SYS_SUPPORTS_MIPS_CPS
>> 2492 select MIPS_CM
>> 2493 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2494 select SMP
>> 2495 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2496 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2497 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2498 select SYS_SUPPORTS_SMP
>> 2499 select WEAK_ORDERING
>> 2500 help
>> 2501 Select this if you wish to run an SMP kernel across multiple cores
>> 2502 within a MIPS Coherent Processing System. When this option is
>> 2503 enabled the kernel will probe for other cores and boot them with
>> 2504 no external assistance. It is safe to enable this when hardware
>> 2505 support is unavailable.
>> 2506
>> 2507 config MIPS_CPS_PM
>> 2508 depends on MIPS_CPS
>> 2509 bool
>> 2510
>> 2511 config MIPS_CM
>> 2512 bool
>> 2513 select MIPS_CPC
>> 2514
>> 2515 config MIPS_CPC
>> 2516 bool
>> 2517
>> 2518 config SB1_PASS_2_WORKAROUNDS
>> 2519 bool
>> 2520 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2521 default y
142 2522
143 Select this if your implementation h !! 2523 config SB1_PASS_2_1_WORKAROUNDS
144 l.ror rotate right instruction. !! 2524 bool
>> 2525 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2526 default y
145 2527
146 Say N if you are unsure. !! 2528 choice
>> 2529 prompt "SmartMIPS or microMIPS ASE support"
147 2530
148 config OPENRISC_HAVE_INST_RORI !! 2531 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
149 bool "Have instruction l.rori for rota !! 2532 bool "None"
150 default n <<
151 help 2533 help
152 This config enables gcc to generate !! 2534 Select this if you want neither microMIPS nor SmartMIPS support
153 the kernel which in general will imp <<
154 binary size. <<
155 2535
156 Select this if your implementation h !! 2536 config CPU_HAS_SMARTMIPS
157 l.rori rotate right with immediate i !! 2537 depends on SYS_SUPPORTS_SMARTMIPS
>> 2538 bool "SmartMIPS"
>> 2539 help
>> 2540 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2541 increased security at both hardware and software level for
>> 2542 smartcards. Enabling this option will allow proper use of the
>> 2543 SmartMIPS instructions by Linux applications. However a kernel with
>> 2544 this option will not work on a MIPS core without SmartMIPS core. If
>> 2545 you don't know you probably don't have SmartMIPS and should say N
>> 2546 here.
158 2547
159 Say N if you are unsure. !! 2548 config CPU_MICROMIPS
>> 2549 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2550 bool "microMIPS"
>> 2551 help
>> 2552 When this option is enabled the kernel will be built using the
>> 2553 microMIPS ISA
160 2554
161 config OPENRISC_HAVE_INST_SEXT !! 2555 endchoice
162 bool "Have instructions l.ext* for sig !! 2556
163 default n !! 2557 config CPU_HAS_MSA
>> 2558 bool "Support for the MIPS SIMD Architecture"
>> 2559 depends on CPU_SUPPORTS_MSA
>> 2560 depends on MIPS_FP_SUPPORT
>> 2561 depends on 64BIT || MIPS_O32_FP64_SUPPORT
164 help 2562 help
165 This config enables gcc to generate !! 2563 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
166 the kernel which in general will imp !! 2564 and a set of SIMD instructions to operate on them. When this option
167 binary size. !! 2565 is enabled the kernel will support allocating & switching MSA
>> 2566 vector register contexts. If you know that your kernel will only be
>> 2567 running on CPUs which do not support MSA or that your userland will
>> 2568 not be making use of it then you may wish to say N here to reduce
>> 2569 the size & complexity of your kernel.
>> 2570
>> 2571 If unsure, say Y.
>> 2572
>> 2573 config CPU_HAS_WB
>> 2574 bool
>> 2575
>> 2576 config XKS01
>> 2577 bool
>> 2578
>> 2579 config CPU_HAS_DIEI
>> 2580 depends on !CPU_DIEI_BROKEN
>> 2581 bool
168 2582
169 Select this if your implementation h !! 2583 config CPU_DIEI_BROKEN
170 l.exths, l.extbs, l.exthz and l.extb !! 2584 bool
171 2585
172 Say N if you are unsure. !! 2586 config CPU_HAS_RIXI
>> 2587 bool
173 2588
174 endmenu !! 2589 config CPU_NO_LOAD_STORE_LR
>> 2590 bool
>> 2591 help
>> 2592 CPU lacks support for unaligned load and store instructions:
>> 2593 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2594 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2595 systems).
175 2596
176 config NR_CPUS !! 2597 #
177 int "Maximum number of CPUs (2-32)" !! 2598 # Vectored interrupt mode is an R2 feature
178 range 2 32 !! 2599 #
179 depends on SMP !! 2600 config CPU_MIPSR2_IRQ_VI
180 default "2" !! 2601 bool
>> 2602
>> 2603 #
>> 2604 # Extended interrupt mode is an R2 feature
>> 2605 #
>> 2606 config CPU_MIPSR2_IRQ_EI
>> 2607 bool
>> 2608
>> 2609 config CPU_HAS_SYNC
>> 2610 bool
>> 2611 depends on !CPU_R3000
>> 2612 default y
>> 2613
>> 2614 #
>> 2615 # CPU non-features
>> 2616 #
>> 2617 config CPU_DADDI_WORKAROUNDS
>> 2618 bool
>> 2619
>> 2620 config CPU_R4000_WORKAROUNDS
>> 2621 bool
>> 2622 select CPU_R4400_WORKAROUNDS
>> 2623
>> 2624 config CPU_R4400_WORKAROUNDS
>> 2625 bool
>> 2626
>> 2627 config CPU_R4X00_BUGS64
>> 2628 bool
>> 2629 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
>> 2630
>> 2631 config MIPS_ASID_SHIFT
>> 2632 int
>> 2633 default 6 if CPU_R3000 || CPU_TX39XX
>> 2634 default 0
>> 2635
>> 2636 config MIPS_ASID_BITS
>> 2637 int
>> 2638 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2639 default 6 if CPU_R3000 || CPU_TX39XX
>> 2640 default 8
>> 2641
>> 2642 config MIPS_ASID_BITS_VARIABLE
>> 2643 bool
>> 2644
>> 2645 config MIPS_CRC_SUPPORT
>> 2646 bool
>> 2647
>> 2648 # R4600 erratum. Due to the lack of errata information the exact
>> 2649 # technical details aren't known. I've experimentally found that disabling
>> 2650 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2651 # with the issue.
>> 2652 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2653 bool
>> 2654
>> 2655 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
>> 2656 #
>> 2657 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2658 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2659 # executed if there is no other dcache activity. If the dcache is
>> 2660 # accessed for another instruction immeidately preceding when these
>> 2661 # cache instructions are executing, it is possible that the dcache
>> 2662 # tag match outputs used by these cache instructions will be
>> 2663 # incorrect. These cache instructions should be preceded by at least
>> 2664 # four instructions that are not any kind of load or store
>> 2665 # instruction.
>> 2666 #
>> 2667 # This is not allowed: lw
>> 2668 # nop
>> 2669 # nop
>> 2670 # nop
>> 2671 # cache Hit_Writeback_Invalidate_D
>> 2672 #
>> 2673 # This is allowed: lw
>> 2674 # nop
>> 2675 # nop
>> 2676 # nop
>> 2677 # nop
>> 2678 # cache Hit_Writeback_Invalidate_D
>> 2679 config WAR_R4600_V1_HIT_CACHEOP
>> 2680 bool
>> 2681
>> 2682 # Writeback and invalidate the primary cache dcache before DMA.
>> 2683 #
>> 2684 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2685 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2686 # operate correctly if the internal data cache refill buffer is empty. These
>> 2687 # CACHE instructions should be separated from any potential data cache miss
>> 2688 # by a load instruction to an uncached address to empty the response buffer."
>> 2689 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2690 # in .pdf format.)
>> 2691 config WAR_R4600_V2_HIT_CACHEOP
>> 2692 bool
>> 2693
>> 2694 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
>> 2695 # the line which this instruction itself exists, the following
>> 2696 # operation is not guaranteed."
>> 2697 #
>> 2698 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2699 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2700 bool
>> 2701
>> 2702 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2703 # opposes it being called that) where invalid instructions in the same
>> 2704 # I-cache line worth of instructions being fetched may case spurious
>> 2705 # exceptions.
>> 2706 config WAR_ICACHE_REFILLS
>> 2707 bool
>> 2708
>> 2709 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
>> 2710 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2711 config WAR_R10000_LLSC
>> 2712 bool
>> 2713
>> 2714 # 34K core erratum: "Problems Executing the TLBR Instruction"
>> 2715 config WAR_MIPS34K_MISSED_ITLB
>> 2716 bool
>> 2717
>> 2718 #
>> 2719 # - Highmem only makes sense for the 32-bit kernel.
>> 2720 # - The current highmem code will only work properly on physically indexed
>> 2721 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2722 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2723 # moment we protect the user and offer the highmem option only on machines
>> 2724 # where it's known to be safe. This will not offer highmem on a few systems
>> 2725 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2726 # indexed CPUs but we're playing safe.
>> 2727 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2728 # know they might have memory configurations that could make use of highmem
>> 2729 # support.
>> 2730 #
>> 2731 config HIGHMEM
>> 2732 bool "High Memory Support"
>> 2733 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2734
>> 2735 config CPU_SUPPORTS_HIGHMEM
>> 2736 bool
>> 2737
>> 2738 config SYS_SUPPORTS_HIGHMEM
>> 2739 bool
>> 2740
>> 2741 config SYS_SUPPORTS_SMARTMIPS
>> 2742 bool
>> 2743
>> 2744 config SYS_SUPPORTS_MICROMIPS
>> 2745 bool
>> 2746
>> 2747 config SYS_SUPPORTS_MIPS16
>> 2748 bool
>> 2749 help
>> 2750 This option must be set if a kernel might be executed on a MIPS16-
>> 2751 enabled CPU even if MIPS16 is not actually being used. In other
>> 2752 words, it makes the kernel MIPS16-tolerant.
>> 2753
>> 2754 config CPU_SUPPORTS_MSA
>> 2755 bool
>> 2756
>> 2757 config ARCH_FLATMEM_ENABLE
>> 2758 def_bool y
>> 2759 depends on !NUMA && !CPU_LOONGSON2EF
>> 2760
>> 2761 config ARCH_SPARSEMEM_ENABLE
>> 2762 bool
>> 2763 select SPARSEMEM_STATIC if !SGI_IP27
>> 2764
>> 2765 config NUMA
>> 2766 bool "NUMA Support"
>> 2767 depends on SYS_SUPPORTS_NUMA
>> 2768 help
>> 2769 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2770 Access). This option improves performance on systems with more
>> 2771 than two nodes; on two node systems it is generally better to
>> 2772 leave it disabled; on single node systems leave this option
>> 2773 disabled.
>> 2774
>> 2775 config SYS_SUPPORTS_NUMA
>> 2776 bool
>> 2777
>> 2778 config HAVE_SETUP_PER_CPU_AREA
>> 2779 def_bool y
>> 2780 depends on NUMA
>> 2781
>> 2782 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2783 def_bool y
>> 2784 depends on NUMA
>> 2785
>> 2786 config RELOCATABLE
>> 2787 bool "Relocatable kernel"
>> 2788 depends on SYS_SUPPORTS_RELOCATABLE
>> 2789 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2790 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2791 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2792 CPU_P5600 || CAVIUM_OCTEON_SOC
>> 2793 help
>> 2794 This builds a kernel image that retains relocation information
>> 2795 so it can be loaded someplace besides the default 1MB.
>> 2796 The relocations make the kernel binary about 15% larger,
>> 2797 but are discarded at runtime
>> 2798
>> 2799 config RELOCATION_TABLE_SIZE
>> 2800 hex "Relocation table size"
>> 2801 depends on RELOCATABLE
>> 2802 range 0x0 0x01000000
>> 2803 default "0x00100000"
>> 2804 help
>> 2805 A table of relocation data will be appended to the kernel binary
>> 2806 and parsed at boot to fix up the relocated kernel.
>> 2807
>> 2808 This option allows the amount of space reserved for the table to be
>> 2809 adjusted, although the default of 1Mb should be ok in most cases.
>> 2810
>> 2811 The build will fail and a valid size suggested if this is too small.
>> 2812
>> 2813 If unsure, leave at the default value.
>> 2814
>> 2815 config RANDOMIZE_BASE
>> 2816 bool "Randomize the address of the kernel image"
>> 2817 depends on RELOCATABLE
>> 2818 help
>> 2819 Randomizes the physical and virtual address at which the
>> 2820 kernel image is loaded, as a security feature that
>> 2821 deters exploit attempts relying on knowledge of the location
>> 2822 of kernel internals.
>> 2823
>> 2824 Entropy is generated using any coprocessor 0 registers available.
>> 2825
>> 2826 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2827
>> 2828 If unsure, say N.
>> 2829
>> 2830 config RANDOMIZE_BASE_MAX_OFFSET
>> 2831 hex "Maximum kASLR offset" if EXPERT
>> 2832 depends on RANDOMIZE_BASE
>> 2833 range 0x0 0x40000000 if EVA || 64BIT
>> 2834 range 0x0 0x08000000
>> 2835 default "0x01000000"
>> 2836 help
>> 2837 When kASLR is active, this provides the maximum offset that will
>> 2838 be applied to the kernel image. It should be set according to the
>> 2839 amount of physical RAM available in the target system minus
>> 2840 PHYSICAL_START and must be a power of 2.
>> 2841
>> 2842 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2843 EVA or 64-bit. The default is 16Mb.
>> 2844
>> 2845 config NODES_SHIFT
>> 2846 int
>> 2847 default "6"
>> 2848 depends on NEED_MULTIPLE_NODES
>> 2849
>> 2850 config HW_PERF_EVENTS
>> 2851 bool "Enable hardware performance counter support for perf events"
>> 2852 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2853 default y
>> 2854 help
>> 2855 Enable hardware performance counter support for perf events. If
>> 2856 disabled, perf events will use software events only.
>> 2857
>> 2858 config DMI
>> 2859 bool "Enable DMI scanning"
>> 2860 depends on MACH_LOONGSON64
>> 2861 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2862 default y
>> 2863 help
>> 2864 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2865 here unless you have verified that your setup is not
>> 2866 affected by entries in the DMI blacklist. Required by PNP
>> 2867 BIOS code.
181 2868
182 config SMP 2869 config SMP
183 bool "Symmetric Multi-Processing suppo !! 2870 bool "Multi-Processing support"
>> 2871 depends on SYS_SUPPORTS_SMP
184 help 2872 help
185 This enables support for systems wit 2873 This enables support for systems with more than one CPU. If you have
186 a system with only one CPU, say N. I 2874 a system with only one CPU, say N. If you have a system with more
187 than one CPU, say Y. 2875 than one CPU, say Y.
188 2876
>> 2877 If you say N here, the kernel will run on uni- and multiprocessor
>> 2878 machines, but will use only one CPU of a multiprocessor machine. If
>> 2879 you say Y here, the kernel will run on many, but not all,
>> 2880 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2881 will run faster if you say N here.
>> 2882
>> 2883 People using multiprocessor machines who say Y here should also say
>> 2884 Y to "Enhanced Real Time Clock Support", below.
>> 2885
>> 2886 See also the SMP-HOWTO available at
>> 2887 <https://www.tldp.org/docs.html#howto>.
>> 2888
189 If you don't know what to do here, s 2889 If you don't know what to do here, say N.
190 2890
191 config FPU !! 2891 config HOTPLUG_CPU
192 bool "FPU support" !! 2892 bool "Support for hot-pluggable CPUs"
193 default y !! 2893 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
194 help 2894 help
195 Say N here if you want to disable al !! 2895 Say Y here to allow turning CPUs off and on. CPUs can be
196 in the kernel and reduce binary size !! 2896 controlled through /sys/devices/system/cpu.
>> 2897 (Note: power management support will enable this option
>> 2898 automatically on SMP systems. )
>> 2899 Say N if you want to disable CPU hotplug.
197 2900
198 If you don't know what to do here, s !! 2901 config SMP_UP
>> 2902 bool
199 2903
200 source "kernel/Kconfig.hz" !! 2904 config SYS_SUPPORTS_MIPS_CMP
>> 2905 bool
201 2906
202 config OPENRISC_NO_SPR_SR_DSX !! 2907 config SYS_SUPPORTS_MIPS_CPS
203 bool "use SPR_SR_DSX software emulatio !! 2908 bool
204 default y !! 2909
>> 2910 config SYS_SUPPORTS_SMP
>> 2911 bool
>> 2912
>> 2913 config NR_CPUS_DEFAULT_4
>> 2914 bool
>> 2915
>> 2916 config NR_CPUS_DEFAULT_8
>> 2917 bool
>> 2918
>> 2919 config NR_CPUS_DEFAULT_16
>> 2920 bool
>> 2921
>> 2922 config NR_CPUS_DEFAULT_32
>> 2923 bool
>> 2924
>> 2925 config NR_CPUS_DEFAULT_64
>> 2926 bool
>> 2927
>> 2928 config NR_CPUS
>> 2929 int "Maximum number of CPUs (2-256)"
>> 2930 range 2 256
>> 2931 depends on SMP
>> 2932 default "4" if NR_CPUS_DEFAULT_4
>> 2933 default "8" if NR_CPUS_DEFAULT_8
>> 2934 default "16" if NR_CPUS_DEFAULT_16
>> 2935 default "32" if NR_CPUS_DEFAULT_32
>> 2936 default "64" if NR_CPUS_DEFAULT_64
205 help 2937 help
206 SPR_SR_DSX bit is status register bi !! 2938 This allows you to specify the maximum number of CPUs which this
207 the last exception has happened in d !! 2939 kernel will support. The maximum supported value is 32 for 32-bit
>> 2940 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2941 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2942 and 2 for all others.
>> 2943
>> 2944 This is purely to save memory - each supported CPU adds
>> 2945 approximately eight kilobytes to the kernel image. For best
>> 2946 performance should round up your number of processors to the next
>> 2947 power of two.
208 2948
209 OpenRISC architecture makes it optio !! 2949 config MIPS_PERF_SHARED_TC_COUNTERS
210 in hardware and the OR1200 does not !! 2950 bool
211 2951
212 Say N here if you know that your Ope !! 2952 config MIPS_NR_CPU_NR_MAP_1024
213 SPR_SR_DSX bit implemented. Say Y if !! 2953 bool
214 2954
215 config OPENRISC_HAVE_SHADOW_GPRS !! 2955 config MIPS_NR_CPU_NR_MAP
216 bool "Support for shadow gpr files" if !! 2956 int
217 default y if SMP !! 2957 depends on SMP
>> 2958 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2959 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2960
>> 2961 #
>> 2962 # Timer Interrupt Frequency Configuration
>> 2963 #
>> 2964
>> 2965 choice
>> 2966 prompt "Timer frequency"
>> 2967 default HZ_250
218 help 2968 help
219 Say Y here if your OpenRISC processo !! 2969 Allows the configuration of the timer frequency.
220 register files. They will in such ca <<
221 scratch reg storage on exception ent <<
222 <<
223 On SMP systems, this feature is mand <<
224 On a unicore system it's safe to say <<
225 <<
226 config CMDLINE <<
227 string "Default kernel command string" <<
228 default "" <<
229 help <<
230 On some architectures there is curre <<
231 to pass arguments to the kernel. For <<
232 supply some command-line options at <<
233 here. <<
234 2970
235 menu "Debugging options" !! 2971 config HZ_24
>> 2972 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
236 2973
237 config JUMP_UPON_UNHANDLED_EXCEPTION !! 2974 config HZ_48
238 bool "Try to die gracefully" !! 2975 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2976
>> 2977 config HZ_100
>> 2978 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2979
>> 2980 config HZ_128
>> 2981 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2982
>> 2983 config HZ_250
>> 2984 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2985
>> 2986 config HZ_256
>> 2987 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2988
>> 2989 config HZ_1000
>> 2990 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2991
>> 2992 config HZ_1024
>> 2993 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2994
>> 2995 endchoice
>> 2996
>> 2997 config SYS_SUPPORTS_24HZ
>> 2998 bool
>> 2999
>> 3000 config SYS_SUPPORTS_48HZ
>> 3001 bool
>> 3002
>> 3003 config SYS_SUPPORTS_100HZ
>> 3004 bool
>> 3005
>> 3006 config SYS_SUPPORTS_128HZ
>> 3007 bool
>> 3008
>> 3009 config SYS_SUPPORTS_250HZ
>> 3010 bool
>> 3011
>> 3012 config SYS_SUPPORTS_256HZ
>> 3013 bool
>> 3014
>> 3015 config SYS_SUPPORTS_1000HZ
>> 3016 bool
>> 3017
>> 3018 config SYS_SUPPORTS_1024HZ
>> 3019 bool
>> 3020
>> 3021 config SYS_SUPPORTS_ARBIT_HZ
>> 3022 bool
>> 3023 default y if !SYS_SUPPORTS_24HZ && \
>> 3024 !SYS_SUPPORTS_48HZ && \
>> 3025 !SYS_SUPPORTS_100HZ && \
>> 3026 !SYS_SUPPORTS_128HZ && \
>> 3027 !SYS_SUPPORTS_250HZ && \
>> 3028 !SYS_SUPPORTS_256HZ && \
>> 3029 !SYS_SUPPORTS_1000HZ && \
>> 3030 !SYS_SUPPORTS_1024HZ
>> 3031
>> 3032 config HZ
>> 3033 int
>> 3034 default 24 if HZ_24
>> 3035 default 48 if HZ_48
>> 3036 default 100 if HZ_100
>> 3037 default 128 if HZ_128
>> 3038 default 250 if HZ_250
>> 3039 default 256 if HZ_256
>> 3040 default 1000 if HZ_1000
>> 3041 default 1024 if HZ_1024
>> 3042
>> 3043 config SCHED_HRTICK
>> 3044 def_bool HIGH_RES_TIMERS
>> 3045
>> 3046 config KEXEC
>> 3047 bool "Kexec system call"
>> 3048 select KEXEC_CORE
>> 3049 help
>> 3050 kexec is a system call that implements the ability to shutdown your
>> 3051 current kernel, and to start another kernel. It is like a reboot
>> 3052 but it is independent of the system firmware. And like a reboot
>> 3053 you can start any kernel with it, not just Linux.
>> 3054
>> 3055 The name comes from the similarity to the exec system call.
>> 3056
>> 3057 It is an ongoing process to be certain the hardware in a machine
>> 3058 is properly shutdown, so do not be surprised if this code does not
>> 3059 initially work for you. As of this writing the exact hardware
>> 3060 interface is strongly in flux, so no good recommendation can be
>> 3061 made.
>> 3062
>> 3063 config CRASH_DUMP
>> 3064 bool "Kernel crash dumps"
>> 3065 help
>> 3066 Generate crash dump after being started by kexec.
>> 3067 This should be normally only set in special crash dump kernels
>> 3068 which are loaded in the main kernel with kexec-tools into
>> 3069 a specially reserved region and then later executed after
>> 3070 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3071 to a memory address not used by the main kernel or firmware using
>> 3072 PHYSICAL_START.
>> 3073
>> 3074 config PHYSICAL_START
>> 3075 hex "Physical address where the kernel is loaded"
>> 3076 default "0xffffffff84000000"
>> 3077 depends on CRASH_DUMP
>> 3078 help
>> 3079 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3080 If you plan to use kernel for capturing the crash dump change
>> 3081 this value to start of the reserved region (the "X" value as
>> 3082 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3083 passed to the panic-ed kernel).
>> 3084
>> 3085 config MIPS_O32_FP64_SUPPORT
>> 3086 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3087 depends on 32BIT || MIPS32_O32
>> 3088 help
>> 3089 When this is enabled, the kernel will support use of 64-bit floating
>> 3090 point registers with binaries using the O32 ABI along with the
>> 3091 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3092 32-bit MIPS systems this support is at the cost of increasing the
>> 3093 size and complexity of the compiled FPU emulator. Thus if you are
>> 3094 running a MIPS32 system and know that none of your userland binaries
>> 3095 will require 64-bit floating point, you may wish to reduce the size
>> 3096 of your kernel & potentially improve FP emulation performance by
>> 3097 saying N here.
>> 3098
>> 3099 Although binutils currently supports use of this flag the details
>> 3100 concerning its effect upon the O32 ABI in userland are still being
>> 3101 worked on. In order to avoid userland becoming dependant upon current
>> 3102 behaviour before the details have been finalised, this option should
>> 3103 be considered experimental and only enabled by those working upon
>> 3104 said details.
>> 3105
>> 3106 If unsure, say N.
>> 3107
>> 3108 config USE_OF
>> 3109 bool
>> 3110 select OF
>> 3111 select OF_EARLY_FLATTREE
>> 3112 select IRQ_DOMAIN
>> 3113
>> 3114 config UHI_BOOT
>> 3115 bool
>> 3116
>> 3117 config BUILTIN_DTB
>> 3118 bool
>> 3119
>> 3120 choice
>> 3121 prompt "Kernel appended dtb support" if USE_OF
>> 3122 default MIPS_NO_APPENDED_DTB
>> 3123
>> 3124 config MIPS_NO_APPENDED_DTB
>> 3125 bool "None"
>> 3126 help
>> 3127 Do not enable appended dtb support.
>> 3128
>> 3129 config MIPS_ELF_APPENDED_DTB
>> 3130 bool "vmlinux"
>> 3131 help
>> 3132 With this option, the boot code will look for a device tree binary
>> 3133 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3134 it is empty and the DTB can be appended using binutils command
>> 3135 objcopy:
>> 3136
>> 3137 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3138
>> 3139 This is meant as a backward compatiblity convenience for those
>> 3140 systems with a bootloader that can't be upgraded to accommodate
>> 3141 the documented boot protocol using a device tree.
>> 3142
>> 3143 config MIPS_RAW_APPENDED_DTB
>> 3144 bool "vmlinux.bin or vmlinuz.bin"
>> 3145 help
>> 3146 With this option, the boot code will look for a device tree binary
>> 3147 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3148 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3149
>> 3150 This is meant as a backward compatibility convenience for those
>> 3151 systems with a bootloader that can't be upgraded to accommodate
>> 3152 the documented boot protocol using a device tree.
>> 3153
>> 3154 Beware that there is very little in terms of protection against
>> 3155 this option being confused by leftover garbage in memory that might
>> 3156 look like a DTB header after a reboot if no actual DTB is appended
>> 3157 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3158 if you don't intend to always append a DTB.
>> 3159 endchoice
>> 3160
>> 3161 choice
>> 3162 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3163 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3164 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3165 !CAVIUM_OCTEON_SOC
>> 3166 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3167
>> 3168 config MIPS_CMDLINE_FROM_DTB
>> 3169 depends on USE_OF
>> 3170 bool "Dtb kernel arguments if available"
>> 3171
>> 3172 config MIPS_CMDLINE_DTB_EXTEND
>> 3173 depends on USE_OF
>> 3174 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3175
>> 3176 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3177 bool "Bootloader kernel arguments if available"
>> 3178
>> 3179 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3180 depends on CMDLINE_BOOL
>> 3181 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3182 endchoice
>> 3183
>> 3184 endmenu
>> 3185
>> 3186 config LOCKDEP_SUPPORT
>> 3187 bool
>> 3188 default y
>> 3189
>> 3190 config STACKTRACE_SUPPORT
>> 3191 bool
239 default y 3192 default y
>> 3193
>> 3194 config PGTABLE_LEVELS
>> 3195 int
>> 3196 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3197 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3198 default 2
>> 3199
>> 3200 config MIPS_AUTO_PFN_OFFSET
>> 3201 bool
>> 3202
>> 3203 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3204
>> 3205 config PCI_DRIVERS_GENERIC
>> 3206 select PCI_DOMAINS_GENERIC if PCI
>> 3207 bool
>> 3208
>> 3209 config PCI_DRIVERS_LEGACY
>> 3210 def_bool !PCI_DRIVERS_GENERIC
>> 3211 select NO_GENERIC_PCI_IOPORT_MAP
>> 3212 select PCI_DOMAINS if PCI
>> 3213
>> 3214 #
>> 3215 # ISA support is now enabled via select. Too many systems still have the one
>> 3216 # or other ISA chip on the board that users don't know about so don't expect
>> 3217 # users to choose the right thing ...
>> 3218 #
>> 3219 config ISA
>> 3220 bool
>> 3221
>> 3222 config TC
>> 3223 bool "TURBOchannel support"
>> 3224 depends on MACH_DECSTATION
240 help 3225 help
241 Now this puts kernel into infinite l !! 3226 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
242 your kernel crashes this doesn't hav !! 3227 processors. TURBOchannel programming specifications are available
>> 3228 at:
>> 3229 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3230 and:
>> 3231 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3232 Linux driver support status is documented at:
>> 3233 <http://www.linux-mips.org/wiki/DECstation>
>> 3234
>> 3235 config MMU
>> 3236 bool
>> 3237 default y
243 3238
244 Say Y if you are unsure. !! 3239 config ARCH_MMAP_RND_BITS_MIN
>> 3240 default 12 if 64BIT
>> 3241 default 8
>> 3242
>> 3243 config ARCH_MMAP_RND_BITS_MAX
>> 3244 default 18 if 64BIT
>> 3245 default 15
>> 3246
>> 3247 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3248 default 8
>> 3249
>> 3250 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3251 default 15
>> 3252
>> 3253 config I8253
>> 3254 bool
>> 3255 select CLKSRC_I8253
>> 3256 select CLKEVT_I8253
>> 3257 select MIPS_EXTERNAL_TIMER
245 3258
246 config OPENRISC_ESR_EXCEPTION_BUG_CHECK !! 3259 config ZONE_DMA
247 bool "Check for possible ESR exception !! 3260 bool
248 default n !! 3261
>> 3262 config ZONE_DMA32
>> 3263 bool
>> 3264
>> 3265 endmenu
>> 3266
>> 3267 config TRAD_SIGNALS
>> 3268 bool
>> 3269
>> 3270 config MIPS32_COMPAT
>> 3271 bool
>> 3272
>> 3273 config COMPAT
>> 3274 bool
>> 3275
>> 3276 config SYSVIPC_COMPAT
>> 3277 bool
>> 3278
>> 3279 config MIPS32_O32
>> 3280 bool "Kernel support for o32 binaries"
>> 3281 depends on 64BIT
>> 3282 select ARCH_WANT_OLD_COMPAT_IPC
>> 3283 select COMPAT
>> 3284 select MIPS32_COMPAT
>> 3285 select SYSVIPC_COMPAT if SYSVIPC
>> 3286 help
>> 3287 Select this option if you want to run o32 binaries. These are pure
>> 3288 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3289 existing binaries are in this format.
>> 3290
>> 3291 If unsure, say Y.
>> 3292
>> 3293 config MIPS32_N32
>> 3294 bool "Kernel support for n32 binaries"
>> 3295 depends on 64BIT
>> 3296 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3297 select COMPAT
>> 3298 select MIPS32_COMPAT
>> 3299 select SYSVIPC_COMPAT if SYSVIPC
249 help 3300 help
250 This option enables some checks that !! 3301 Select this option if you want to run n32 binaries. These are
251 in kernel. !! 3302 64-bit binaries using 32-bit quantities for addressing and certain
>> 3303 data that would normally be 64-bit. They are used in special
>> 3304 cases.
252 3305
253 Say N if you are unsure. !! 3306 If unsure, say N.
>> 3307
>> 3308 config BINFMT_ELF32
>> 3309 bool
>> 3310 default y if MIPS32_O32 || MIPS32_N32
>> 3311 select ELFCORE
>> 3312
>> 3313 menu "Power management options"
>> 3314
>> 3315 config ARCH_HIBERNATION_POSSIBLE
>> 3316 def_bool y
>> 3317 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3318
>> 3319 config ARCH_SUSPEND_POSSIBLE
>> 3320 def_bool y
>> 3321 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3322
>> 3323 source "kernel/power/Kconfig"
254 3324
255 endmenu 3325 endmenu
256 3326
>> 3327 config MIPS_EXTERNAL_TIMER
>> 3328 bool
>> 3329
>> 3330 menu "CPU Power Management"
>> 3331
>> 3332 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3333 source "drivers/cpufreq/Kconfig"
>> 3334 endif
>> 3335
>> 3336 source "drivers/cpuidle/Kconfig"
>> 3337
257 endmenu 3338 endmenu
>> 3339
>> 3340 source "drivers/firmware/Kconfig"
>> 3341
>> 3342 source "arch/mips/kvm/Kconfig"
>> 3343
>> 3344 source "arch/mips/vdso/Kconfig"
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