1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # !! 2 config MIPS
3 # For a description of the syntax of this conf !! 3 bool
4 # see Documentation/kbuild/kconfig-language.rs !! 4 default y
5 # !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 config OPENRISC !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 def_bool y !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ARCH_32BIT_OFF_T !! 9 select ARCH_HAS_FORTIFY_SOURCE
10 select ARCH_HAS_DMA_SET_UNCACHED !! 10 select ARCH_HAS_KCOV
11 select ARCH_HAS_DMA_CLEAR_UNCACHED !! 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE !! 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
13 select COMMON_CLK !! 13 select ARCH_HAS_STRNCPY_FROM_USER
14 select OF !! 14 select ARCH_HAS_STRNLEN_USER
15 select OF_EARLY_FLATTREE !! 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
16 select IRQ_DOMAIN !! 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
17 select GPIOLIB !! 17 select ARCH_HAS_GCOV_PROFILE_ALL
18 select HAVE_ARCH_TRACEHOOK !! 18 select ARCH_KEEP_MEMBLOCK
19 select SPARSE_IRQ !! 19 select ARCH_SUPPORTS_UPROBES
20 select GENERIC_IRQ_CHIP !! 20 select ARCH_USE_BUILTIN_BSWAP
>> 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
>> 22 select ARCH_USE_MEMTEST
>> 23 select ARCH_USE_QUEUED_RWLOCKS
>> 24 select ARCH_USE_QUEUED_SPINLOCKS
>> 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
>> 27 select ARCH_WANT_IPC_PARSE_VERSION
>> 28 select ARCH_WANT_LD_ORPHAN_WARN
>> 29 select BUILDTIME_TABLE_SORT
>> 30 select CLONE_BACKWARDS
>> 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
>> 32 select CPU_PM if CPU_IDLE
>> 33 select GENERIC_ATOMIC64 if !64BIT
>> 34 select GENERIC_CMOS_UPDATE
>> 35 select GENERIC_CPU_AUTOPROBE
>> 36 select GENERIC_FIND_FIRST_BIT
>> 37 select GENERIC_GETTIMEOFDAY
>> 38 select GENERIC_IOMAP
21 select GENERIC_IRQ_PROBE 39 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP !! 41 select GENERIC_ISA_DMA if EISA
24 select GENERIC_IOREMAP !! 42 select GENERIC_LIB_ASHLDI3
25 select GENERIC_CPU_DEVICES !! 43 select GENERIC_LIB_ASHRDI3
26 select HAVE_PCI !! 44 select GENERIC_LIB_CMPDI2
27 select HAVE_UID16 !! 45 select GENERIC_LIB_LSHRDI3
28 select HAVE_PAGE_SIZE_8KB !! 46 select GENERIC_LIB_UCMPDI2
29 select GENERIC_ATOMIC64 !! 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
30 select GENERIC_CLOCKEVENTS_BROADCAST <<
31 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_SMP_IDLE_THREAD
32 select MODULES_USE_ELF_RELA !! 49 select GENERIC_TIME_VSYSCALL
>> 50 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
>> 51 select HANDLE_DOMAIN_IRQ
>> 52 select HAVE_ARCH_COMPILER_H
>> 53 select HAVE_ARCH_JUMP_LABEL
>> 54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 55 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
>> 57 select HAVE_ARCH_SECCOMP_FILTER
>> 58 select HAVE_ARCH_TRACEHOOK
>> 59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
>> 60 select HAVE_ASM_MODVERSIONS
>> 61 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 62 select HAVE_CONTEXT_TRACKING
>> 63 select HAVE_TIF_NOHZ
>> 64 select HAVE_C_RECORDMCOUNT
>> 65 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DEBUG_STACKOVERFLOW 66 select HAVE_DEBUG_STACKOVERFLOW
34 select OR1K_PIC !! 67 select HAVE_DMA_CONTIGUOUS
35 select CPU_NO_EFFICIENT_FFS if !OPENRI !! 68 select HAVE_DYNAMIC_FTRACE
36 select ARCH_USE_QUEUED_RWLOCKS !! 69 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
37 select OMPIC if SMP !! 70 select HAVE_EXIT_THREAD
38 select PCI_DOMAINS_GENERIC if PCI !! 71 select HAVE_FAST_GUP
39 select PCI_MSI if PCI !! 72 select HAVE_FTRACE_MCOUNT_RECORD
40 select ARCH_WANT_FRAME_POINTERS !! 73 select HAVE_FUNCTION_GRAPH_TRACER
41 select GENERIC_IRQ_MULTI_HANDLER !! 74 select HAVE_FUNCTION_TRACER
42 select MMU_GATHER_NO_RANGE if MMU !! 75 select HAVE_GCC_PLUGINS
>> 76 select HAVE_GENERIC_VDSO
>> 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
>> 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 83 select HAVE_MOD_ARCH_SPECIFIC
>> 84 select HAVE_NMI
>> 85 select HAVE_PATA_PLATFORM
>> 86 select HAVE_PERF_EVENTS
>> 87 select HAVE_PERF_REGS
>> 88 select HAVE_PERF_USER_STACK_DUMP
>> 89 select HAVE_REGS_AND_STACK_ACCESS_API
>> 90 select HAVE_RSEQ
>> 91 select HAVE_SPARSE_SYSCALL_NR
>> 92 select HAVE_STACKPROTECTOR
>> 93 select HAVE_SYSCALL_TRACEPOINTS
>> 94 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
>> 95 select IRQ_FORCED_THREADING
>> 96 select ISA if EISA
>> 97 select MODULES_USE_ELF_REL if MODULES
>> 98 select MODULES_USE_ELF_RELA if MODULES && 64BIT
>> 99 select PERF_USE_VMALLOC
>> 100 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 101 select RTC_LIB
>> 102 select SYSCTL_EXCEPTION_TRACE
43 select TRACE_IRQFLAGS_SUPPORT 103 select TRACE_IRQFLAGS_SUPPORT
>> 104 select VIRT_TO_BUS
>> 105 select ARCH_HAS_ELFCORE_COMPAT
44 106
45 config CPU_BIG_ENDIAN !! 107 config MIPS_FIXUP_BIGPHYS_ADDR
46 def_bool y !! 108 bool
47 109
48 config MMU !! 110 config MIPS_GENERIC
49 def_bool y !! 111 bool
>> 112
>> 113 config MACH_INGENIC
>> 114 bool
>> 115 select SYS_SUPPORTS_32BIT_KERNEL
>> 116 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 117 select SYS_SUPPORTS_ZBOOT
>> 118 select DMA_NONCOHERENT
>> 119 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 120 select IRQ_MIPS_CPU
>> 121 select PINCTRL
>> 122 select GPIOLIB
>> 123 select COMMON_CLK
>> 124 select GENERIC_IRQ_CHIP
>> 125 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 126 select USE_OF
>> 127 select CPU_SUPPORTS_CPUFREQ
>> 128 select MIPS_EXTERNAL_TIMER
>> 129
>> 130 menu "Machine selection"
>> 131
>> 132 choice
>> 133 prompt "System type"
>> 134 default MIPS_GENERIC_KERNEL
>> 135
>> 136 config MIPS_GENERIC_KERNEL
>> 137 bool "Generic board-agnostic MIPS kernel"
>> 138 select ARCH_HAS_SETUP_DMA_OPS
>> 139 select MIPS_GENERIC
>> 140 select BOOT_RAW
>> 141 select BUILTIN_DTB
>> 142 select CEVT_R4K
>> 143 select CLKSRC_MIPS_GIC
>> 144 select COMMON_CLK
>> 145 select CPU_MIPSR2_IRQ_EI
>> 146 select CPU_MIPSR2_IRQ_VI
>> 147 select CSRC_R4K
>> 148 select DMA_NONCOHERENT
>> 149 select HAVE_PCI
>> 150 select IRQ_MIPS_CPU
>> 151 select MIPS_AUTO_PFN_OFFSET
>> 152 select MIPS_CPU_SCACHE
>> 153 select MIPS_GIC
>> 154 select MIPS_L1_CACHE_SHIFT_7
>> 155 select NO_EXCEPT_FILL
>> 156 select PCI_DRIVERS_GENERIC
>> 157 select SMP_UP if SMP
>> 158 select SWAP_IO_SPACE
>> 159 select SYS_HAS_CPU_MIPS32_R1
>> 160 select SYS_HAS_CPU_MIPS32_R2
>> 161 select SYS_HAS_CPU_MIPS32_R6
>> 162 select SYS_HAS_CPU_MIPS64_R1
>> 163 select SYS_HAS_CPU_MIPS64_R2
>> 164 select SYS_HAS_CPU_MIPS64_R6
>> 165 select SYS_SUPPORTS_32BIT_KERNEL
>> 166 select SYS_SUPPORTS_64BIT_KERNEL
>> 167 select SYS_SUPPORTS_BIG_ENDIAN
>> 168 select SYS_SUPPORTS_HIGHMEM
>> 169 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 170 select SYS_SUPPORTS_MICROMIPS
>> 171 select SYS_SUPPORTS_MIPS16
>> 172 select SYS_SUPPORTS_MIPS_CPS
>> 173 select SYS_SUPPORTS_MULTITHREADING
>> 174 select SYS_SUPPORTS_RELOCATABLE
>> 175 select SYS_SUPPORTS_SMARTMIPS
>> 176 select SYS_SUPPORTS_ZBOOT
>> 177 select UHI_BOOT
>> 178 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 179 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 184 select USE_OF
>> 185 help
>> 186 Select this to build a kernel which aims to support multiple boards,
>> 187 generally using a flattened device tree passed from the bootloader
>> 188 using the boot protocol defined in the UHI (Unified Hosting
>> 189 Interface) specification.
>> 190
>> 191 config MIPS_ALCHEMY
>> 192 bool "Alchemy processor based machines"
>> 193 select PHYS_ADDR_T_64BIT
>> 194 select CEVT_R4K
>> 195 select CSRC_R4K
>> 196 select IRQ_MIPS_CPU
>> 197 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 198 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 199 select SYS_HAS_CPU_MIPS32_R1
>> 200 select SYS_SUPPORTS_32BIT_KERNEL
>> 201 select SYS_SUPPORTS_APM_EMULATION
>> 202 select GPIOLIB
>> 203 select SYS_SUPPORTS_ZBOOT
>> 204 select COMMON_CLK
>> 205
>> 206 config AR7
>> 207 bool "Texas Instruments AR7"
>> 208 select BOOT_ELF32
>> 209 select COMMON_CLK
>> 210 select DMA_NONCOHERENT
>> 211 select CEVT_R4K
>> 212 select CSRC_R4K
>> 213 select IRQ_MIPS_CPU
>> 214 select NO_EXCEPT_FILL
>> 215 select SWAP_IO_SPACE
>> 216 select SYS_HAS_CPU_MIPS32_R1
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART16550
>> 222 select GPIOLIB
>> 223 select VLYNQ
>> 224 help
>> 225 Support for the Texas Instruments AR7 System-on-a-Chip
>> 226 family: TNETD7100, 7200 and 7300.
>> 227
>> 228 config ATH25
>> 229 bool "Atheros AR231x/AR531x SoC support"
>> 230 select CEVT_R4K
>> 231 select CSRC_R4K
>> 232 select DMA_NONCOHERENT
>> 233 select IRQ_MIPS_CPU
>> 234 select IRQ_DOMAIN
>> 235 select SYS_HAS_CPU_MIPS32_R1
>> 236 select SYS_SUPPORTS_BIG_ENDIAN
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_HAS_EARLY_PRINTK
>> 239 help
>> 240 Support for Atheros AR231x and Atheros AR531x based boards
>> 241
>> 242 config ATH79
>> 243 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 244 select ARCH_HAS_RESET_CONTROLLER
>> 245 select BOOT_RAW
>> 246 select CEVT_R4K
>> 247 select CSRC_R4K
>> 248 select DMA_NONCOHERENT
>> 249 select GPIOLIB
>> 250 select PINCTRL
>> 251 select COMMON_CLK
>> 252 select IRQ_MIPS_CPU
>> 253 select SYS_HAS_CPU_MIPS32_R2
>> 254 select SYS_HAS_EARLY_PRINTK
>> 255 select SYS_SUPPORTS_32BIT_KERNEL
>> 256 select SYS_SUPPORTS_BIG_ENDIAN
>> 257 select SYS_SUPPORTS_MIPS16
>> 258 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 259 select USE_OF
>> 260 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 261 help
>> 262 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 263
>> 264 config BMIPS_GENERIC
>> 265 bool "Broadcom Generic BMIPS kernel"
>> 266 select ARCH_HAS_RESET_CONTROLLER
>> 267 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 268 select ARCH_HAS_PHYS_TO_DMA
>> 269 select BOOT_RAW
>> 270 select NO_EXCEPT_FILL
>> 271 select USE_OF
>> 272 select CEVT_R4K
>> 273 select CSRC_R4K
>> 274 select SYNC_R4K
>> 275 select COMMON_CLK
>> 276 select BCM6345_L1_IRQ
>> 277 select BCM7038_L1_IRQ
>> 278 select BCM7120_L2_IRQ
>> 279 select BRCMSTB_L2_IRQ
>> 280 select IRQ_MIPS_CPU
>> 281 select DMA_NONCOHERENT
>> 282 select SYS_SUPPORTS_32BIT_KERNEL
>> 283 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 284 select SYS_SUPPORTS_BIG_ENDIAN
>> 285 select SYS_SUPPORTS_HIGHMEM
>> 286 select SYS_HAS_CPU_BMIPS32_3300
>> 287 select SYS_HAS_CPU_BMIPS4350
>> 288 select SYS_HAS_CPU_BMIPS4380
>> 289 select SYS_HAS_CPU_BMIPS5000
>> 290 select SWAP_IO_SPACE
>> 291 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 294 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 295 select HARDIRQS_SW_RESEND
>> 296 help
>> 297 Build a generic DT-based kernel image that boots on select
>> 298 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 299 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 300 must be set appropriately for your board.
>> 301
>> 302 config BCM47XX
>> 303 bool "Broadcom BCM47XX based boards"
>> 304 select BOOT_RAW
>> 305 select CEVT_R4K
>> 306 select CSRC_R4K
>> 307 select DMA_NONCOHERENT
>> 308 select HAVE_PCI
>> 309 select IRQ_MIPS_CPU
>> 310 select SYS_HAS_CPU_MIPS32_R1
>> 311 select NO_EXCEPT_FILL
>> 312 select SYS_SUPPORTS_32BIT_KERNEL
>> 313 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 314 select SYS_SUPPORTS_MIPS16
>> 315 select SYS_SUPPORTS_ZBOOT
>> 316 select SYS_HAS_EARLY_PRINTK
>> 317 select USE_GENERIC_EARLY_PRINTK_8250
>> 318 select GPIOLIB
>> 319 select LEDS_GPIO_REGISTER
>> 320 select BCM47XX_NVRAM
>> 321 select BCM47XX_SPROM
>> 322 select BCM47XX_SSB if !BCM47XX_BCMA
>> 323 help
>> 324 Support for BCM47XX based boards
>> 325
>> 326 config BCM63XX
>> 327 bool "Broadcom BCM63XX based boards"
>> 328 select BOOT_RAW
>> 329 select CEVT_R4K
>> 330 select CSRC_R4K
>> 331 select SYNC_R4K
>> 332 select DMA_NONCOHERENT
>> 333 select IRQ_MIPS_CPU
>> 334 select SYS_SUPPORTS_32BIT_KERNEL
>> 335 select SYS_SUPPORTS_BIG_ENDIAN
>> 336 select SYS_HAS_EARLY_PRINTK
>> 337 select SYS_HAS_CPU_BMIPS32_3300
>> 338 select SYS_HAS_CPU_BMIPS4350
>> 339 select SYS_HAS_CPU_BMIPS4380
>> 340 select SWAP_IO_SPACE
>> 341 select GPIOLIB
>> 342 select MIPS_L1_CACHE_SHIFT_4
>> 343 select HAVE_LEGACY_CLK
>> 344 help
>> 345 Support for BCM63XX based boards
>> 346
>> 347 config MIPS_COBALT
>> 348 bool "Cobalt Server"
>> 349 select CEVT_R4K
>> 350 select CSRC_R4K
>> 351 select CEVT_GT641XX
>> 352 select DMA_NONCOHERENT
>> 353 select FORCE_PCI
>> 354 select I8253
>> 355 select I8259
>> 356 select IRQ_MIPS_CPU
>> 357 select IRQ_GT641XX
>> 358 select PCI_GT64XXX_PCI0
>> 359 select SYS_HAS_CPU_NEVADA
>> 360 select SYS_HAS_EARLY_PRINTK
>> 361 select SYS_SUPPORTS_32BIT_KERNEL
>> 362 select SYS_SUPPORTS_64BIT_KERNEL
>> 363 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 364 select USE_GENERIC_EARLY_PRINTK_8250
>> 365
>> 366 config MACH_DECSTATION
>> 367 bool "DECstations"
>> 368 select BOOT_ELF32
>> 369 select CEVT_DS1287
>> 370 select CEVT_R4K if CPU_R4X00
>> 371 select CSRC_IOASIC
>> 372 select CSRC_R4K if CPU_R4X00
>> 373 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 374 select CPU_R4000_WORKAROUNDS if 64BIT
>> 375 select CPU_R4400_WORKAROUNDS if 64BIT
>> 376 select DMA_NONCOHERENT
>> 377 select NO_IOPORT_MAP
>> 378 select IRQ_MIPS_CPU
>> 379 select SYS_HAS_CPU_R3000
>> 380 select SYS_HAS_CPU_R4X00
>> 381 select SYS_SUPPORTS_32BIT_KERNEL
>> 382 select SYS_SUPPORTS_64BIT_KERNEL
>> 383 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 384 select SYS_SUPPORTS_128HZ
>> 385 select SYS_SUPPORTS_256HZ
>> 386 select SYS_SUPPORTS_1024HZ
>> 387 select MIPS_L1_CACHE_SHIFT_4
>> 388 help
>> 389 This enables support for DEC's MIPS based workstations. For details
>> 390 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 391 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 392
>> 393 If you have one of the following DECstation Models you definitely
>> 394 want to choose R4xx0 for the CPU Type:
>> 395
>> 396 DECstation 5000/50
>> 397 DECstation 5000/150
>> 398 DECstation 5000/260
>> 399 DECsystem 5900/260
>> 400
>> 401 otherwise choose R3000.
>> 402
>> 403 config MACH_JAZZ
>> 404 bool "Jazz family of machines"
>> 405 select ARC_MEMORY
>> 406 select ARC_PROMLIB
>> 407 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 408 select ARCH_MIGHT_HAVE_PC_SERIO
>> 409 select DMA_OPS
>> 410 select FW_ARC
>> 411 select FW_ARC32
>> 412 select ARCH_MAY_HAVE_PC_FDC
>> 413 select CEVT_R4K
>> 414 select CSRC_R4K
>> 415 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 416 select GENERIC_ISA_DMA
>> 417 select HAVE_PCSPKR_PLATFORM
>> 418 select IRQ_MIPS_CPU
>> 419 select I8253
>> 420 select I8259
>> 421 select ISA
>> 422 select SYS_HAS_CPU_R4X00
>> 423 select SYS_SUPPORTS_32BIT_KERNEL
>> 424 select SYS_SUPPORTS_64BIT_KERNEL
>> 425 select SYS_SUPPORTS_100HZ
>> 426 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 427 help
>> 428 This a family of machines based on the MIPS R4030 chipset which was
>> 429 used by several vendors to build RISC/os and Windows NT workstations.
>> 430 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 431 Olivetti M700-10 workstations.
>> 432
>> 433 config MACH_INGENIC_SOC
>> 434 bool "Ingenic SoC based machines"
>> 435 select MIPS_GENERIC
>> 436 select MACH_INGENIC
>> 437 select SYS_SUPPORTS_ZBOOT_UART16550
>> 438 select CPU_SUPPORTS_CPUFREQ
>> 439 select MIPS_EXTERNAL_TIMER
>> 440
>> 441 config LANTIQ
>> 442 bool "Lantiq based platforms"
>> 443 select DMA_NONCOHERENT
>> 444 select IRQ_MIPS_CPU
>> 445 select CEVT_R4K
>> 446 select CSRC_R4K
>> 447 select SYS_HAS_CPU_MIPS32_R1
>> 448 select SYS_HAS_CPU_MIPS32_R2
>> 449 select SYS_SUPPORTS_BIG_ENDIAN
>> 450 select SYS_SUPPORTS_32BIT_KERNEL
>> 451 select SYS_SUPPORTS_MIPS16
>> 452 select SYS_SUPPORTS_MULTITHREADING
>> 453 select SYS_SUPPORTS_VPE_LOADER
>> 454 select SYS_HAS_EARLY_PRINTK
>> 455 select GPIOLIB
>> 456 select SWAP_IO_SPACE
>> 457 select BOOT_RAW
>> 458 select HAVE_LEGACY_CLK
>> 459 select USE_OF
>> 460 select PINCTRL
>> 461 select PINCTRL_LANTIQ
>> 462 select ARCH_HAS_RESET_CONTROLLER
>> 463 select RESET_CONTROLLER
>> 464
>> 465 config MACH_LOONGSON32
>> 466 bool "Loongson 32-bit family of machines"
>> 467 select SYS_SUPPORTS_ZBOOT
>> 468 help
>> 469 This enables support for the Loongson-1 family of machines.
>> 470
>> 471 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 472 the Institute of Computing Technology (ICT), Chinese Academy of
>> 473 Sciences (CAS).
>> 474
>> 475 config MACH_LOONGSON2EF
>> 476 bool "Loongson-2E/F family of machines"
>> 477 select SYS_SUPPORTS_ZBOOT
>> 478 help
>> 479 This enables the support of early Loongson-2E/F family of machines.
>> 480
>> 481 config MACH_LOONGSON64
>> 482 bool "Loongson 64-bit family of machines"
>> 483 select ARCH_DMA_DEFAULT_COHERENT
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 help
>> 517 This enables the support of Loongson-2/3 family of machines.
>> 518
>> 519 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 520 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 521 and Loongson-2F which will be removed), developed by the Institute
>> 522 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 523
>> 524 config MIPS_MALTA
>> 525 bool "MIPS Malta board"
>> 526 select ARCH_MAY_HAVE_PC_FDC
>> 527 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 528 select ARCH_MIGHT_HAVE_PC_SERIO
>> 529 select BOOT_ELF32
>> 530 select BOOT_RAW
>> 531 select BUILTIN_DTB
>> 532 select CEVT_R4K
>> 533 select CLKSRC_MIPS_GIC
>> 534 select COMMON_CLK
>> 535 select CSRC_R4K
>> 536 select DMA_NONCOHERENT
>> 537 select GENERIC_ISA_DMA
>> 538 select HAVE_PCSPKR_PLATFORM
>> 539 select HAVE_PCI
>> 540 select I8253
>> 541 select I8259
>> 542 select IRQ_MIPS_CPU
>> 543 select MIPS_BONITO64
>> 544 select MIPS_CPU_SCACHE
>> 545 select MIPS_GIC
>> 546 select MIPS_L1_CACHE_SHIFT_6
>> 547 select MIPS_MSC
>> 548 select PCI_GT64XXX_PCI0
>> 549 select SMP_UP if SMP
>> 550 select SWAP_IO_SPACE
>> 551 select SYS_HAS_CPU_MIPS32_R1
>> 552 select SYS_HAS_CPU_MIPS32_R2
>> 553 select SYS_HAS_CPU_MIPS32_R3_5
>> 554 select SYS_HAS_CPU_MIPS32_R5
>> 555 select SYS_HAS_CPU_MIPS32_R6
>> 556 select SYS_HAS_CPU_MIPS64_R1
>> 557 select SYS_HAS_CPU_MIPS64_R2
>> 558 select SYS_HAS_CPU_MIPS64_R6
>> 559 select SYS_HAS_CPU_NEVADA
>> 560 select SYS_HAS_CPU_RM7000
>> 561 select SYS_SUPPORTS_32BIT_KERNEL
>> 562 select SYS_SUPPORTS_64BIT_KERNEL
>> 563 select SYS_SUPPORTS_BIG_ENDIAN
>> 564 select SYS_SUPPORTS_HIGHMEM
>> 565 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 566 select SYS_SUPPORTS_MICROMIPS
>> 567 select SYS_SUPPORTS_MIPS16
>> 568 select SYS_SUPPORTS_MIPS_CMP
>> 569 select SYS_SUPPORTS_MIPS_CPS
>> 570 select SYS_SUPPORTS_MULTITHREADING
>> 571 select SYS_SUPPORTS_RELOCATABLE
>> 572 select SYS_SUPPORTS_SMARTMIPS
>> 573 select SYS_SUPPORTS_VPE_LOADER
>> 574 select SYS_SUPPORTS_ZBOOT
>> 575 select USE_OF
>> 576 select WAR_ICACHE_REFILLS
>> 577 select ZONE_DMA32 if 64BIT
>> 578 help
>> 579 This enables support for the MIPS Technologies Malta evaluation
>> 580 board.
>> 581
>> 582 config MACH_PIC32
>> 583 bool "Microchip PIC32 Family"
>> 584 help
>> 585 This enables support for the Microchip PIC32 family of platforms.
>> 586
>> 587 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 588 microcontrollers.
>> 589
>> 590 config MACH_VR41XX
>> 591 bool "NEC VR4100 series based machines"
>> 592 select CEVT_R4K
>> 593 select CSRC_R4K
>> 594 select SYS_HAS_CPU_VR41XX
>> 595 select SYS_SUPPORTS_MIPS16
>> 596 select GPIOLIB
>> 597
>> 598 config MACH_NINTENDO64
>> 599 bool "Nintendo 64 console"
>> 600 select CEVT_R4K
>> 601 select CSRC_R4K
>> 602 select SYS_HAS_CPU_R4300
>> 603 select SYS_SUPPORTS_BIG_ENDIAN
>> 604 select SYS_SUPPORTS_ZBOOT
>> 605 select SYS_SUPPORTS_32BIT_KERNEL
>> 606 select SYS_SUPPORTS_64BIT_KERNEL
>> 607 select DMA_NONCOHERENT
>> 608 select IRQ_MIPS_CPU
>> 609
>> 610 config RALINK
>> 611 bool "Ralink based machines"
>> 612 select CEVT_R4K
>> 613 select COMMON_CLK
>> 614 select CSRC_R4K
>> 615 select BOOT_RAW
>> 616 select DMA_NONCOHERENT
>> 617 select IRQ_MIPS_CPU
>> 618 select USE_OF
>> 619 select SYS_HAS_CPU_MIPS32_R1
>> 620 select SYS_HAS_CPU_MIPS32_R2
>> 621 select SYS_SUPPORTS_32BIT_KERNEL
>> 622 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 623 select SYS_SUPPORTS_MIPS16
>> 624 select SYS_SUPPORTS_ZBOOT
>> 625 select SYS_HAS_EARLY_PRINTK
>> 626 select ARCH_HAS_RESET_CONTROLLER
>> 627 select RESET_CONTROLLER
>> 628
>> 629 config MACH_REALTEK_RTL
>> 630 bool "Realtek RTL838x/RTL839x based machines"
>> 631 select MIPS_GENERIC
>> 632 select DMA_NONCOHERENT
>> 633 select IRQ_MIPS_CPU
>> 634 select CSRC_R4K
>> 635 select CEVT_R4K
>> 636 select SYS_HAS_CPU_MIPS32_R1
>> 637 select SYS_HAS_CPU_MIPS32_R2
>> 638 select SYS_SUPPORTS_BIG_ENDIAN
>> 639 select SYS_SUPPORTS_32BIT_KERNEL
>> 640 select SYS_SUPPORTS_MIPS16
>> 641 select SYS_SUPPORTS_MULTITHREADING
>> 642 select SYS_SUPPORTS_VPE_LOADER
>> 643 select SYS_HAS_EARLY_PRINTK
>> 644 select SYS_HAS_EARLY_PRINTK_8250
>> 645 select USE_GENERIC_EARLY_PRINTK_8250
>> 646 select BOOT_RAW
>> 647 select PINCTRL
>> 648 select USE_OF
>> 649
>> 650 config SGI_IP22
>> 651 bool "SGI IP22 (Indy/Indigo2)"
>> 652 select ARC_MEMORY
>> 653 select ARC_PROMLIB
>> 654 select FW_ARC
>> 655 select FW_ARC32
>> 656 select ARCH_MIGHT_HAVE_PC_SERIO
>> 657 select BOOT_ELF32
>> 658 select CEVT_R4K
>> 659 select CSRC_R4K
>> 660 select DEFAULT_SGI_PARTITION
>> 661 select DMA_NONCOHERENT
>> 662 select HAVE_EISA
>> 663 select I8253
>> 664 select I8259
>> 665 select IP22_CPU_SCACHE
>> 666 select IRQ_MIPS_CPU
>> 667 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 668 select SGI_HAS_I8042
>> 669 select SGI_HAS_INDYDOG
>> 670 select SGI_HAS_HAL2
>> 671 select SGI_HAS_SEEQ
>> 672 select SGI_HAS_WD93
>> 673 select SGI_HAS_ZILOG
>> 674 select SWAP_IO_SPACE
>> 675 select SYS_HAS_CPU_R4X00
>> 676 select SYS_HAS_CPU_R5000
>> 677 select SYS_HAS_EARLY_PRINTK
>> 678 select SYS_SUPPORTS_32BIT_KERNEL
>> 679 select SYS_SUPPORTS_64BIT_KERNEL
>> 680 select SYS_SUPPORTS_BIG_ENDIAN
>> 681 select WAR_R4600_V1_INDEX_ICACHEOP
>> 682 select WAR_R4600_V1_HIT_CACHEOP
>> 683 select WAR_R4600_V2_HIT_CACHEOP
>> 684 select MIPS_L1_CACHE_SHIFT_7
>> 685 help
>> 686 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 687 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 688 that runs on these, say Y here.
>> 689
>> 690 config SGI_IP27
>> 691 bool "SGI IP27 (Origin200/2000)"
>> 692 select ARCH_HAS_PHYS_TO_DMA
>> 693 select ARCH_SPARSEMEM_ENABLE
>> 694 select FW_ARC
>> 695 select FW_ARC64
>> 696 select ARC_CMDLINE_ONLY
>> 697 select BOOT_ELF64
>> 698 select DEFAULT_SGI_PARTITION
>> 699 select FORCE_PCI
>> 700 select SYS_HAS_EARLY_PRINTK
>> 701 select HAVE_PCI
>> 702 select IRQ_MIPS_CPU
>> 703 select IRQ_DOMAIN_HIERARCHY
>> 704 select NR_CPUS_DEFAULT_64
>> 705 select PCI_DRIVERS_GENERIC
>> 706 select PCI_XTALK_BRIDGE
>> 707 select SYS_HAS_CPU_R10000
>> 708 select SYS_SUPPORTS_64BIT_KERNEL
>> 709 select SYS_SUPPORTS_BIG_ENDIAN
>> 710 select SYS_SUPPORTS_NUMA
>> 711 select SYS_SUPPORTS_SMP
>> 712 select WAR_R10000_LLSC
>> 713 select MIPS_L1_CACHE_SHIFT_7
>> 714 select NUMA
>> 715 help
>> 716 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 717 workstations. To compile a Linux kernel that runs on these, say Y
>> 718 here.
>> 719
>> 720 config SGI_IP28
>> 721 bool "SGI IP28 (Indigo2 R10k)"
>> 722 select ARC_MEMORY
>> 723 select ARC_PROMLIB
>> 724 select FW_ARC
>> 725 select FW_ARC64
>> 726 select ARCH_MIGHT_HAVE_PC_SERIO
>> 727 select BOOT_ELF64
>> 728 select CEVT_R4K
>> 729 select CSRC_R4K
>> 730 select DEFAULT_SGI_PARTITION
>> 731 select DMA_NONCOHERENT
>> 732 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 733 select IRQ_MIPS_CPU
>> 734 select HAVE_EISA
>> 735 select I8253
>> 736 select I8259
>> 737 select SGI_HAS_I8042
>> 738 select SGI_HAS_INDYDOG
>> 739 select SGI_HAS_HAL2
>> 740 select SGI_HAS_SEEQ
>> 741 select SGI_HAS_WD93
>> 742 select SGI_HAS_ZILOG
>> 743 select SWAP_IO_SPACE
>> 744 select SYS_HAS_CPU_R10000
>> 745 select SYS_HAS_EARLY_PRINTK
>> 746 select SYS_SUPPORTS_64BIT_KERNEL
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 select WAR_R10000_LLSC
>> 749 select MIPS_L1_CACHE_SHIFT_7
>> 750 help
>> 751 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 752 kernel that runs on these, say Y here.
>> 753
>> 754 config SGI_IP30
>> 755 bool "SGI IP30 (Octane/Octane2)"
>> 756 select ARCH_HAS_PHYS_TO_DMA
>> 757 select FW_ARC
>> 758 select FW_ARC64
>> 759 select BOOT_ELF64
>> 760 select CEVT_R4K
>> 761 select CSRC_R4K
>> 762 select FORCE_PCI
>> 763 select SYNC_R4K if SMP
>> 764 select ZONE_DMA32
>> 765 select HAVE_PCI
>> 766 select IRQ_MIPS_CPU
>> 767 select IRQ_DOMAIN_HIERARCHY
>> 768 select NR_CPUS_DEFAULT_2
>> 769 select PCI_DRIVERS_GENERIC
>> 770 select PCI_XTALK_BRIDGE
>> 771 select SYS_HAS_EARLY_PRINTK
>> 772 select SYS_HAS_CPU_R10000
>> 773 select SYS_SUPPORTS_64BIT_KERNEL
>> 774 select SYS_SUPPORTS_BIG_ENDIAN
>> 775 select SYS_SUPPORTS_SMP
>> 776 select WAR_R10000_LLSC
>> 777 select MIPS_L1_CACHE_SHIFT_7
>> 778 select ARC_MEMORY
>> 779 help
>> 780 These are the SGI Octane and Octane2 graphics workstations. To
>> 781 compile a Linux kernel that runs on these, say Y here.
>> 782
>> 783 config SGI_IP32
>> 784 bool "SGI IP32 (O2)"
>> 785 select ARC_MEMORY
>> 786 select ARC_PROMLIB
>> 787 select ARCH_HAS_PHYS_TO_DMA
>> 788 select FW_ARC
>> 789 select FW_ARC32
>> 790 select BOOT_ELF32
>> 791 select CEVT_R4K
>> 792 select CSRC_R4K
>> 793 select DMA_NONCOHERENT
>> 794 select HAVE_PCI
>> 795 select IRQ_MIPS_CPU
>> 796 select R5000_CPU_SCACHE
>> 797 select RM7000_CPU_SCACHE
>> 798 select SYS_HAS_CPU_R5000
>> 799 select SYS_HAS_CPU_R10000 if BROKEN
>> 800 select SYS_HAS_CPU_RM7000
>> 801 select SYS_HAS_CPU_NEVADA
>> 802 select SYS_SUPPORTS_64BIT_KERNEL
>> 803 select SYS_SUPPORTS_BIG_ENDIAN
>> 804 select WAR_ICACHE_REFILLS
>> 805 help
>> 806 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 807
>> 808 config SIBYTE_CRHINE
>> 809 bool "Sibyte BCM91120C-CRhine"
>> 810 select BOOT_ELF32
>> 811 select SIBYTE_BCM1120
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 816
>> 817 config SIBYTE_CARMEL
>> 818 bool "Sibyte BCM91120x-Carmel"
>> 819 select BOOT_ELF32
>> 820 select SIBYTE_BCM1120
>> 821 select SWAP_IO_SPACE
>> 822 select SYS_HAS_CPU_SB1
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825
>> 826 config SIBYTE_CRHONE
>> 827 bool "Sibyte BCM91125C-CRhone"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_BCM1125
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_HIGHMEM
>> 834 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 835
>> 836 config SIBYTE_RHONE
>> 837 bool "Sibyte BCM91125E-Rhone"
>> 838 select BOOT_ELF32
>> 839 select SIBYTE_BCM1125H
>> 840 select SWAP_IO_SPACE
>> 841 select SYS_HAS_CPU_SB1
>> 842 select SYS_SUPPORTS_BIG_ENDIAN
>> 843 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 844
>> 845 config SIBYTE_SWARM
>> 846 bool "Sibyte BCM91250A-SWARM"
>> 847 select BOOT_ELF32
>> 848 select HAVE_PATA_PLATFORM
>> 849 select SIBYTE_SB1250
>> 850 select SWAP_IO_SPACE
>> 851 select SYS_HAS_CPU_SB1
>> 852 select SYS_SUPPORTS_BIG_ENDIAN
>> 853 select SYS_SUPPORTS_HIGHMEM
>> 854 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 855 select ZONE_DMA32 if 64BIT
>> 856 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 857
>> 858 config SIBYTE_LITTLESUR
>> 859 bool "Sibyte BCM91250C2-LittleSur"
>> 860 select BOOT_ELF32
>> 861 select HAVE_PATA_PLATFORM
>> 862 select SIBYTE_SB1250
>> 863 select SWAP_IO_SPACE
>> 864 select SYS_HAS_CPU_SB1
>> 865 select SYS_SUPPORTS_BIG_ENDIAN
>> 866 select SYS_SUPPORTS_HIGHMEM
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 select ZONE_DMA32 if 64BIT
>> 869
>> 870 config SIBYTE_SENTOSA
>> 871 bool "Sibyte BCM91250E-Sentosa"
>> 872 select BOOT_ELF32
>> 873 select SIBYTE_SB1250
>> 874 select SWAP_IO_SPACE
>> 875 select SYS_HAS_CPU_SB1
>> 876 select SYS_SUPPORTS_BIG_ENDIAN
>> 877 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 878 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 879
>> 880 config SIBYTE_BIGSUR
>> 881 bool "Sibyte BCM91480B-BigSur"
>> 882 select BOOT_ELF32
>> 883 select NR_CPUS_DEFAULT_4
>> 884 select SIBYTE_BCM1x80
>> 885 select SWAP_IO_SPACE
>> 886 select SYS_HAS_CPU_SB1
>> 887 select SYS_SUPPORTS_BIG_ENDIAN
>> 888 select SYS_SUPPORTS_HIGHMEM
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select ZONE_DMA32 if 64BIT
>> 891 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 892
>> 893 config SNI_RM
>> 894 bool "SNI RM200/300/400"
>> 895 select ARC_MEMORY
>> 896 select ARC_PROMLIB
>> 897 select FW_ARC if CPU_LITTLE_ENDIAN
>> 898 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 899 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 900 select ARCH_MAY_HAVE_PC_FDC
>> 901 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 902 select ARCH_MIGHT_HAVE_PC_SERIO
>> 903 select BOOT_ELF32
>> 904 select CEVT_R4K
>> 905 select CSRC_R4K
>> 906 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 907 select DMA_NONCOHERENT
>> 908 select GENERIC_ISA_DMA
>> 909 select HAVE_EISA
>> 910 select HAVE_PCSPKR_PLATFORM
>> 911 select HAVE_PCI
>> 912 select IRQ_MIPS_CPU
>> 913 select I8253
>> 914 select I8259
>> 915 select ISA
>> 916 select MIPS_L1_CACHE_SHIFT_6
>> 917 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 918 select SYS_HAS_CPU_R4X00
>> 919 select SYS_HAS_CPU_R5000
>> 920 select SYS_HAS_CPU_R10000
>> 921 select R5000_CPU_SCACHE
>> 922 select SYS_HAS_EARLY_PRINTK
>> 923 select SYS_SUPPORTS_32BIT_KERNEL
>> 924 select SYS_SUPPORTS_64BIT_KERNEL
>> 925 select SYS_SUPPORTS_BIG_ENDIAN
>> 926 select SYS_SUPPORTS_HIGHMEM
>> 927 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 928 select WAR_R4600_V2_HIT_CACHEOP
>> 929 help
>> 930 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 931 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 932 Technology and now in turn merged with Fujitsu. Say Y here to
>> 933 support this machine type.
>> 934
>> 935 config MACH_TX39XX
>> 936 bool "Toshiba TX39 series based machines"
>> 937
>> 938 config MACH_TX49XX
>> 939 bool "Toshiba TX49 series based machines"
>> 940 select WAR_TX49XX_ICACHE_INDEX_INV
>> 941
>> 942 config MIKROTIK_RB532
>> 943 bool "Mikrotik RB532 boards"
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select DMA_NONCOHERENT
>> 947 select HAVE_PCI
>> 948 select IRQ_MIPS_CPU
>> 949 select SYS_HAS_CPU_MIPS32_R1
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 952 select SWAP_IO_SPACE
>> 953 select BOOT_RAW
>> 954 select GPIOLIB
>> 955 select MIPS_L1_CACHE_SHIFT_4
>> 956 help
>> 957 Support the Mikrotik(tm) RouterBoard 532 series,
>> 958 based on the IDT RC32434 SoC.
>> 959
>> 960 config CAVIUM_OCTEON_SOC
>> 961 bool "Cavium Networks Octeon SoC based boards"
>> 962 select CEVT_R4K
>> 963 select ARCH_HAS_PHYS_TO_DMA
>> 964 select HAVE_RAPIDIO
>> 965 select PHYS_ADDR_T_64BIT
>> 966 select SYS_SUPPORTS_64BIT_KERNEL
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select EDAC_SUPPORT
>> 969 select EDAC_ATOMIC_SCRUB
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 974 select HAVE_PCI
>> 975 select HAVE_PLAT_DELAY
>> 976 select HAVE_PLAT_FW_INIT_CMDLINE
>> 977 select HAVE_PLAT_MEMCPY
>> 978 select ZONE_DMA32
>> 979 select GPIOLIB
>> 980 select USE_OF
>> 981 select ARCH_SPARSEMEM_ENABLE
>> 982 select SYS_SUPPORTS_SMP
>> 983 select NR_CPUS_DEFAULT_64
>> 984 select MIPS_NR_CPU_NR_MAP_1024
>> 985 select BUILTIN_DTB
>> 986 select MTD
>> 987 select MTD_COMPLEX_MAPPINGS
>> 988 select SWIOTLB
>> 989 select SYS_SUPPORTS_RELOCATABLE
>> 990 help
>> 991 This option supports all of the Octeon reference boards from Cavium
>> 992 Networks. It builds a kernel that dynamically determines the Octeon
>> 993 CPU type and supports all known board reference implementations.
>> 994 Some of the supported boards are:
>> 995 EBT3000
>> 996 EBH3000
>> 997 EBH3100
>> 998 Thunder
>> 999 Kodama
>> 1000 Hikari
>> 1001 Say Y here for most Octeon reference boards.
>> 1002
>> 1003 config NLM_XLR_BOARD
>> 1004 bool "Netlogic XLR/XLS based systems"
>> 1005 select BOOT_ELF32
>> 1006 select NLM_COMMON
>> 1007 select SYS_HAS_CPU_XLR
>> 1008 select SYS_SUPPORTS_SMP
>> 1009 select HAVE_PCI
>> 1010 select SWAP_IO_SPACE
>> 1011 select SYS_SUPPORTS_32BIT_KERNEL
>> 1012 select SYS_SUPPORTS_64BIT_KERNEL
>> 1013 select PHYS_ADDR_T_64BIT
>> 1014 select SYS_SUPPORTS_BIG_ENDIAN
>> 1015 select SYS_SUPPORTS_HIGHMEM
>> 1016 select NR_CPUS_DEFAULT_32
>> 1017 select CEVT_R4K
>> 1018 select CSRC_R4K
>> 1019 select IRQ_MIPS_CPU
>> 1020 select ZONE_DMA32 if 64BIT
>> 1021 select SYNC_R4K
>> 1022 select SYS_HAS_EARLY_PRINTK
>> 1023 select SYS_SUPPORTS_ZBOOT
>> 1024 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1025 help
>> 1026 Support for systems based on Netlogic XLR and XLS processors.
>> 1027 Say Y here if you have a XLR or XLS based board.
>> 1028
>> 1029 config NLM_XLP_BOARD
>> 1030 bool "Netlogic XLP based systems"
>> 1031 select BOOT_ELF32
>> 1032 select NLM_COMMON
>> 1033 select SYS_HAS_CPU_XLP
>> 1034 select SYS_SUPPORTS_SMP
>> 1035 select HAVE_PCI
>> 1036 select SYS_SUPPORTS_32BIT_KERNEL
>> 1037 select SYS_SUPPORTS_64BIT_KERNEL
>> 1038 select PHYS_ADDR_T_64BIT
>> 1039 select GPIOLIB
>> 1040 select SYS_SUPPORTS_BIG_ENDIAN
>> 1041 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1042 select SYS_SUPPORTS_HIGHMEM
>> 1043 select NR_CPUS_DEFAULT_32
>> 1044 select CEVT_R4K
>> 1045 select CSRC_R4K
>> 1046 select IRQ_MIPS_CPU
>> 1047 select ZONE_DMA32 if 64BIT
>> 1048 select SYNC_R4K
>> 1049 select SYS_HAS_EARLY_PRINTK
>> 1050 select USE_OF
>> 1051 select SYS_SUPPORTS_ZBOOT
>> 1052 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1053 help
>> 1054 This board is based on Netlogic XLP Processor.
>> 1055 Say Y here if you have a XLP based board.
>> 1056
>> 1057 endchoice
>> 1058
>> 1059 source "arch/mips/alchemy/Kconfig"
>> 1060 source "arch/mips/ath25/Kconfig"
>> 1061 source "arch/mips/ath79/Kconfig"
>> 1062 source "arch/mips/bcm47xx/Kconfig"
>> 1063 source "arch/mips/bcm63xx/Kconfig"
>> 1064 source "arch/mips/bmips/Kconfig"
>> 1065 source "arch/mips/generic/Kconfig"
>> 1066 source "arch/mips/ingenic/Kconfig"
>> 1067 source "arch/mips/jazz/Kconfig"
>> 1068 source "arch/mips/lantiq/Kconfig"
>> 1069 source "arch/mips/pic32/Kconfig"
>> 1070 source "arch/mips/ralink/Kconfig"
>> 1071 source "arch/mips/sgi-ip27/Kconfig"
>> 1072 source "arch/mips/sibyte/Kconfig"
>> 1073 source "arch/mips/txx9/Kconfig"
>> 1074 source "arch/mips/vr41xx/Kconfig"
>> 1075 source "arch/mips/cavium-octeon/Kconfig"
>> 1076 source "arch/mips/loongson2ef/Kconfig"
>> 1077 source "arch/mips/loongson32/Kconfig"
>> 1078 source "arch/mips/loongson64/Kconfig"
>> 1079 source "arch/mips/netlogic/Kconfig"
>> 1080
>> 1081 endmenu
50 1082
51 config GENERIC_HWEIGHT 1083 config GENERIC_HWEIGHT
52 def_bool y !! 1084 bool
>> 1085 default y
>> 1086
>> 1087 config GENERIC_CALIBRATE_DELAY
>> 1088 bool
>> 1089 default y
>> 1090
>> 1091 config SCHED_OMIT_FRAME_POINTER
>> 1092 bool
>> 1093 default y
>> 1094
>> 1095 #
>> 1096 # Select some configuration options automatically based on user selections.
>> 1097 #
>> 1098 config FW_ARC
>> 1099 bool
>> 1100
>> 1101 config ARCH_MAY_HAVE_PC_FDC
>> 1102 bool
>> 1103
>> 1104 config BOOT_RAW
>> 1105 bool
>> 1106
>> 1107 config CEVT_BCM1480
>> 1108 bool
>> 1109
>> 1110 config CEVT_DS1287
>> 1111 bool
>> 1112
>> 1113 config CEVT_GT641XX
>> 1114 bool
>> 1115
>> 1116 config CEVT_R4K
>> 1117 bool
>> 1118
>> 1119 config CEVT_SB1250
>> 1120 bool
>> 1121
>> 1122 config CEVT_TXX9
>> 1123 bool
>> 1124
>> 1125 config CSRC_BCM1480
>> 1126 bool
>> 1127
>> 1128 config CSRC_IOASIC
>> 1129 bool
>> 1130
>> 1131 config CSRC_R4K
>> 1132 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1133 bool
>> 1134
>> 1135 config CSRC_SB1250
>> 1136 bool
>> 1137
>> 1138 config MIPS_CLOCK_VSYSCALL
>> 1139 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1140
>> 1141 config GPIO_TXX9
>> 1142 select GPIOLIB
>> 1143 bool
>> 1144
>> 1145 config FW_CFE
>> 1146 bool
>> 1147
>> 1148 config ARCH_SUPPORTS_UPROBES
>> 1149 bool
>> 1150
>> 1151 config DMA_PERDEV_COHERENT
>> 1152 bool
>> 1153 select ARCH_HAS_SETUP_DMA_OPS
>> 1154 select DMA_NONCOHERENT
>> 1155
>> 1156 config DMA_NONCOHERENT
>> 1157 bool
>> 1158 #
>> 1159 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1160 # Attribute bits. It is believed that the uncached access through
>> 1161 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1162 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1163 # significant advantages.
>> 1164 #
>> 1165 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1166 select ARCH_HAS_DMA_PREP_COHERENT
>> 1167 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1168 select ARCH_HAS_DMA_SET_UNCACHED
>> 1169 select DMA_NONCOHERENT_MMAP
>> 1170 select NEED_DMA_MAP_STATE
>> 1171
>> 1172 config SYS_HAS_EARLY_PRINTK
>> 1173 bool
>> 1174
>> 1175 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1176 bool
>> 1177
>> 1178 config MIPS_BONITO64
>> 1179 bool
>> 1180
>> 1181 config MIPS_MSC
>> 1182 bool
>> 1183
>> 1184 config SYNC_R4K
>> 1185 bool
53 1186
54 config NO_IOPORT_MAP 1187 config NO_IOPORT_MAP
55 def_bool y !! 1188 def_bool n
56 1189
57 # For now, use generic checksum functions <<
58 #These can be reimplemented in assembly later <<
59 config GENERIC_CSUM 1190 config GENERIC_CSUM
60 def_bool y !! 1191 def_bool CPU_NO_LOAD_STORE_LR
61 1192
62 config STACKTRACE_SUPPORT !! 1193 config GENERIC_ISA_DMA
>> 1194 bool
>> 1195 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1196 select ISA_DMA_API
>> 1197
>> 1198 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1199 bool
>> 1200 select GENERIC_ISA_DMA
>> 1201
>> 1202 config HAVE_PLAT_DELAY
>> 1203 bool
>> 1204
>> 1205 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1206 bool
>> 1207
>> 1208 config HAVE_PLAT_MEMCPY
>> 1209 bool
>> 1210
>> 1211 config ISA_DMA_API
>> 1212 bool
>> 1213
>> 1214 config SYS_SUPPORTS_RELOCATABLE
>> 1215 bool
>> 1216 help
>> 1217 Selected if the platform supports relocating the kernel.
>> 1218 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1219 to allow access to command line and entropy sources.
>> 1220
>> 1221 config MIPS_CBPF_JIT
63 def_bool y 1222 def_bool y
>> 1223 depends on BPF_JIT && HAVE_CBPF_JIT
64 1224
65 config LOCKDEP_SUPPORT !! 1225 config MIPS_EBPF_JIT
66 def_bool y !! 1226 def_bool y
>> 1227 depends on BPF_JIT && HAVE_EBPF_JIT
67 1228
68 menu "Processor type and features" <<
69 1229
>> 1230 #
>> 1231 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1232 # answer,so we try hard to limit the available choices. Also the use of a
>> 1233 # choice statement should be more obvious to the user.
>> 1234 #
70 choice 1235 choice
71 prompt "Subarchitecture" !! 1236 prompt "Endianness selection"
72 default OR1K_1200 <<
73 <<
74 config OR1K_1200 <<
75 bool "OR1200" <<
76 help 1237 help
77 Generic OpenRISC 1200 architecture !! 1238 Some MIPS machines can be configured for either little or big endian
>> 1239 byte order. These modes require different kernels and a different
>> 1240 Linux distribution. In general there is one preferred byteorder for a
>> 1241 particular system but some systems are just as commonly used in the
>> 1242 one or the other endianness.
>> 1243
>> 1244 config CPU_BIG_ENDIAN
>> 1245 bool "Big endian"
>> 1246 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1247
>> 1248 config CPU_LITTLE_ENDIAN
>> 1249 bool "Little endian"
>> 1250 depends on SYS_SUPPORTS_LITTLE_ENDIAN
78 1251
79 endchoice 1252 endchoice
80 1253
81 config DCACHE_WRITETHROUGH !! 1254 config EXPORT_UASM
82 bool "Have write through data caches" !! 1255 bool
>> 1256
>> 1257 config SYS_SUPPORTS_APM_EMULATION
>> 1258 bool
>> 1259
>> 1260 config SYS_SUPPORTS_BIG_ENDIAN
>> 1261 bool
>> 1262
>> 1263 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1264 bool
>> 1265
>> 1266 config MIPS_HUGE_TLB_SUPPORT
>> 1267 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1268
>> 1269 config IRQ_MSP_SLP
>> 1270 bool
>> 1271
>> 1272 config IRQ_MSP_CIC
>> 1273 bool
>> 1274
>> 1275 config IRQ_TXX9
>> 1276 bool
>> 1277
>> 1278 config IRQ_GT641XX
>> 1279 bool
>> 1280
>> 1281 config PCI_GT64XXX_PCI0
>> 1282 bool
>> 1283
>> 1284 config PCI_XTALK_BRIDGE
>> 1285 bool
>> 1286
>> 1287 config NO_EXCEPT_FILL
>> 1288 bool
>> 1289
>> 1290 config MIPS_SPRAM
>> 1291 bool
>> 1292
>> 1293 config SWAP_IO_SPACE
>> 1294 bool
>> 1295
>> 1296 config SGI_HAS_INDYDOG
>> 1297 bool
>> 1298
>> 1299 config SGI_HAS_HAL2
>> 1300 bool
>> 1301
>> 1302 config SGI_HAS_SEEQ
>> 1303 bool
>> 1304
>> 1305 config SGI_HAS_WD93
>> 1306 bool
>> 1307
>> 1308 config SGI_HAS_ZILOG
>> 1309 bool
>> 1310
>> 1311 config SGI_HAS_I8042
>> 1312 bool
>> 1313
>> 1314 config DEFAULT_SGI_PARTITION
>> 1315 bool
>> 1316
>> 1317 config FW_ARC32
>> 1318 bool
>> 1319
>> 1320 config FW_SNIPROM
>> 1321 bool
>> 1322
>> 1323 config BOOT_ELF32
>> 1324 bool
>> 1325
>> 1326 config MIPS_L1_CACHE_SHIFT_4
>> 1327 bool
>> 1328
>> 1329 config MIPS_L1_CACHE_SHIFT_5
>> 1330 bool
>> 1331
>> 1332 config MIPS_L1_CACHE_SHIFT_6
>> 1333 bool
>> 1334
>> 1335 config MIPS_L1_CACHE_SHIFT_7
>> 1336 bool
>> 1337
>> 1338 config MIPS_L1_CACHE_SHIFT
>> 1339 int
>> 1340 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1341 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1342 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1343 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1344 default "5"
>> 1345
>> 1346 config ARC_CMDLINE_ONLY
>> 1347 bool
>> 1348
>> 1349 config ARC_CONSOLE
>> 1350 bool "ARC console support"
>> 1351 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1352
>> 1353 config ARC_MEMORY
>> 1354 bool
>> 1355
>> 1356 config ARC_PROMLIB
>> 1357 bool
>> 1358
>> 1359 config FW_ARC64
>> 1360 bool
>> 1361
>> 1362 config BOOT_ELF64
>> 1363 bool
>> 1364
>> 1365 menu "CPU selection"
>> 1366
>> 1367 choice
>> 1368 prompt "CPU type"
>> 1369 default CPU_R4X00
>> 1370
>> 1371 config CPU_LOONGSON64
>> 1372 bool "Loongson 64-bit CPU"
>> 1373 depends on SYS_HAS_CPU_LOONGSON64
>> 1374 select ARCH_HAS_PHYS_TO_DMA
>> 1375 select CPU_MIPSR2
>> 1376 select CPU_HAS_PREFETCH
>> 1377 select CPU_SUPPORTS_64BIT_KERNEL
>> 1378 select CPU_SUPPORTS_HIGHMEM
>> 1379 select CPU_SUPPORTS_HUGEPAGES
>> 1380 select CPU_SUPPORTS_MSA
>> 1381 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1382 select CPU_MIPSR2_IRQ_VI
>> 1383 select DMA_NONCOHERENT
>> 1384 select WEAK_ORDERING
>> 1385 select WEAK_REORDERING_BEYOND_LLSC
>> 1386 select MIPS_ASID_BITS_VARIABLE
>> 1387 select MIPS_PGD_C0_CONTEXT
>> 1388 select MIPS_L1_CACHE_SHIFT_6
>> 1389 select MIPS_FP_SUPPORT
>> 1390 select GPIOLIB
>> 1391 select SWIOTLB
>> 1392 select HAVE_KVM
>> 1393 help
>> 1394 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1395 cores implements the MIPS64R2 instruction set with many extensions,
>> 1396 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1397 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1398 Loongson-2E/2F is not covered here and will be removed in future.
>> 1399
>> 1400 config LOONGSON3_ENHANCEMENT
>> 1401 bool "New Loongson-3 CPU Enhancements"
83 default n 1402 default n
>> 1403 depends on CPU_LOONGSON64
84 help 1404 help
85 Select this if your implementation f !! 1405 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
86 Selecting 'N' here will allow the ke !! 1406 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
87 caches at relevant times. Most OpenR !! 1407 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
88 through data caches. !! 1408 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1409 Fast TLB refill support, etc.
>> 1410
>> 1411 This option enable those enhancements which are not probed at run
>> 1412 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1413 please say 'N' here. If you want a high-performance kernel to run on
>> 1414 new Loongson-3 machines only, please say 'Y' here.
89 1415
90 If unsure say N here !! 1416 config CPU_LOONGSON3_WORKAROUNDS
>> 1417 bool "Old Loongson-3 LLSC Workarounds"
>> 1418 default y if SMP
>> 1419 depends on CPU_LOONGSON64
>> 1420 help
>> 1421 Loongson-3 processors have the llsc issues which require workarounds.
>> 1422 Without workarounds the system may hang unexpectedly.
91 1423
92 config OPENRISC_BUILTIN_DTB !! 1424 Newer Loongson-3 will fix these issues and no workarounds are needed.
93 string "Builtin DTB" !! 1425 The workarounds have no significant side effect on them but may
94 default "" !! 1426 decrease the performance of the system so this option should be
>> 1427 disabled unless the kernel is intended to be run on old systems.
95 1428
96 menu "Class II Instructions" !! 1429 If unsure, please say Y.
97 1430
98 config OPENRISC_HAVE_INST_FF1 !! 1431 config CPU_LOONGSON3_CPUCFG_EMULATION
99 bool "Have instruction l.ff1" !! 1432 bool "Emulate the CPUCFG instruction on older Loongson cores"
100 default y 1433 default y
>> 1434 depends on CPU_LOONGSON64
101 help 1435 help
102 Select this if your implementation h !! 1436 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1437 userland to query CPU capabilities, much like CPUID on x86. This
>> 1438 option provides emulation of the instruction on older Loongson
>> 1439 cores, back to Loongson-3A1000.
>> 1440
>> 1441 If unsure, please say Y.
>> 1442
>> 1443 config CPU_LOONGSON2E
>> 1444 bool "Loongson 2E"
>> 1445 depends on SYS_HAS_CPU_LOONGSON2E
>> 1446 select CPU_LOONGSON2EF
>> 1447 help
>> 1448 The Loongson 2E processor implements the MIPS III instruction set
>> 1449 with many extensions.
>> 1450
>> 1451 It has an internal FPGA northbridge, which is compatible to
>> 1452 bonito64.
>> 1453
>> 1454 config CPU_LOONGSON2F
>> 1455 bool "Loongson 2F"
>> 1456 depends on SYS_HAS_CPU_LOONGSON2F
>> 1457 select CPU_LOONGSON2EF
>> 1458 select GPIOLIB
>> 1459 help
>> 1460 The Loongson 2F processor implements the MIPS III instruction set
>> 1461 with many extensions.
103 1462
104 config OPENRISC_HAVE_INST_FL1 !! 1463 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
105 bool "Have instruction l.fl1" !! 1464 have a similar programming interface with FPGA northbridge used in
>> 1465 Loongson2E.
>> 1466
>> 1467 config CPU_LOONGSON1B
>> 1468 bool "Loongson 1B"
>> 1469 depends on SYS_HAS_CPU_LOONGSON1B
>> 1470 select CPU_LOONGSON32
>> 1471 select LEDS_GPIO_REGISTER
>> 1472 help
>> 1473 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1474 Release 1 instruction set and part of the MIPS32 Release 2
>> 1475 instruction set.
>> 1476
>> 1477 config CPU_LOONGSON1C
>> 1478 bool "Loongson 1C"
>> 1479 depends on SYS_HAS_CPU_LOONGSON1C
>> 1480 select CPU_LOONGSON32
>> 1481 select LEDS_GPIO_REGISTER
>> 1482 help
>> 1483 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1484 Release 1 instruction set and part of the MIPS32 Release 2
>> 1485 instruction set.
>> 1486
>> 1487 config CPU_MIPS32_R1
>> 1488 bool "MIPS32 Release 1"
>> 1489 depends on SYS_HAS_CPU_MIPS32_R1
>> 1490 select CPU_HAS_PREFETCH
>> 1491 select CPU_SUPPORTS_32BIT_KERNEL
>> 1492 select CPU_SUPPORTS_HIGHMEM
>> 1493 help
>> 1494 Choose this option to build a kernel for release 1 or later of the
>> 1495 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1496 MIPS processor are based on a MIPS32 processor. If you know the
>> 1497 specific type of processor in your system, choose those that one
>> 1498 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1499 Release 2 of the MIPS32 architecture is available since several
>> 1500 years so chances are you even have a MIPS32 Release 2 processor
>> 1501 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1502 performance.
>> 1503
>> 1504 config CPU_MIPS32_R2
>> 1505 bool "MIPS32 Release 2"
>> 1506 depends on SYS_HAS_CPU_MIPS32_R2
>> 1507 select CPU_HAS_PREFETCH
>> 1508 select CPU_SUPPORTS_32BIT_KERNEL
>> 1509 select CPU_SUPPORTS_HIGHMEM
>> 1510 select CPU_SUPPORTS_MSA
>> 1511 select HAVE_KVM
>> 1512 help
>> 1513 Choose this option to build a kernel for release 2 or later of the
>> 1514 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1515 MIPS processor are based on a MIPS32 processor. If you know the
>> 1516 specific type of processor in your system, choose those that one
>> 1517 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1518
>> 1519 config CPU_MIPS32_R5
>> 1520 bool "MIPS32 Release 5"
>> 1521 depends on SYS_HAS_CPU_MIPS32_R5
>> 1522 select CPU_HAS_PREFETCH
>> 1523 select CPU_SUPPORTS_32BIT_KERNEL
>> 1524 select CPU_SUPPORTS_HIGHMEM
>> 1525 select CPU_SUPPORTS_MSA
>> 1526 select HAVE_KVM
>> 1527 select MIPS_O32_FP64_SUPPORT
>> 1528 help
>> 1529 Choose this option to build a kernel for release 5 or later of the
>> 1530 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1531 family, are based on a MIPS32r5 processor. If you own an older
>> 1532 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1533
>> 1534 config CPU_MIPS32_R6
>> 1535 bool "MIPS32 Release 6"
>> 1536 depends on SYS_HAS_CPU_MIPS32_R6
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_NO_LOAD_STORE_LR
>> 1539 select CPU_SUPPORTS_32BIT_KERNEL
>> 1540 select CPU_SUPPORTS_HIGHMEM
>> 1541 select CPU_SUPPORTS_MSA
>> 1542 select HAVE_KVM
>> 1543 select MIPS_O32_FP64_SUPPORT
>> 1544 help
>> 1545 Choose this option to build a kernel for release 6 or later of the
>> 1546 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1547 family, are based on a MIPS32r6 processor. If you own an older
>> 1548 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1549
>> 1550 config CPU_MIPS64_R1
>> 1551 bool "MIPS64 Release 1"
>> 1552 depends on SYS_HAS_CPU_MIPS64_R1
>> 1553 select CPU_HAS_PREFETCH
>> 1554 select CPU_SUPPORTS_32BIT_KERNEL
>> 1555 select CPU_SUPPORTS_64BIT_KERNEL
>> 1556 select CPU_SUPPORTS_HIGHMEM
>> 1557 select CPU_SUPPORTS_HUGEPAGES
>> 1558 help
>> 1559 Choose this option to build a kernel for release 1 or later of the
>> 1560 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1561 MIPS processor are based on a MIPS64 processor. If you know the
>> 1562 specific type of processor in your system, choose those that one
>> 1563 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1564 Release 2 of the MIPS64 architecture is available since several
>> 1565 years so chances are you even have a MIPS64 Release 2 processor
>> 1566 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1567 performance.
>> 1568
>> 1569 config CPU_MIPS64_R2
>> 1570 bool "MIPS64 Release 2"
>> 1571 depends on SYS_HAS_CPU_MIPS64_R2
>> 1572 select CPU_HAS_PREFETCH
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_64BIT_KERNEL
>> 1575 select CPU_SUPPORTS_HIGHMEM
>> 1576 select CPU_SUPPORTS_HUGEPAGES
>> 1577 select CPU_SUPPORTS_MSA
>> 1578 select HAVE_KVM
>> 1579 help
>> 1580 Choose this option to build a kernel for release 2 or later of the
>> 1581 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1582 MIPS processor are based on a MIPS64 processor. If you know the
>> 1583 specific type of processor in your system, choose those that one
>> 1584 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1585
>> 1586 config CPU_MIPS64_R5
>> 1587 bool "MIPS64 Release 5"
>> 1588 depends on SYS_HAS_CPU_MIPS64_R5
>> 1589 select CPU_HAS_PREFETCH
>> 1590 select CPU_SUPPORTS_32BIT_KERNEL
>> 1591 select CPU_SUPPORTS_64BIT_KERNEL
>> 1592 select CPU_SUPPORTS_HIGHMEM
>> 1593 select CPU_SUPPORTS_HUGEPAGES
>> 1594 select CPU_SUPPORTS_MSA
>> 1595 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1596 select HAVE_KVM
>> 1597 help
>> 1598 Choose this option to build a kernel for release 5 or later of the
>> 1599 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1600 release partly implementing release 6 features. Though there is no
>> 1601 any hardware known to be based on this release.
>> 1602
>> 1603 config CPU_MIPS64_R6
>> 1604 bool "MIPS64 Release 6"
>> 1605 depends on SYS_HAS_CPU_MIPS64_R6
>> 1606 select CPU_HAS_PREFETCH
>> 1607 select CPU_NO_LOAD_STORE_LR
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HIGHMEM
>> 1611 select CPU_SUPPORTS_HUGEPAGES
>> 1612 select CPU_SUPPORTS_MSA
>> 1613 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1614 select HAVE_KVM
>> 1615 help
>> 1616 Choose this option to build a kernel for release 6 or later of the
>> 1617 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1618 family, are based on a MIPS64r6 processor. If you own an older
>> 1619 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1620
>> 1621 config CPU_P5600
>> 1622 bool "MIPS Warrior P5600"
>> 1623 depends on SYS_HAS_CPU_P5600
>> 1624 select CPU_HAS_PREFETCH
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_HIGHMEM
>> 1627 select CPU_SUPPORTS_MSA
>> 1628 select CPU_SUPPORTS_CPUFREQ
>> 1629 select CPU_MIPSR2_IRQ_VI
>> 1630 select CPU_MIPSR2_IRQ_EI
>> 1631 select HAVE_KVM
>> 1632 select MIPS_O32_FP64_SUPPORT
>> 1633 help
>> 1634 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1635 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1636 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1637 level features like up to six P5600 calculation cores, CM2 with L2
>> 1638 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1639 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1640 eJTAG and PDtrace.
>> 1641
>> 1642 config CPU_R3000
>> 1643 bool "R3000"
>> 1644 depends on SYS_HAS_CPU_R3000
>> 1645 select CPU_HAS_WB
>> 1646 select CPU_R3K_TLB
>> 1647 select CPU_SUPPORTS_32BIT_KERNEL
>> 1648 select CPU_SUPPORTS_HIGHMEM
>> 1649 help
>> 1650 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1651 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1652 *not* work on R4000 machines and vice versa. However, since most
>> 1653 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1654 might be a safe bet. If the resulting kernel does not work,
>> 1655 try to recompile with R3000.
>> 1656
>> 1657 config CPU_TX39XX
>> 1658 bool "R39XX"
>> 1659 depends on SYS_HAS_CPU_TX39XX
>> 1660 select CPU_SUPPORTS_32BIT_KERNEL
>> 1661 select CPU_R3K_TLB
>> 1662
>> 1663 config CPU_VR41XX
>> 1664 bool "R41xx"
>> 1665 depends on SYS_HAS_CPU_VR41XX
>> 1666 select CPU_SUPPORTS_32BIT_KERNEL
>> 1667 select CPU_SUPPORTS_64BIT_KERNEL
>> 1668 help
>> 1669 The options selects support for the NEC VR4100 series of processors.
>> 1670 Only choose this option if you have one of these processors as a
>> 1671 kernel built with this option will not run on any other type of
>> 1672 processor or vice versa.
>> 1673
>> 1674 config CPU_R4300
>> 1675 bool "R4300"
>> 1676 depends on SYS_HAS_CPU_R4300
>> 1677 select CPU_SUPPORTS_32BIT_KERNEL
>> 1678 select CPU_SUPPORTS_64BIT_KERNEL
>> 1679 select CPU_HAS_LOAD_STORE_LR
>> 1680 help
>> 1681 MIPS Technologies R4300-series processors.
>> 1682
>> 1683 config CPU_R4X00
>> 1684 bool "R4x00"
>> 1685 depends on SYS_HAS_CPU_R4X00
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select CPU_SUPPORTS_64BIT_KERNEL
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689 help
>> 1690 MIPS Technologies R4000-series processors other than 4300, including
>> 1691 the R4000, R4400, R4600, and 4700.
>> 1692
>> 1693 config CPU_TX49XX
>> 1694 bool "R49XX"
>> 1695 depends on SYS_HAS_CPU_TX49XX
>> 1696 select CPU_HAS_PREFETCH
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select CPU_SUPPORTS_HUGEPAGES
>> 1700
>> 1701 config CPU_R5000
>> 1702 bool "R5000"
>> 1703 depends on SYS_HAS_CPU_R5000
>> 1704 select CPU_SUPPORTS_32BIT_KERNEL
>> 1705 select CPU_SUPPORTS_64BIT_KERNEL
>> 1706 select CPU_SUPPORTS_HUGEPAGES
>> 1707 help
>> 1708 MIPS Technologies R5000-series processors other than the Nevada.
>> 1709
>> 1710 config CPU_R5500
>> 1711 bool "R5500"
>> 1712 depends on SYS_HAS_CPU_R5500
>> 1713 select CPU_SUPPORTS_32BIT_KERNEL
>> 1714 select CPU_SUPPORTS_64BIT_KERNEL
>> 1715 select CPU_SUPPORTS_HUGEPAGES
>> 1716 help
>> 1717 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1718 instruction set.
>> 1719
>> 1720 config CPU_NEVADA
>> 1721 bool "RM52xx"
>> 1722 depends on SYS_HAS_CPU_NEVADA
>> 1723 select CPU_SUPPORTS_32BIT_KERNEL
>> 1724 select CPU_SUPPORTS_64BIT_KERNEL
>> 1725 select CPU_SUPPORTS_HUGEPAGES
>> 1726 help
>> 1727 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1728
>> 1729 config CPU_R10000
>> 1730 bool "R10000"
>> 1731 depends on SYS_HAS_CPU_R10000
>> 1732 select CPU_HAS_PREFETCH
>> 1733 select CPU_SUPPORTS_32BIT_KERNEL
>> 1734 select CPU_SUPPORTS_64BIT_KERNEL
>> 1735 select CPU_SUPPORTS_HIGHMEM
>> 1736 select CPU_SUPPORTS_HUGEPAGES
>> 1737 help
>> 1738 MIPS Technologies R10000-series processors.
>> 1739
>> 1740 config CPU_RM7000
>> 1741 bool "RM7000"
>> 1742 depends on SYS_HAS_CPU_RM7000
>> 1743 select CPU_HAS_PREFETCH
>> 1744 select CPU_SUPPORTS_32BIT_KERNEL
>> 1745 select CPU_SUPPORTS_64BIT_KERNEL
>> 1746 select CPU_SUPPORTS_HIGHMEM
>> 1747 select CPU_SUPPORTS_HUGEPAGES
>> 1748
>> 1749 config CPU_SB1
>> 1750 bool "SB1"
>> 1751 depends on SYS_HAS_CPU_SB1
>> 1752 select CPU_SUPPORTS_32BIT_KERNEL
>> 1753 select CPU_SUPPORTS_64BIT_KERNEL
>> 1754 select CPU_SUPPORTS_HIGHMEM
>> 1755 select CPU_SUPPORTS_HUGEPAGES
>> 1756 select WEAK_ORDERING
>> 1757
>> 1758 config CPU_CAVIUM_OCTEON
>> 1759 bool "Cavium Octeon processor"
>> 1760 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1761 select CPU_HAS_PREFETCH
>> 1762 select CPU_SUPPORTS_64BIT_KERNEL
>> 1763 select WEAK_ORDERING
>> 1764 select CPU_SUPPORTS_HIGHMEM
>> 1765 select CPU_SUPPORTS_HUGEPAGES
>> 1766 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1767 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1768 select MIPS_L1_CACHE_SHIFT_7
>> 1769 select HAVE_KVM
>> 1770 help
>> 1771 The Cavium Octeon processor is a highly integrated chip containing
>> 1772 many ethernet hardware widgets for networking tasks. The processor
>> 1773 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1774 Full details can be found at http://www.caviumnetworks.com.
>> 1775
>> 1776 config CPU_BMIPS
>> 1777 bool "Broadcom BMIPS"
>> 1778 depends on SYS_HAS_CPU_BMIPS
>> 1779 select CPU_MIPS32
>> 1780 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1781 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1782 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1783 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1784 select CPU_SUPPORTS_32BIT_KERNEL
>> 1785 select DMA_NONCOHERENT
>> 1786 select IRQ_MIPS_CPU
>> 1787 select SWAP_IO_SPACE
>> 1788 select WEAK_ORDERING
>> 1789 select CPU_SUPPORTS_HIGHMEM
>> 1790 select CPU_HAS_PREFETCH
>> 1791 select CPU_SUPPORTS_CPUFREQ
>> 1792 select MIPS_EXTERNAL_TIMER
>> 1793 help
>> 1794 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1795
>> 1796 config CPU_XLR
>> 1797 bool "Netlogic XLR SoC"
>> 1798 depends on SYS_HAS_CPU_XLR
>> 1799 select CPU_SUPPORTS_32BIT_KERNEL
>> 1800 select CPU_SUPPORTS_64BIT_KERNEL
>> 1801 select CPU_SUPPORTS_HIGHMEM
>> 1802 select CPU_SUPPORTS_HUGEPAGES
>> 1803 select WEAK_ORDERING
>> 1804 select WEAK_REORDERING_BEYOND_LLSC
>> 1805 help
>> 1806 Netlogic Microsystems XLR/XLS processors.
>> 1807
>> 1808 config CPU_XLP
>> 1809 bool "Netlogic XLP SoC"
>> 1810 depends on SYS_HAS_CPU_XLP
>> 1811 select CPU_SUPPORTS_32BIT_KERNEL
>> 1812 select CPU_SUPPORTS_64BIT_KERNEL
>> 1813 select CPU_SUPPORTS_HIGHMEM
>> 1814 select WEAK_ORDERING
>> 1815 select WEAK_REORDERING_BEYOND_LLSC
>> 1816 select CPU_HAS_PREFETCH
>> 1817 select CPU_MIPSR2
>> 1818 select CPU_SUPPORTS_HUGEPAGES
>> 1819 select MIPS_ASID_BITS_VARIABLE
>> 1820 help
>> 1821 Netlogic Microsystems XLP processors.
>> 1822 endchoice
>> 1823
>> 1824 config CPU_MIPS32_3_5_FEATURES
>> 1825 bool "MIPS32 Release 3.5 Features"
>> 1826 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1827 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1828 CPU_P5600
>> 1829 help
>> 1830 Choose this option to build a kernel for release 2 or later of the
>> 1831 MIPS32 architecture including features from the 3.5 release such as
>> 1832 support for Enhanced Virtual Addressing (EVA).
>> 1833
>> 1834 config CPU_MIPS32_3_5_EVA
>> 1835 bool "Enhanced Virtual Addressing (EVA)"
>> 1836 depends on CPU_MIPS32_3_5_FEATURES
>> 1837 select EVA
106 default y 1838 default y
107 help 1839 help
108 Select this if your implementation h !! 1840 Choose this option if you want to enable the Enhanced Virtual
>> 1841 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1842 One of its primary benefits is an increase in the maximum size
>> 1843 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1844
>> 1845 config CPU_MIPS32_R5_FEATURES
>> 1846 bool "MIPS32 Release 5 Features"
>> 1847 depends on SYS_HAS_CPU_MIPS32_R5
>> 1848 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1849 help
>> 1850 Choose this option to build a kernel for release 2 or later of the
>> 1851 MIPS32 architecture including features from release 5 such as
>> 1852 support for Extended Physical Addressing (XPA).
>> 1853
>> 1854 config CPU_MIPS32_R5_XPA
>> 1855 bool "Extended Physical Addressing (XPA)"
>> 1856 depends on CPU_MIPS32_R5_FEATURES
>> 1857 depends on !EVA
>> 1858 depends on !PAGE_SIZE_4KB
>> 1859 depends on SYS_SUPPORTS_HIGHMEM
>> 1860 select XPA
>> 1861 select HIGHMEM
>> 1862 select PHYS_ADDR_T_64BIT
>> 1863 default n
>> 1864 help
>> 1865 Choose this option if you want to enable the Extended Physical
>> 1866 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1867 benefit is to increase physical addressing equal to or greater
>> 1868 than 40 bits. Note that this has the side effect of turning on
>> 1869 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1870 If unsure, say 'N' here.
>> 1871
>> 1872 if CPU_LOONGSON2F
>> 1873 config CPU_NOP_WORKAROUNDS
>> 1874 bool
>> 1875
>> 1876 config CPU_JUMP_WORKAROUNDS
>> 1877 bool
109 1878
110 config OPENRISC_HAVE_INST_MUL !! 1879 config CPU_LOONGSON2F_WORKAROUNDS
111 bool "Have instruction l.mul for hardw !! 1880 bool "Loongson 2F Workarounds"
112 default y 1881 default y
>> 1882 select CPU_NOP_WORKAROUNDS
>> 1883 select CPU_JUMP_WORKAROUNDS
>> 1884 help
>> 1885 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1886 require workarounds. Without workarounds the system may hang
>> 1887 unexpectedly. For more information please refer to the gas
>> 1888 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1889
>> 1890 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1891 are needed. The workarounds have no significant side effect on them
>> 1892 but may decrease the performance of the system so this option should
>> 1893 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1894 systems.
>> 1895
>> 1896 If unsure, please say Y.
>> 1897 endif # CPU_LOONGSON2F
>> 1898
>> 1899 config SYS_SUPPORTS_ZBOOT
>> 1900 bool
>> 1901 select HAVE_KERNEL_GZIP
>> 1902 select HAVE_KERNEL_BZIP2
>> 1903 select HAVE_KERNEL_LZ4
>> 1904 select HAVE_KERNEL_LZMA
>> 1905 select HAVE_KERNEL_LZO
>> 1906 select HAVE_KERNEL_XZ
>> 1907 select HAVE_KERNEL_ZSTD
>> 1908
>> 1909 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1910 bool
>> 1911 select SYS_SUPPORTS_ZBOOT
>> 1912
>> 1913 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1914 bool
>> 1915 select SYS_SUPPORTS_ZBOOT
>> 1916
>> 1917 config CPU_LOONGSON2EF
>> 1918 bool
>> 1919 select CPU_SUPPORTS_32BIT_KERNEL
>> 1920 select CPU_SUPPORTS_64BIT_KERNEL
>> 1921 select CPU_SUPPORTS_HIGHMEM
>> 1922 select CPU_SUPPORTS_HUGEPAGES
>> 1923 select ARCH_HAS_PHYS_TO_DMA
>> 1924
>> 1925 config CPU_LOONGSON32
>> 1926 bool
>> 1927 select CPU_MIPS32
>> 1928 select CPU_MIPSR2
>> 1929 select CPU_HAS_PREFETCH
>> 1930 select CPU_SUPPORTS_32BIT_KERNEL
>> 1931 select CPU_SUPPORTS_HIGHMEM
>> 1932 select CPU_SUPPORTS_CPUFREQ
>> 1933
>> 1934 config CPU_BMIPS32_3300
>> 1935 select SMP_UP if SMP
>> 1936 bool
>> 1937
>> 1938 config CPU_BMIPS4350
>> 1939 bool
>> 1940 select SYS_SUPPORTS_SMP
>> 1941 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1942
>> 1943 config CPU_BMIPS4380
>> 1944 bool
>> 1945 select MIPS_L1_CACHE_SHIFT_6
>> 1946 select SYS_SUPPORTS_SMP
>> 1947 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1948 select CPU_HAS_RIXI
>> 1949
>> 1950 config CPU_BMIPS5000
>> 1951 bool
>> 1952 select MIPS_CPU_SCACHE
>> 1953 select MIPS_L1_CACHE_SHIFT_7
>> 1954 select SYS_SUPPORTS_SMP
>> 1955 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1956 select CPU_HAS_RIXI
>> 1957
>> 1958 config SYS_HAS_CPU_LOONGSON64
>> 1959 bool
>> 1960 select CPU_SUPPORTS_CPUFREQ
>> 1961 select CPU_HAS_RIXI
>> 1962
>> 1963 config SYS_HAS_CPU_LOONGSON2E
>> 1964 bool
>> 1965
>> 1966 config SYS_HAS_CPU_LOONGSON2F
>> 1967 bool
>> 1968 select CPU_SUPPORTS_CPUFREQ
>> 1969 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1970
>> 1971 config SYS_HAS_CPU_LOONGSON1B
>> 1972 bool
>> 1973
>> 1974 config SYS_HAS_CPU_LOONGSON1C
>> 1975 bool
>> 1976
>> 1977 config SYS_HAS_CPU_MIPS32_R1
>> 1978 bool
>> 1979
>> 1980 config SYS_HAS_CPU_MIPS32_R2
>> 1981 bool
>> 1982
>> 1983 config SYS_HAS_CPU_MIPS32_R3_5
>> 1984 bool
>> 1985
>> 1986 config SYS_HAS_CPU_MIPS32_R5
>> 1987 bool
>> 1988 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1989
>> 1990 config SYS_HAS_CPU_MIPS32_R6
>> 1991 bool
>> 1992 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1993
>> 1994 config SYS_HAS_CPU_MIPS64_R1
>> 1995 bool
>> 1996
>> 1997 config SYS_HAS_CPU_MIPS64_R2
>> 1998 bool
>> 1999
>> 2000 config SYS_HAS_CPU_MIPS64_R5
>> 2001 bool
>> 2002 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2003
>> 2004 config SYS_HAS_CPU_MIPS64_R6
>> 2005 bool
>> 2006 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2007
>> 2008 config SYS_HAS_CPU_P5600
>> 2009 bool
>> 2010 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2011
>> 2012 config SYS_HAS_CPU_R3000
>> 2013 bool
>> 2014
>> 2015 config SYS_HAS_CPU_TX39XX
>> 2016 bool
>> 2017
>> 2018 config SYS_HAS_CPU_VR41XX
>> 2019 bool
>> 2020
>> 2021 config SYS_HAS_CPU_R4300
>> 2022 bool
>> 2023
>> 2024 config SYS_HAS_CPU_R4X00
>> 2025 bool
>> 2026
>> 2027 config SYS_HAS_CPU_TX49XX
>> 2028 bool
>> 2029
>> 2030 config SYS_HAS_CPU_R5000
>> 2031 bool
>> 2032
>> 2033 config SYS_HAS_CPU_R5500
>> 2034 bool
>> 2035
>> 2036 config SYS_HAS_CPU_NEVADA
>> 2037 bool
>> 2038
>> 2039 config SYS_HAS_CPU_R10000
>> 2040 bool
>> 2041 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2042
>> 2043 config SYS_HAS_CPU_RM7000
>> 2044 bool
>> 2045
>> 2046 config SYS_HAS_CPU_SB1
>> 2047 bool
>> 2048
>> 2049 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2050 bool
>> 2051
>> 2052 config SYS_HAS_CPU_BMIPS
>> 2053 bool
>> 2054
>> 2055 config SYS_HAS_CPU_BMIPS32_3300
>> 2056 bool
>> 2057 select SYS_HAS_CPU_BMIPS
>> 2058
>> 2059 config SYS_HAS_CPU_BMIPS4350
>> 2060 bool
>> 2061 select SYS_HAS_CPU_BMIPS
>> 2062
>> 2063 config SYS_HAS_CPU_BMIPS4380
>> 2064 bool
>> 2065 select SYS_HAS_CPU_BMIPS
>> 2066
>> 2067 config SYS_HAS_CPU_BMIPS5000
>> 2068 bool
>> 2069 select SYS_HAS_CPU_BMIPS
>> 2070 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2071
>> 2072 config SYS_HAS_CPU_XLR
>> 2073 bool
>> 2074
>> 2075 config SYS_HAS_CPU_XLP
>> 2076 bool
>> 2077
>> 2078 #
>> 2079 # CPU may reorder R->R, R->W, W->R, W->W
>> 2080 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2081 #
>> 2082 config WEAK_ORDERING
>> 2083 bool
>> 2084
>> 2085 #
>> 2086 # CPU may reorder reads and writes beyond LL/SC
>> 2087 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2088 #
>> 2089 config WEAK_REORDERING_BEYOND_LLSC
>> 2090 bool
>> 2091 endmenu
>> 2092
>> 2093 #
>> 2094 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2095 #
>> 2096 config CPU_MIPS32
>> 2097 bool
>> 2098 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2099 CPU_MIPS32_R6 || CPU_P5600
>> 2100
>> 2101 config CPU_MIPS64
>> 2102 bool
>> 2103 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2104 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 2105
>> 2106 #
>> 2107 # These indicate the revision of the architecture
>> 2108 #
>> 2109 config CPU_MIPSR1
>> 2110 bool
>> 2111 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2112
>> 2113 config CPU_MIPSR2
>> 2114 bool
>> 2115 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2116 select CPU_HAS_RIXI
>> 2117 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2118 select MIPS_SPRAM
>> 2119
>> 2120 config CPU_MIPSR5
>> 2121 bool
>> 2122 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2123 select CPU_HAS_RIXI
>> 2124 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2125 select MIPS_SPRAM
>> 2126
>> 2127 config CPU_MIPSR6
>> 2128 bool
>> 2129 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2130 select CPU_HAS_RIXI
>> 2131 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2132 select HAVE_ARCH_BITREVERSE
>> 2133 select MIPS_ASID_BITS_VARIABLE
>> 2134 select MIPS_CRC_SUPPORT
>> 2135 select MIPS_SPRAM
>> 2136
>> 2137 config TARGET_ISA_REV
>> 2138 int
>> 2139 default 1 if CPU_MIPSR1
>> 2140 default 2 if CPU_MIPSR2
>> 2141 default 5 if CPU_MIPSR5
>> 2142 default 6 if CPU_MIPSR6
>> 2143 default 0
113 help 2144 help
114 Select this if your implementation h !! 2145 Reflects the ISA revision being targeted by the kernel build. This
>> 2146 is effectively the Kconfig equivalent of MIPS_ISA_REV.
115 2147
116 config OPENRISC_HAVE_INST_DIV !! 2148 config EVA
117 bool "Have instruction l.div for hardw !! 2149 bool
>> 2150
>> 2151 config XPA
>> 2152 bool
>> 2153
>> 2154 config SYS_SUPPORTS_32BIT_KERNEL
>> 2155 bool
>> 2156 config SYS_SUPPORTS_64BIT_KERNEL
>> 2157 bool
>> 2158 config CPU_SUPPORTS_32BIT_KERNEL
>> 2159 bool
>> 2160 config CPU_SUPPORTS_64BIT_KERNEL
>> 2161 bool
>> 2162 config CPU_SUPPORTS_CPUFREQ
>> 2163 bool
>> 2164 config CPU_SUPPORTS_ADDRWINCFG
>> 2165 bool
>> 2166 config CPU_SUPPORTS_HUGEPAGES
>> 2167 bool
>> 2168 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2169 config MIPS_PGD_C0_CONTEXT
>> 2170 bool
>> 2171 depends on 64BIT
>> 2172 default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2173
>> 2174 #
>> 2175 # Set to y for ptrace access to watch registers.
>> 2176 #
>> 2177 config HARDWARE_WATCHPOINTS
>> 2178 bool
>> 2179 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2180
>> 2181 menu "Kernel type"
>> 2182
>> 2183 choice
>> 2184 prompt "Kernel code model"
>> 2185 help
>> 2186 You should only select this option if you have a workload that
>> 2187 actually benefits from 64-bit processing or if your machine has
>> 2188 large memory. You will only be presented a single option in this
>> 2189 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2190
>> 2191 config 32BIT
>> 2192 bool "32-bit kernel"
>> 2193 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2194 select TRAD_SIGNALS
>> 2195 help
>> 2196 Select this option if you want to build a 32-bit kernel.
>> 2197
>> 2198 config 64BIT
>> 2199 bool "64-bit kernel"
>> 2200 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2201 help
>> 2202 Select this option if you want to build a 64-bit kernel.
>> 2203
>> 2204 endchoice
>> 2205
>> 2206 config MIPS_VA_BITS_48
>> 2207 bool "48 bits virtual memory"
>> 2208 depends on 64BIT
>> 2209 help
>> 2210 Support a maximum at least 48 bits of application virtual
>> 2211 memory. Default is 40 bits or less, depending on the CPU.
>> 2212 For page sizes 16k and above, this option results in a small
>> 2213 memory overhead for page tables. For 4k page size, a fourth
>> 2214 level of page tables is added which imposes both a memory
>> 2215 overhead as well as slower TLB fault handling.
>> 2216
>> 2217 If unsure, say N.
>> 2218
>> 2219 choice
>> 2220 prompt "Kernel page size"
>> 2221 default PAGE_SIZE_4KB
>> 2222
>> 2223 config PAGE_SIZE_4KB
>> 2224 bool "4kB"
>> 2225 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2226 help
>> 2227 This option select the standard 4kB Linux page size. On some
>> 2228 R3000-family processors this is the only available page size. Using
>> 2229 4kB page size will minimize memory consumption and is therefore
>> 2230 recommended for low memory systems.
>> 2231
>> 2232 config PAGE_SIZE_8KB
>> 2233 bool "8kB"
>> 2234 depends on CPU_CAVIUM_OCTEON
>> 2235 depends on !MIPS_VA_BITS_48
>> 2236 help
>> 2237 Using 8kB page size will result in higher performance kernel at
>> 2238 the price of higher memory consumption. This option is available
>> 2239 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2240 distribution to support this.
>> 2241
>> 2242 config PAGE_SIZE_16KB
>> 2243 bool "16kB"
>> 2244 depends on !CPU_R3000 && !CPU_TX39XX
>> 2245 help
>> 2246 Using 16kB page size will result in higher performance kernel at
>> 2247 the price of higher memory consumption. This option is available on
>> 2248 all non-R3000 family processors. Note that you will need a suitable
>> 2249 Linux distribution to support this.
>> 2250
>> 2251 config PAGE_SIZE_32KB
>> 2252 bool "32kB"
>> 2253 depends on CPU_CAVIUM_OCTEON
>> 2254 depends on !MIPS_VA_BITS_48
>> 2255 help
>> 2256 Using 32kB page size will result in higher performance kernel at
>> 2257 the price of higher memory consumption. This option is available
>> 2258 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2259 distribution to support this.
>> 2260
>> 2261 config PAGE_SIZE_64KB
>> 2262 bool "64kB"
>> 2263 depends on !CPU_R3000 && !CPU_TX39XX
>> 2264 help
>> 2265 Using 64kB page size will result in higher performance kernel at
>> 2266 the price of higher memory consumption. This option is available on
>> 2267 all non-R3000 family processor. Not that at the time of this
>> 2268 writing this option is still high experimental.
>> 2269
>> 2270 endchoice
>> 2271
>> 2272 config FORCE_MAX_ZONEORDER
>> 2273 int "Maximum zone order"
>> 2274 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2275 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2276 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2277 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2278 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2279 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2280 range 0 64
>> 2281 default "11"
>> 2282 help
>> 2283 The kernel memory allocator divides physically contiguous memory
>> 2284 blocks into "zones", where each zone is a power of two number of
>> 2285 pages. This option selects the largest power of two that the kernel
>> 2286 keeps in the memory allocator. If you need to allocate very large
>> 2287 blocks of physically contiguous memory, then you may need to
>> 2288 increase this value.
>> 2289
>> 2290 This config option is actually maximum order plus one. For example,
>> 2291 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2292
>> 2293 The page size is not necessarily 4KB. Keep this in mind
>> 2294 when choosing a value for this option.
>> 2295
>> 2296 config BOARD_SCACHE
>> 2297 bool
>> 2298
>> 2299 config IP22_CPU_SCACHE
>> 2300 bool
>> 2301 select BOARD_SCACHE
>> 2302
>> 2303 #
>> 2304 # Support for a MIPS32 / MIPS64 style S-caches
>> 2305 #
>> 2306 config MIPS_CPU_SCACHE
>> 2307 bool
>> 2308 select BOARD_SCACHE
>> 2309
>> 2310 config R5000_CPU_SCACHE
>> 2311 bool
>> 2312 select BOARD_SCACHE
>> 2313
>> 2314 config RM7000_CPU_SCACHE
>> 2315 bool
>> 2316 select BOARD_SCACHE
>> 2317
>> 2318 config SIBYTE_DMA_PAGEOPS
>> 2319 bool "Use DMA to clear/copy pages"
>> 2320 depends on CPU_SB1
>> 2321 help
>> 2322 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2323 channel. These DMA channels are otherwise unused by the standard
>> 2324 SiByte Linux port. Seems to give a small performance benefit.
>> 2325
>> 2326 config CPU_HAS_PREFETCH
>> 2327 bool
>> 2328
>> 2329 config CPU_GENERIC_DUMP_TLB
>> 2330 bool
>> 2331 default y if !(CPU_R3000 || CPU_TX39XX)
>> 2332
>> 2333 config MIPS_FP_SUPPORT
>> 2334 bool "Floating Point support" if EXPERT
118 default y 2335 default y
119 help 2336 help
120 Select this if your implementation h !! 2337 Select y to include support for floating point in the kernel
>> 2338 including initialization of FPU hardware, FP context save & restore
>> 2339 and emulation of an FPU where necessary. Without this support any
>> 2340 userland program attempting to use floating point instructions will
>> 2341 receive a SIGILL.
>> 2342
>> 2343 If you know that your userland will not attempt to use floating point
>> 2344 instructions then you can say n here to shrink the kernel a little.
>> 2345
>> 2346 If unsure, say y.
>> 2347
>> 2348 config CPU_R2300_FPU
>> 2349 bool
>> 2350 depends on MIPS_FP_SUPPORT
>> 2351 default y if CPU_R3000 || CPU_TX39XX
>> 2352
>> 2353 config CPU_R3K_TLB
>> 2354 bool
>> 2355
>> 2356 config CPU_R4K_FPU
>> 2357 bool
>> 2358 depends on MIPS_FP_SUPPORT
>> 2359 default y if !CPU_R2300_FPU
>> 2360
>> 2361 config CPU_R4K_CACHE_TLB
>> 2362 bool
>> 2363 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
121 2364
122 config OPENRISC_HAVE_INST_CMOV !! 2365 config MIPS_MT_SMP
123 bool "Have instruction l.cmov for cond !! 2366 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2367 default y
>> 2368 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2369 select CPU_MIPSR2_IRQ_VI
>> 2370 select CPU_MIPSR2_IRQ_EI
>> 2371 select SYNC_R4K
>> 2372 select MIPS_MT
>> 2373 select SMP
>> 2374 select SMP_UP
>> 2375 select SYS_SUPPORTS_SMP
>> 2376 select SYS_SUPPORTS_SCHED_SMT
>> 2377 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2378 help
>> 2379 This is a kernel model which is known as SMVP. This is supported
>> 2380 on cores with the MT ASE and uses the available VPEs to implement
>> 2381 virtual processors which supports SMP. This is equivalent to the
>> 2382 Intel Hyperthreading feature. For further information go to
>> 2383 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2384
>> 2385 config MIPS_MT
>> 2386 bool
>> 2387
>> 2388 config SCHED_SMT
>> 2389 bool "SMT (multithreading) scheduler support"
>> 2390 depends on SYS_SUPPORTS_SCHED_SMT
124 default n 2391 default n
125 help 2392 help
126 This config enables gcc to generate !! 2393 SMT scheduler support improves the CPU scheduler's decision making
127 the kernel which in general will imp !! 2394 when dealing with MIPS MT enabled cores at a cost of slightly
128 binary size. !! 2395 increased overhead in some places. If unsure say N here.
>> 2396
>> 2397 config SYS_SUPPORTS_SCHED_SMT
>> 2398 bool
129 2399
130 Select this if your implementation h !! 2400 config SYS_SUPPORTS_MULTITHREADING
131 l.cmov conistional move instruction. !! 2401 bool
132 2402
133 Say N if you are unsure. !! 2403 config MIPS_MT_FPAFF
>> 2404 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2405 default y
>> 2406 depends on MIPS_MT_SMP
>> 2407
>> 2408 config MIPSR2_TO_R6_EMULATOR
>> 2409 bool "MIPS R2-to-R6 emulator"
>> 2410 depends on CPU_MIPSR6
>> 2411 depends on MIPS_FP_SUPPORT
>> 2412 default y
>> 2413 help
>> 2414 Choose this option if you want to run non-R6 MIPS userland code.
>> 2415 Even if you say 'Y' here, the emulator will still be disabled by
>> 2416 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2417 The only reason this is a build-time option is to save ~14K from the
>> 2418 final kernel image.
>> 2419
>> 2420 config SYS_SUPPORTS_VPE_LOADER
>> 2421 bool
>> 2422 depends on SYS_SUPPORTS_MULTITHREADING
>> 2423 help
>> 2424 Indicates that the platform supports the VPE loader, and provides
>> 2425 physical_memsize.
>> 2426
>> 2427 config MIPS_VPE_LOADER
>> 2428 bool "VPE loader support."
>> 2429 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2430 select CPU_MIPSR2_IRQ_VI
>> 2431 select CPU_MIPSR2_IRQ_EI
>> 2432 select MIPS_MT
>> 2433 help
>> 2434 Includes a loader for loading an elf relocatable object
>> 2435 onto another VPE and running it.
134 2436
135 config OPENRISC_HAVE_INST_ROR !! 2437 config MIPS_VPE_LOADER_CMP
136 bool "Have instruction l.ror for rotat !! 2438 bool
>> 2439 default "y"
>> 2440 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2441
>> 2442 config MIPS_VPE_LOADER_MT
>> 2443 bool
>> 2444 default "y"
>> 2445 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2446
>> 2447 config MIPS_VPE_LOADER_TOM
>> 2448 bool "Load VPE program into memory hidden from linux"
>> 2449 depends on MIPS_VPE_LOADER
>> 2450 default y
>> 2451 help
>> 2452 The loader can use memory that is present but has been hidden from
>> 2453 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2454 you to ensure the amount you put in the option and the space your
>> 2455 program requires is less or equal to the amount physically present.
>> 2456
>> 2457 config MIPS_VPE_APSP_API
>> 2458 bool "Enable support for AP/SP API (RTLX)"
>> 2459 depends on MIPS_VPE_LOADER
>> 2460
>> 2461 config MIPS_VPE_APSP_API_CMP
>> 2462 bool
>> 2463 default "y"
>> 2464 depends on MIPS_VPE_APSP_API && MIPS_CMP
>> 2465
>> 2466 config MIPS_VPE_APSP_API_MT
>> 2467 bool
>> 2468 default "y"
>> 2469 depends on MIPS_VPE_APSP_API && !MIPS_CMP
>> 2470
>> 2471 config MIPS_CMP
>> 2472 bool "MIPS CMP framework support (DEPRECATED)"
>> 2473 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2474 select SMP
>> 2475 select SYNC_R4K
>> 2476 select SYS_SUPPORTS_SMP
>> 2477 select WEAK_ORDERING
137 default n 2478 default n
138 help 2479 help
139 This config enables gcc to generate !! 2480 Select this if you are using a bootloader which implements the "CMP
140 the kernel which in general will imp !! 2481 framework" protocol (ie. YAMON) and want your kernel to make use of
141 binary size. !! 2482 its ability to start secondary CPUs.
>> 2483
>> 2484 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2485 instead of this.
>> 2486
>> 2487 config MIPS_CPS
>> 2488 bool "MIPS Coherent Processing System support"
>> 2489 depends on SYS_SUPPORTS_MIPS_CPS
>> 2490 select MIPS_CM
>> 2491 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2492 select SMP
>> 2493 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2494 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2495 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2496 select SYS_SUPPORTS_SMP
>> 2497 select WEAK_ORDERING
>> 2498 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2499 help
>> 2500 Select this if you wish to run an SMP kernel across multiple cores
>> 2501 within a MIPS Coherent Processing System. When this option is
>> 2502 enabled the kernel will probe for other cores and boot them with
>> 2503 no external assistance. It is safe to enable this when hardware
>> 2504 support is unavailable.
>> 2505
>> 2506 config MIPS_CPS_PM
>> 2507 depends on MIPS_CPS
>> 2508 bool
>> 2509
>> 2510 config MIPS_CM
>> 2511 bool
>> 2512 select MIPS_CPC
>> 2513
>> 2514 config MIPS_CPC
>> 2515 bool
>> 2516
>> 2517 config SB1_PASS_2_WORKAROUNDS
>> 2518 bool
>> 2519 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2520 default y
142 2521
143 Select this if your implementation h !! 2522 config SB1_PASS_2_1_WORKAROUNDS
144 l.ror rotate right instruction. !! 2523 bool
>> 2524 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2525 default y
145 2526
146 Say N if you are unsure. !! 2527 choice
>> 2528 prompt "SmartMIPS or microMIPS ASE support"
147 2529
148 config OPENRISC_HAVE_INST_RORI !! 2530 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
149 bool "Have instruction l.rori for rota !! 2531 bool "None"
150 default n <<
151 help 2532 help
152 This config enables gcc to generate !! 2533 Select this if you want neither microMIPS nor SmartMIPS support
153 the kernel which in general will imp <<
154 binary size. <<
155 2534
156 Select this if your implementation h !! 2535 config CPU_HAS_SMARTMIPS
157 l.rori rotate right with immediate i !! 2536 depends on SYS_SUPPORTS_SMARTMIPS
>> 2537 bool "SmartMIPS"
>> 2538 help
>> 2539 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2540 increased security at both hardware and software level for
>> 2541 smartcards. Enabling this option will allow proper use of the
>> 2542 SmartMIPS instructions by Linux applications. However a kernel with
>> 2543 this option will not work on a MIPS core without SmartMIPS core. If
>> 2544 you don't know you probably don't have SmartMIPS and should say N
>> 2545 here.
158 2546
159 Say N if you are unsure. !! 2547 config CPU_MICROMIPS
>> 2548 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2549 bool "microMIPS"
>> 2550 help
>> 2551 When this option is enabled the kernel will be built using the
>> 2552 microMIPS ISA
160 2553
161 config OPENRISC_HAVE_INST_SEXT !! 2554 endchoice
162 bool "Have instructions l.ext* for sig !! 2555
163 default n !! 2556 config CPU_HAS_MSA
>> 2557 bool "Support for the MIPS SIMD Architecture"
>> 2558 depends on CPU_SUPPORTS_MSA
>> 2559 depends on MIPS_FP_SUPPORT
>> 2560 depends on 64BIT || MIPS_O32_FP64_SUPPORT
164 help 2561 help
165 This config enables gcc to generate !! 2562 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
166 the kernel which in general will imp !! 2563 and a set of SIMD instructions to operate on them. When this option
167 binary size. !! 2564 is enabled the kernel will support allocating & switching MSA
>> 2565 vector register contexts. If you know that your kernel will only be
>> 2566 running on CPUs which do not support MSA or that your userland will
>> 2567 not be making use of it then you may wish to say N here to reduce
>> 2568 the size & complexity of your kernel.
>> 2569
>> 2570 If unsure, say Y.
>> 2571
>> 2572 config CPU_HAS_WB
>> 2573 bool
>> 2574
>> 2575 config XKS01
>> 2576 bool
>> 2577
>> 2578 config CPU_HAS_DIEI
>> 2579 depends on !CPU_DIEI_BROKEN
>> 2580 bool
168 2581
169 Select this if your implementation h !! 2582 config CPU_DIEI_BROKEN
170 l.exths, l.extbs, l.exthz and l.extb !! 2583 bool
171 2584
172 Say N if you are unsure. !! 2585 config CPU_HAS_RIXI
>> 2586 bool
173 2587
174 endmenu !! 2588 config CPU_NO_LOAD_STORE_LR
>> 2589 bool
>> 2590 help
>> 2591 CPU lacks support for unaligned load and store instructions:
>> 2592 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2593 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2594 systems).
175 2595
176 config NR_CPUS !! 2596 #
177 int "Maximum number of CPUs (2-32)" !! 2597 # Vectored interrupt mode is an R2 feature
178 range 2 32 !! 2598 #
179 depends on SMP !! 2599 config CPU_MIPSR2_IRQ_VI
180 default "2" !! 2600 bool
>> 2601
>> 2602 #
>> 2603 # Extended interrupt mode is an R2 feature
>> 2604 #
>> 2605 config CPU_MIPSR2_IRQ_EI
>> 2606 bool
>> 2607
>> 2608 config CPU_HAS_SYNC
>> 2609 bool
>> 2610 depends on !CPU_R3000
>> 2611 default y
>> 2612
>> 2613 #
>> 2614 # CPU non-features
>> 2615 #
>> 2616 config CPU_DADDI_WORKAROUNDS
>> 2617 bool
>> 2618
>> 2619 config CPU_R4000_WORKAROUNDS
>> 2620 bool
>> 2621 select CPU_R4400_WORKAROUNDS
>> 2622
>> 2623 config CPU_R4400_WORKAROUNDS
>> 2624 bool
>> 2625
>> 2626 config CPU_R4X00_BUGS64
>> 2627 bool
>> 2628 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
>> 2629
>> 2630 config MIPS_ASID_SHIFT
>> 2631 int
>> 2632 default 6 if CPU_R3000 || CPU_TX39XX
>> 2633 default 0
>> 2634
>> 2635 config MIPS_ASID_BITS
>> 2636 int
>> 2637 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2638 default 6 if CPU_R3000 || CPU_TX39XX
>> 2639 default 8
>> 2640
>> 2641 config MIPS_ASID_BITS_VARIABLE
>> 2642 bool
>> 2643
>> 2644 config MIPS_CRC_SUPPORT
>> 2645 bool
>> 2646
>> 2647 # R4600 erratum. Due to the lack of errata information the exact
>> 2648 # technical details aren't known. I've experimentally found that disabling
>> 2649 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2650 # with the issue.
>> 2651 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2652 bool
>> 2653
>> 2654 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
>> 2655 #
>> 2656 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2657 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2658 # executed if there is no other dcache activity. If the dcache is
>> 2659 # accessed for another instruction immediately preceding when these
>> 2660 # cache instructions are executing, it is possible that the dcache
>> 2661 # tag match outputs used by these cache instructions will be
>> 2662 # incorrect. These cache instructions should be preceded by at least
>> 2663 # four instructions that are not any kind of load or store
>> 2664 # instruction.
>> 2665 #
>> 2666 # This is not allowed: lw
>> 2667 # nop
>> 2668 # nop
>> 2669 # nop
>> 2670 # cache Hit_Writeback_Invalidate_D
>> 2671 #
>> 2672 # This is allowed: lw
>> 2673 # nop
>> 2674 # nop
>> 2675 # nop
>> 2676 # nop
>> 2677 # cache Hit_Writeback_Invalidate_D
>> 2678 config WAR_R4600_V1_HIT_CACHEOP
>> 2679 bool
>> 2680
>> 2681 # Writeback and invalidate the primary cache dcache before DMA.
>> 2682 #
>> 2683 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2684 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2685 # operate correctly if the internal data cache refill buffer is empty. These
>> 2686 # CACHE instructions should be separated from any potential data cache miss
>> 2687 # by a load instruction to an uncached address to empty the response buffer."
>> 2688 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2689 # in .pdf format.)
>> 2690 config WAR_R4600_V2_HIT_CACHEOP
>> 2691 bool
>> 2692
>> 2693 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
>> 2694 # the line which this instruction itself exists, the following
>> 2695 # operation is not guaranteed."
>> 2696 #
>> 2697 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2698 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2699 bool
>> 2700
>> 2701 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2702 # opposes it being called that) where invalid instructions in the same
>> 2703 # I-cache line worth of instructions being fetched may case spurious
>> 2704 # exceptions.
>> 2705 config WAR_ICACHE_REFILLS
>> 2706 bool
>> 2707
>> 2708 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
>> 2709 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2710 config WAR_R10000_LLSC
>> 2711 bool
>> 2712
>> 2713 # 34K core erratum: "Problems Executing the TLBR Instruction"
>> 2714 config WAR_MIPS34K_MISSED_ITLB
>> 2715 bool
>> 2716
>> 2717 #
>> 2718 # - Highmem only makes sense for the 32-bit kernel.
>> 2719 # - The current highmem code will only work properly on physically indexed
>> 2720 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2721 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2722 # moment we protect the user and offer the highmem option only on machines
>> 2723 # where it's known to be safe. This will not offer highmem on a few systems
>> 2724 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2725 # indexed CPUs but we're playing safe.
>> 2726 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2727 # know they might have memory configurations that could make use of highmem
>> 2728 # support.
>> 2729 #
>> 2730 config HIGHMEM
>> 2731 bool "High Memory Support"
>> 2732 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2733 select KMAP_LOCAL
>> 2734
>> 2735 config CPU_SUPPORTS_HIGHMEM
>> 2736 bool
>> 2737
>> 2738 config SYS_SUPPORTS_HIGHMEM
>> 2739 bool
>> 2740
>> 2741 config SYS_SUPPORTS_SMARTMIPS
>> 2742 bool
>> 2743
>> 2744 config SYS_SUPPORTS_MICROMIPS
>> 2745 bool
>> 2746
>> 2747 config SYS_SUPPORTS_MIPS16
>> 2748 bool
>> 2749 help
>> 2750 This option must be set if a kernel might be executed on a MIPS16-
>> 2751 enabled CPU even if MIPS16 is not actually being used. In other
>> 2752 words, it makes the kernel MIPS16-tolerant.
>> 2753
>> 2754 config CPU_SUPPORTS_MSA
>> 2755 bool
>> 2756
>> 2757 config ARCH_FLATMEM_ENABLE
>> 2758 def_bool y
>> 2759 depends on !NUMA && !CPU_LOONGSON2EF
>> 2760
>> 2761 config ARCH_SPARSEMEM_ENABLE
>> 2762 bool
>> 2763 select SPARSEMEM_STATIC if !SGI_IP27
>> 2764
>> 2765 config NUMA
>> 2766 bool "NUMA Support"
>> 2767 depends on SYS_SUPPORTS_NUMA
>> 2768 select SMP
>> 2769 help
>> 2770 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2771 Access). This option improves performance on systems with more
>> 2772 than two nodes; on two node systems it is generally better to
>> 2773 leave it disabled; on single node systems leave this option
>> 2774 disabled.
>> 2775
>> 2776 config SYS_SUPPORTS_NUMA
>> 2777 bool
>> 2778
>> 2779 config HAVE_SETUP_PER_CPU_AREA
>> 2780 def_bool y
>> 2781 depends on NUMA
>> 2782
>> 2783 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2784 def_bool y
>> 2785 depends on NUMA
>> 2786
>> 2787 config RELOCATABLE
>> 2788 bool "Relocatable kernel"
>> 2789 depends on SYS_SUPPORTS_RELOCATABLE
>> 2790 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2791 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2792 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2793 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2794 CPU_LOONGSON64
>> 2795 help
>> 2796 This builds a kernel image that retains relocation information
>> 2797 so it can be loaded someplace besides the default 1MB.
>> 2798 The relocations make the kernel binary about 15% larger,
>> 2799 but are discarded at runtime
>> 2800
>> 2801 config RELOCATION_TABLE_SIZE
>> 2802 hex "Relocation table size"
>> 2803 depends on RELOCATABLE
>> 2804 range 0x0 0x01000000
>> 2805 default "0x00200000" if CPU_LOONGSON64
>> 2806 default "0x00100000"
>> 2807 help
>> 2808 A table of relocation data will be appended to the kernel binary
>> 2809 and parsed at boot to fix up the relocated kernel.
>> 2810
>> 2811 This option allows the amount of space reserved for the table to be
>> 2812 adjusted, although the default of 1Mb should be ok in most cases.
>> 2813
>> 2814 The build will fail and a valid size suggested if this is too small.
>> 2815
>> 2816 If unsure, leave at the default value.
>> 2817
>> 2818 config RANDOMIZE_BASE
>> 2819 bool "Randomize the address of the kernel image"
>> 2820 depends on RELOCATABLE
>> 2821 help
>> 2822 Randomizes the physical and virtual address at which the
>> 2823 kernel image is loaded, as a security feature that
>> 2824 deters exploit attempts relying on knowledge of the location
>> 2825 of kernel internals.
>> 2826
>> 2827 Entropy is generated using any coprocessor 0 registers available.
>> 2828
>> 2829 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2830
>> 2831 If unsure, say N.
>> 2832
>> 2833 config RANDOMIZE_BASE_MAX_OFFSET
>> 2834 hex "Maximum kASLR offset" if EXPERT
>> 2835 depends on RANDOMIZE_BASE
>> 2836 range 0x0 0x40000000 if EVA || 64BIT
>> 2837 range 0x0 0x08000000
>> 2838 default "0x01000000"
>> 2839 help
>> 2840 When kASLR is active, this provides the maximum offset that will
>> 2841 be applied to the kernel image. It should be set according to the
>> 2842 amount of physical RAM available in the target system minus
>> 2843 PHYSICAL_START and must be a power of 2.
>> 2844
>> 2845 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2846 EVA or 64-bit. The default is 16Mb.
>> 2847
>> 2848 config NODES_SHIFT
>> 2849 int
>> 2850 default "6"
>> 2851 depends on NUMA
>> 2852
>> 2853 config HW_PERF_EVENTS
>> 2854 bool "Enable hardware performance counter support for perf events"
>> 2855 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2856 default y
>> 2857 help
>> 2858 Enable hardware performance counter support for perf events. If
>> 2859 disabled, perf events will use software events only.
>> 2860
>> 2861 config DMI
>> 2862 bool "Enable DMI scanning"
>> 2863 depends on MACH_LOONGSON64
>> 2864 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2865 default y
>> 2866 help
>> 2867 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2868 here unless you have verified that your setup is not
>> 2869 affected by entries in the DMI blacklist. Required by PNP
>> 2870 BIOS code.
181 2871
182 config SMP 2872 config SMP
183 bool "Symmetric Multi-Processing suppo !! 2873 bool "Multi-Processing support"
>> 2874 depends on SYS_SUPPORTS_SMP
184 help 2875 help
185 This enables support for systems wit 2876 This enables support for systems with more than one CPU. If you have
186 a system with only one CPU, say N. I 2877 a system with only one CPU, say N. If you have a system with more
187 than one CPU, say Y. 2878 than one CPU, say Y.
188 2879
>> 2880 If you say N here, the kernel will run on uni- and multiprocessor
>> 2881 machines, but will use only one CPU of a multiprocessor machine. If
>> 2882 you say Y here, the kernel will run on many, but not all,
>> 2883 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2884 will run faster if you say N here.
>> 2885
>> 2886 People using multiprocessor machines who say Y here should also say
>> 2887 Y to "Enhanced Real Time Clock Support", below.
>> 2888
>> 2889 See also the SMP-HOWTO available at
>> 2890 <https://www.tldp.org/docs.html#howto>.
>> 2891
189 If you don't know what to do here, s 2892 If you don't know what to do here, say N.
190 2893
191 config FPU !! 2894 config HOTPLUG_CPU
192 bool "FPU support" !! 2895 bool "Support for hot-pluggable CPUs"
193 default y !! 2896 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
194 help 2897 help
195 Say N here if you want to disable al !! 2898 Say Y here to allow turning CPUs off and on. CPUs can be
196 in the kernel and reduce binary size !! 2899 controlled through /sys/devices/system/cpu.
>> 2900 (Note: power management support will enable this option
>> 2901 automatically on SMP systems. )
>> 2902 Say N if you want to disable CPU hotplug.
197 2903
198 If you don't know what to do here, s !! 2904 config SMP_UP
>> 2905 bool
199 2906
200 source "kernel/Kconfig.hz" !! 2907 config SYS_SUPPORTS_MIPS_CMP
>> 2908 bool
201 2909
202 config OPENRISC_NO_SPR_SR_DSX !! 2910 config SYS_SUPPORTS_MIPS_CPS
203 bool "use SPR_SR_DSX software emulatio !! 2911 bool
204 default y !! 2912
>> 2913 config SYS_SUPPORTS_SMP
>> 2914 bool
>> 2915
>> 2916 config NR_CPUS_DEFAULT_4
>> 2917 bool
>> 2918
>> 2919 config NR_CPUS_DEFAULT_8
>> 2920 bool
>> 2921
>> 2922 config NR_CPUS_DEFAULT_16
>> 2923 bool
>> 2924
>> 2925 config NR_CPUS_DEFAULT_32
>> 2926 bool
>> 2927
>> 2928 config NR_CPUS_DEFAULT_64
>> 2929 bool
>> 2930
>> 2931 config NR_CPUS
>> 2932 int "Maximum number of CPUs (2-256)"
>> 2933 range 2 256
>> 2934 depends on SMP
>> 2935 default "4" if NR_CPUS_DEFAULT_4
>> 2936 default "8" if NR_CPUS_DEFAULT_8
>> 2937 default "16" if NR_CPUS_DEFAULT_16
>> 2938 default "32" if NR_CPUS_DEFAULT_32
>> 2939 default "64" if NR_CPUS_DEFAULT_64
205 help 2940 help
206 SPR_SR_DSX bit is status register bi !! 2941 This allows you to specify the maximum number of CPUs which this
207 the last exception has happened in d !! 2942 kernel will support. The maximum supported value is 32 for 32-bit
>> 2943 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2944 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2945 and 2 for all others.
>> 2946
>> 2947 This is purely to save memory - each supported CPU adds
>> 2948 approximately eight kilobytes to the kernel image. For best
>> 2949 performance should round up your number of processors to the next
>> 2950 power of two.
208 2951
209 OpenRISC architecture makes it optio !! 2952 config MIPS_PERF_SHARED_TC_COUNTERS
210 in hardware and the OR1200 does not !! 2953 bool
211 2954
212 Say N here if you know that your Ope !! 2955 config MIPS_NR_CPU_NR_MAP_1024
213 SPR_SR_DSX bit implemented. Say Y if !! 2956 bool
214 2957
215 config OPENRISC_HAVE_SHADOW_GPRS !! 2958 config MIPS_NR_CPU_NR_MAP
216 bool "Support for shadow gpr files" if !! 2959 int
217 default y if SMP !! 2960 depends on SMP
>> 2961 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2962 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2963
>> 2964 #
>> 2965 # Timer Interrupt Frequency Configuration
>> 2966 #
>> 2967
>> 2968 choice
>> 2969 prompt "Timer frequency"
>> 2970 default HZ_250
218 help 2971 help
219 Say Y here if your OpenRISC processo !! 2972 Allows the configuration of the timer frequency.
220 register files. They will in such ca !! 2973
221 scratch reg storage on exception ent !! 2974 config HZ_24
222 !! 2975 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
223 On SMP systems, this feature is mand !! 2976
224 On a unicore system it's safe to say !! 2977 config HZ_48
225 !! 2978 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
226 config CMDLINE !! 2979
227 string "Default kernel command string" !! 2980 config HZ_100
228 default "" !! 2981 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
229 help !! 2982
230 On some architectures there is curre !! 2983 config HZ_128
231 to pass arguments to the kernel. For !! 2984 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
232 supply some command-line options at !! 2985
233 here. !! 2986 config HZ_250
>> 2987 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2988
>> 2989 config HZ_256
>> 2990 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2991
>> 2992 config HZ_1000
>> 2993 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2994
>> 2995 config HZ_1024
>> 2996 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2997
>> 2998 endchoice
>> 2999
>> 3000 config SYS_SUPPORTS_24HZ
>> 3001 bool
234 3002
235 menu "Debugging options" !! 3003 config SYS_SUPPORTS_48HZ
>> 3004 bool
236 3005
237 config JUMP_UPON_UNHANDLED_EXCEPTION !! 3006 config SYS_SUPPORTS_100HZ
238 bool "Try to die gracefully" !! 3007 bool
>> 3008
>> 3009 config SYS_SUPPORTS_128HZ
>> 3010 bool
>> 3011
>> 3012 config SYS_SUPPORTS_250HZ
>> 3013 bool
>> 3014
>> 3015 config SYS_SUPPORTS_256HZ
>> 3016 bool
>> 3017
>> 3018 config SYS_SUPPORTS_1000HZ
>> 3019 bool
>> 3020
>> 3021 config SYS_SUPPORTS_1024HZ
>> 3022 bool
>> 3023
>> 3024 config SYS_SUPPORTS_ARBIT_HZ
>> 3025 bool
>> 3026 default y if !SYS_SUPPORTS_24HZ && \
>> 3027 !SYS_SUPPORTS_48HZ && \
>> 3028 !SYS_SUPPORTS_100HZ && \
>> 3029 !SYS_SUPPORTS_128HZ && \
>> 3030 !SYS_SUPPORTS_250HZ && \
>> 3031 !SYS_SUPPORTS_256HZ && \
>> 3032 !SYS_SUPPORTS_1000HZ && \
>> 3033 !SYS_SUPPORTS_1024HZ
>> 3034
>> 3035 config HZ
>> 3036 int
>> 3037 default 24 if HZ_24
>> 3038 default 48 if HZ_48
>> 3039 default 100 if HZ_100
>> 3040 default 128 if HZ_128
>> 3041 default 250 if HZ_250
>> 3042 default 256 if HZ_256
>> 3043 default 1000 if HZ_1000
>> 3044 default 1024 if HZ_1024
>> 3045
>> 3046 config SCHED_HRTICK
>> 3047 def_bool HIGH_RES_TIMERS
>> 3048
>> 3049 config KEXEC
>> 3050 bool "Kexec system call"
>> 3051 select KEXEC_CORE
>> 3052 help
>> 3053 kexec is a system call that implements the ability to shutdown your
>> 3054 current kernel, and to start another kernel. It is like a reboot
>> 3055 but it is independent of the system firmware. And like a reboot
>> 3056 you can start any kernel with it, not just Linux.
>> 3057
>> 3058 The name comes from the similarity to the exec system call.
>> 3059
>> 3060 It is an ongoing process to be certain the hardware in a machine
>> 3061 is properly shutdown, so do not be surprised if this code does not
>> 3062 initially work for you. As of this writing the exact hardware
>> 3063 interface is strongly in flux, so no good recommendation can be
>> 3064 made.
>> 3065
>> 3066 config CRASH_DUMP
>> 3067 bool "Kernel crash dumps"
>> 3068 help
>> 3069 Generate crash dump after being started by kexec.
>> 3070 This should be normally only set in special crash dump kernels
>> 3071 which are loaded in the main kernel with kexec-tools into
>> 3072 a specially reserved region and then later executed after
>> 3073 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3074 to a memory address not used by the main kernel or firmware using
>> 3075 PHYSICAL_START.
>> 3076
>> 3077 config PHYSICAL_START
>> 3078 hex "Physical address where the kernel is loaded"
>> 3079 default "0xffffffff84000000"
>> 3080 depends on CRASH_DUMP
>> 3081 help
>> 3082 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3083 If you plan to use kernel for capturing the crash dump change
>> 3084 this value to start of the reserved region (the "X" value as
>> 3085 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3086 passed to the panic-ed kernel).
>> 3087
>> 3088 config MIPS_O32_FP64_SUPPORT
>> 3089 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3090 depends on 32BIT || MIPS32_O32
>> 3091 help
>> 3092 When this is enabled, the kernel will support use of 64-bit floating
>> 3093 point registers with binaries using the O32 ABI along with the
>> 3094 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3095 32-bit MIPS systems this support is at the cost of increasing the
>> 3096 size and complexity of the compiled FPU emulator. Thus if you are
>> 3097 running a MIPS32 system and know that none of your userland binaries
>> 3098 will require 64-bit floating point, you may wish to reduce the size
>> 3099 of your kernel & potentially improve FP emulation performance by
>> 3100 saying N here.
>> 3101
>> 3102 Although binutils currently supports use of this flag the details
>> 3103 concerning its effect upon the O32 ABI in userland are still being
>> 3104 worked on. In order to avoid userland becoming dependent upon current
>> 3105 behaviour before the details have been finalised, this option should
>> 3106 be considered experimental and only enabled by those working upon
>> 3107 said details.
>> 3108
>> 3109 If unsure, say N.
>> 3110
>> 3111 config USE_OF
>> 3112 bool
>> 3113 select OF
>> 3114 select OF_EARLY_FLATTREE
>> 3115 select IRQ_DOMAIN
>> 3116
>> 3117 config UHI_BOOT
>> 3118 bool
>> 3119
>> 3120 config BUILTIN_DTB
>> 3121 bool
>> 3122
>> 3123 choice
>> 3124 prompt "Kernel appended dtb support" if USE_OF
>> 3125 default MIPS_NO_APPENDED_DTB
>> 3126
>> 3127 config MIPS_NO_APPENDED_DTB
>> 3128 bool "None"
>> 3129 help
>> 3130 Do not enable appended dtb support.
>> 3131
>> 3132 config MIPS_ELF_APPENDED_DTB
>> 3133 bool "vmlinux"
>> 3134 help
>> 3135 With this option, the boot code will look for a device tree binary
>> 3136 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3137 it is empty and the DTB can be appended using binutils command
>> 3138 objcopy:
>> 3139
>> 3140 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3141
>> 3142 This is meant as a backward compatibility convenience for those
>> 3143 systems with a bootloader that can't be upgraded to accommodate
>> 3144 the documented boot protocol using a device tree.
>> 3145
>> 3146 config MIPS_RAW_APPENDED_DTB
>> 3147 bool "vmlinux.bin or vmlinuz.bin"
>> 3148 help
>> 3149 With this option, the boot code will look for a device tree binary
>> 3150 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3151 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3152
>> 3153 This is meant as a backward compatibility convenience for those
>> 3154 systems with a bootloader that can't be upgraded to accommodate
>> 3155 the documented boot protocol using a device tree.
>> 3156
>> 3157 Beware that there is very little in terms of protection against
>> 3158 this option being confused by leftover garbage in memory that might
>> 3159 look like a DTB header after a reboot if no actual DTB is appended
>> 3160 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3161 if you don't intend to always append a DTB.
>> 3162 endchoice
>> 3163
>> 3164 choice
>> 3165 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3166 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3167 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3168 !CAVIUM_OCTEON_SOC
>> 3169 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3170
>> 3171 config MIPS_CMDLINE_FROM_DTB
>> 3172 depends on USE_OF
>> 3173 bool "Dtb kernel arguments if available"
>> 3174
>> 3175 config MIPS_CMDLINE_DTB_EXTEND
>> 3176 depends on USE_OF
>> 3177 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3178
>> 3179 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3180 bool "Bootloader kernel arguments if available"
>> 3181
>> 3182 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3183 depends on CMDLINE_BOOL
>> 3184 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3185 endchoice
>> 3186
>> 3187 endmenu
>> 3188
>> 3189 config LOCKDEP_SUPPORT
>> 3190 bool
239 default y 3191 default y
>> 3192
>> 3193 config STACKTRACE_SUPPORT
>> 3194 bool
>> 3195 default y
>> 3196
>> 3197 config PGTABLE_LEVELS
>> 3198 int
>> 3199 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3200 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3201 default 2
>> 3202
>> 3203 config MIPS_AUTO_PFN_OFFSET
>> 3204 bool
>> 3205
>> 3206 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3207
>> 3208 config PCI_DRIVERS_GENERIC
>> 3209 select PCI_DOMAINS_GENERIC if PCI
>> 3210 bool
>> 3211
>> 3212 config PCI_DRIVERS_LEGACY
>> 3213 def_bool !PCI_DRIVERS_GENERIC
>> 3214 select NO_GENERIC_PCI_IOPORT_MAP
>> 3215 select PCI_DOMAINS if PCI
>> 3216
>> 3217 #
>> 3218 # ISA support is now enabled via select. Too many systems still have the one
>> 3219 # or other ISA chip on the board that users don't know about so don't expect
>> 3220 # users to choose the right thing ...
>> 3221 #
>> 3222 config ISA
>> 3223 bool
>> 3224
>> 3225 config TC
>> 3226 bool "TURBOchannel support"
>> 3227 depends on MACH_DECSTATION
240 help 3228 help
241 Now this puts kernel into infinite l !! 3229 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
242 your kernel crashes this doesn't hav !! 3230 processors. TURBOchannel programming specifications are available
>> 3231 at:
>> 3232 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3233 and:
>> 3234 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3235 Linux driver support status is documented at:
>> 3236 <http://www.linux-mips.org/wiki/DECstation>
243 3237
244 Say Y if you are unsure. !! 3238 config MMU
>> 3239 bool
>> 3240 default y
245 3241
246 config OPENRISC_ESR_EXCEPTION_BUG_CHECK !! 3242 config ARCH_MMAP_RND_BITS_MIN
247 bool "Check for possible ESR exception !! 3243 default 12 if 64BIT
248 default n !! 3244 default 8
>> 3245
>> 3246 config ARCH_MMAP_RND_BITS_MAX
>> 3247 default 18 if 64BIT
>> 3248 default 15
>> 3249
>> 3250 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3251 default 8
>> 3252
>> 3253 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3254 default 15
>> 3255
>> 3256 config I8253
>> 3257 bool
>> 3258 select CLKSRC_I8253
>> 3259 select CLKEVT_I8253
>> 3260 select MIPS_EXTERNAL_TIMER
>> 3261 endmenu
>> 3262
>> 3263 config TRAD_SIGNALS
>> 3264 bool
>> 3265
>> 3266 config MIPS32_COMPAT
>> 3267 bool
>> 3268
>> 3269 config COMPAT
>> 3270 bool
>> 3271
>> 3272 config SYSVIPC_COMPAT
>> 3273 bool
>> 3274
>> 3275 config MIPS32_O32
>> 3276 bool "Kernel support for o32 binaries"
>> 3277 depends on 64BIT
>> 3278 select ARCH_WANT_OLD_COMPAT_IPC
>> 3279 select COMPAT
>> 3280 select MIPS32_COMPAT
>> 3281 select SYSVIPC_COMPAT if SYSVIPC
>> 3282 help
>> 3283 Select this option if you want to run o32 binaries. These are pure
>> 3284 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3285 existing binaries are in this format.
>> 3286
>> 3287 If unsure, say Y.
>> 3288
>> 3289 config MIPS32_N32
>> 3290 bool "Kernel support for n32 binaries"
>> 3291 depends on 64BIT
>> 3292 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3293 select COMPAT
>> 3294 select MIPS32_COMPAT
>> 3295 select SYSVIPC_COMPAT if SYSVIPC
249 help 3296 help
250 This option enables some checks that !! 3297 Select this option if you want to run n32 binaries. These are
251 in kernel. !! 3298 64-bit binaries using 32-bit quantities for addressing and certain
>> 3299 data that would normally be 64-bit. They are used in special
>> 3300 cases.
>> 3301
>> 3302 If unsure, say N.
>> 3303
>> 3304 menu "Power management options"
>> 3305
>> 3306 config ARCH_HIBERNATION_POSSIBLE
>> 3307 def_bool y
>> 3308 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3309
>> 3310 config ARCH_SUSPEND_POSSIBLE
>> 3311 def_bool y
>> 3312 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
252 3313
253 Say N if you are unsure. !! 3314 source "kernel/power/Kconfig"
254 3315
255 endmenu 3316 endmenu
256 3317
>> 3318 config MIPS_EXTERNAL_TIMER
>> 3319 bool
>> 3320
>> 3321 menu "CPU Power Management"
>> 3322
>> 3323 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3324 source "drivers/cpufreq/Kconfig"
>> 3325 endif
>> 3326
>> 3327 source "drivers/cpuidle/Kconfig"
>> 3328
257 endmenu 3329 endmenu
>> 3330
>> 3331 source "arch/mips/kvm/Kconfig"
>> 3332
>> 3333 source "arch/mips/vdso/Kconfig"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.