1 /* SPDX-License-Identifier: GPL-2.0-or-later * !! 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* !! 2 /* arch/sparc/kernel/entry.S: Sparc trap low-level entry points.
3 * OpenRISC entry.S <<
4 * 3 *
5 * Linux architectural port borrowing liberall !! 4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
6 * others. All original copyrights apply as p !! 5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * declaration. !! 6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * !! 7 * Copyright (C) 1996-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 * Modifications for the OpenRISC architecture !! 8 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@ <<
11 * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.c <<
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@so <<
13 */ 9 */
14 10
>> 11 #include <linux/export.h>
15 #include <linux/linkage.h> 12 #include <linux/linkage.h>
>> 13 #include <linux/errno.h>
16 #include <linux/pgtable.h> 14 #include <linux/pgtable.h>
17 15
18 #include <asm/processor.h> !! 16 #include <asm/head.h>
19 #include <asm/unistd.h> !! 17 #include <asm/asi.h>
20 #include <asm/thread_info.h> !! 18 #include <asm/smp.h>
21 #include <asm/errno.h> !! 19 #include <asm/contregs.h>
22 #include <asm/spr_defs.h> !! 20 #include <asm/ptrace.h>
23 #include <asm/page.h> <<
24 #include <asm/mmu.h> <<
25 #include <asm/asm-offsets.h> 21 #include <asm/asm-offsets.h>
>> 22 #include <asm/psr.h>
>> 23 #include <asm/vaddrs.h>
>> 24 #include <asm/page.h>
>> 25 #include <asm/winmacro.h>
>> 26 #include <asm/signal.h>
>> 27 #include <asm/obio.h>
>> 28 #include <asm/mxcc.h>
>> 29 #include <asm/thread_info.h>
>> 30 #include <asm/param.h>
>> 31 #include <asm/unistd.h>
26 32
27 #define DISABLE_INTERRUPTS(t1,t2) !! 33 #include <asm/asmmacro.h>
28 l.mfspr t2,r0,SPR_SR <<
29 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE) <<
30 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_T <<
31 l.and t2,t2,t1 <<
32 l.mtspr r0,t2,SPR_SR <<
33 <<
34 #define ENABLE_INTERRUPTS(t1) <<
35 l.mfspr t1,r0,SPR_SR <<
36 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE <<
37 l.mtspr r0,t1,SPR_SR <<
38 <<
39 /* =========================================== <<
40 <<
41 #ifdef CONFIG_TRACE_IRQFLAGS <<
42 /* <<
43 * Trace irq on/off creating a stack frame. <<
44 */ <<
45 #define TRACE_IRQS_OP(trace_op) <<
46 l.sw -8(r1),r2 /* store frame <<
47 l.sw -4(r1),r9 /* store retur <<
48 l.addi r2,r1,0 /* move sp to <<
49 l.jal trace_op <<
50 l.addi r1,r1,-8 <<
51 l.ori r1,r2,0 /* restore sp <<
52 l.lwz r9,-4(r1) /* restore ret <<
53 l.lwz r2,-8(r1) /* restore fp <<
54 /* <<
55 * Trace irq on/off and save registers we need <<
56 * clobbered. <<
57 */ <<
58 #define TRACE_IRQS_SAVE(t1,trace_op) <<
59 l.sw -12(r1),t1 /* save extra <<
60 l.sw -8(r1),r2 /* store frame <<
61 l.sw -4(r1),r9 /* store retur <<
62 l.addi r2,r1,0 /* move sp to <<
63 l.jal trace_op <<
64 l.addi r1,r1,-12 <<
65 l.ori r1,r2,0 /* restore sp <<
66 l.lwz r9,-4(r1) /* restore ret <<
67 l.lwz r2,-8(r1) /* restore fp <<
68 l.lwz t1,-12(r1) /* restore ext <<
69 <<
70 #define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_ha <<
71 #define TRACE_IRQS_ON TRACE_IRQS_OP(trace_ha <<
72 #define TRACE_IRQS_ON_SYSCALL <<
73 TRACE_IRQS_SAVE(r10,trace_hardirqs_on) <<
74 l.lwz r3,PT_GPR3(r1) <<
75 l.lwz r4,PT_GPR4(r1) <<
76 l.lwz r5,PT_GPR5(r1) <<
77 l.lwz r6,PT_GPR6(r1) <<
78 l.lwz r7,PT_GPR7(r1) <<
79 l.lwz r8,PT_GPR8(r1) <<
80 l.lwz r11,PT_GPR11(r1) <<
81 #define TRACE_IRQS_OFF_ENTRY <<
82 l.lwz r5,PT_SR(r1) <<
83 l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) <<
84 l.sfeq r5,r0 /* skip trace <<
85 l.bf 1f <<
86 l.nop <<
87 TRACE_IRQS_SAVE(r4,trace_hardirqs_off) <<
88 1: <<
89 #else <<
90 #define TRACE_IRQS_OFF <<
91 #define TRACE_IRQS_ON <<
92 #define TRACE_IRQS_OFF_ENTRY <<
93 #define TRACE_IRQS_ON_SYSCALL <<
94 #endif <<
95 <<
96 /* <<
97 * We need to disable interrupts at beginning <<
98 * since interrupt might come in after we've l <<
99 * and overwrite EPC with address somewhere in <<
100 * which is of course wrong! <<
101 */ <<
102 <<
103 #define RESTORE_ALL <<
104 DISABLE_INTERRUPTS(r3,r4) <<
105 l.lwz r3,PT_PC(r1) <<
106 l.mtspr r0,r3,SPR_EPCR_BASE <<
107 l.lwz r3,PT_SR(r1) <<
108 l.mtspr r0,r3,SPR_ESR_BASE <<
109 l.lwz r2,PT_GPR2(r1) <<
110 l.lwz r3,PT_GPR3(r1) <<
111 l.lwz r4,PT_GPR4(r1) <<
112 l.lwz r5,PT_GPR5(r1) <<
113 l.lwz r6,PT_GPR6(r1) <<
114 l.lwz r7,PT_GPR7(r1) <<
115 l.lwz r8,PT_GPR8(r1) <<
116 l.lwz r9,PT_GPR9(r1) <<
117 l.lwz r10,PT_GPR10(r1) <<
118 l.lwz r11,PT_GPR11(r1) <<
119 l.lwz r12,PT_GPR12(r1) <<
120 l.lwz r13,PT_GPR13(r1) <<
121 l.lwz r14,PT_GPR14(r1) <<
122 l.lwz r15,PT_GPR15(r1) <<
123 l.lwz r16,PT_GPR16(r1) <<
124 l.lwz r17,PT_GPR17(r1) <<
125 l.lwz r18,PT_GPR18(r1) <<
126 l.lwz r19,PT_GPR19(r1) <<
127 l.lwz r20,PT_GPR20(r1) <<
128 l.lwz r21,PT_GPR21(r1) <<
129 l.lwz r22,PT_GPR22(r1) <<
130 l.lwz r23,PT_GPR23(r1) <<
131 l.lwz r24,PT_GPR24(r1) <<
132 l.lwz r25,PT_GPR25(r1) <<
133 l.lwz r26,PT_GPR26(r1) <<
134 l.lwz r27,PT_GPR27(r1) <<
135 l.lwz r28,PT_GPR28(r1) <<
136 l.lwz r29,PT_GPR29(r1) <<
137 l.lwz r30,PT_GPR30(r1) <<
138 l.lwz r31,PT_GPR31(r1) <<
139 l.lwz r1,PT_SP(r1) <<
140 l.rfe <<
141 <<
142 <<
143 #define EXCEPTION_ENTRY(handler) <<
144 .global handler <<
145 handler: <<
146 /* r1, EPCR, ESR a already saved */ <<
147 l.sw PT_GPR2(r1),r2 <<
148 l.sw PT_GPR3(r1),r3 <<
149 /* r4 already save */ <<
150 l.sw PT_GPR5(r1),r5 <<
151 l.sw PT_GPR6(r1),r6 <<
152 l.sw PT_GPR7(r1),r7 <<
153 l.sw PT_GPR8(r1),r8 <<
154 l.sw PT_GPR9(r1),r9 <<
155 /* r10 already saved */ <<
156 l.sw PT_GPR11(r1),r11 <<
157 /* r12 already saved */ <<
158 l.sw PT_GPR13(r1),r13 <<
159 l.sw PT_GPR14(r1),r14 <<
160 l.sw PT_GPR15(r1),r15 <<
161 l.sw PT_GPR16(r1),r16 <<
162 l.sw PT_GPR17(r1),r17 <<
163 l.sw PT_GPR18(r1),r18 <<
164 l.sw PT_GPR19(r1),r19 <<
165 l.sw PT_GPR20(r1),r20 <<
166 l.sw PT_GPR21(r1),r21 <<
167 l.sw PT_GPR22(r1),r22 <<
168 l.sw PT_GPR23(r1),r23 <<
169 l.sw PT_GPR24(r1),r24 <<
170 l.sw PT_GPR25(r1),r25 <<
171 l.sw PT_GPR26(r1),r26 <<
172 l.sw PT_GPR27(r1),r27 <<
173 l.sw PT_GPR28(r1),r28 <<
174 l.sw PT_GPR29(r1),r29 <<
175 /* r30 already save */ <<
176 l.sw PT_GPR31(r1),r31 <<
177 TRACE_IRQS_OFF_ENTRY <<
178 /* Store -1 in orig_gpr11 for non-sysc <<
179 l.addi r30,r0,-1 <<
180 l.sw PT_ORIG_GPR11(r1),r30 <<
181 <<
182 #define UNHANDLED_EXCEPTION(handler,vector) <<
183 .global handler <<
184 handler: <<
185 /* r1, EPCR, ESR already saved */ <<
186 l.sw PT_GPR2(r1),r2 <<
187 l.sw PT_GPR3(r1),r3 <<
188 l.sw PT_GPR5(r1),r5 <<
189 l.sw PT_GPR6(r1),r6 <<
190 l.sw PT_GPR7(r1),r7 <<
191 l.sw PT_GPR8(r1),r8 <<
192 l.sw PT_GPR9(r1),r9 <<
193 /* r10 already saved */ <<
194 l.sw PT_GPR11(r1),r11 <<
195 /* r12 already saved */ <<
196 l.sw PT_GPR13(r1),r13 <<
197 l.sw PT_GPR14(r1),r14 <<
198 l.sw PT_GPR15(r1),r15 <<
199 l.sw PT_GPR16(r1),r16 <<
200 l.sw PT_GPR17(r1),r17 <<
201 l.sw PT_GPR18(r1),r18 <<
202 l.sw PT_GPR19(r1),r19 <<
203 l.sw PT_GPR20(r1),r20 <<
204 l.sw PT_GPR21(r1),r21 <<
205 l.sw PT_GPR22(r1),r22 <<
206 l.sw PT_GPR23(r1),r23 <<
207 l.sw PT_GPR24(r1),r24 <<
208 l.sw PT_GPR25(r1),r25 <<
209 l.sw PT_GPR26(r1),r26 <<
210 l.sw PT_GPR27(r1),r27 <<
211 l.sw PT_GPR28(r1),r28 <<
212 l.sw PT_GPR29(r1),r29 <<
213 /* r30 already saved */ <<
214 l.sw PT_GPR31(r1),r31 <<
215 /* Store -1 in orig_gpr11 for non-sysc <<
216 l.addi r30,r0,-1 <<
217 l.sw PT_ORIG_GPR11(r1),r30 <<
218 l.addi r3,r1,0 <<
219 /* r4 is exception EA */ <<
220 l.addi r5,r0,vector <<
221 l.jal unhandled_exception <<
222 l.nop <<
223 l.j _ret_from_exception <<
224 l.nop <<
225 <<
226 /* clobbers 'reg' */ <<
227 #define CLEAR_LWA_FLAG(reg) \ <<
228 l.movhi reg,hi(lwa_flag) ;\ <<
229 l.ori reg,reg,lo(lwa_flag) ;\ <<
230 l.sw 0(reg),r0 <<
231 /* <<
232 * NOTE: one should never assume that SPR_EPC, <<
233 * contain the same values as when excep <<
234 * occured. in fact they never do. if yo <<
235 * values saved on stack (for SPR_EPC, S <<
236 * of r4 (for SPR_EEAR). for details loo <<
237 * in 'arch/openrisc/kernel/head.S' <<
238 */ <<
239 <<
240 /* =========================================== <<
241 <<
242 /* ---[ 0x100: RESET exception ]-------------- <<
243 34
244 EXCEPTION_ENTRY(_tng_kernel_start) !! 35 #define curptr g6
245 l.jal _start <<
246 l.andi r0,r0,0 <<
247 <<
248 /* ---[ 0x200: BUS exception ]---------------- <<
249 <<
250 EXCEPTION_ENTRY(_bus_fault_handler) <<
251 CLEAR_LWA_FLAG(r3) <<
252 /* r4: EA of fault (set by EXCEPTION_H <<
253 l.jal do_bus_fault <<
254 l.addi r3,r1,0 /* pt_regs */ <<
255 <<
256 l.j _ret_from_exception <<
257 l.nop <<
258 <<
259 /* ---[ 0x300: Data Page Fault exception ]---- <<
260 EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler) <<
261 CLEAR_LWA_FLAG(r3) <<
262 l.and r5,r5,r0 <<
263 l.j 1f <<
264 l.nop <<
265 <<
266 EXCEPTION_ENTRY(_data_page_fault_handler) <<
267 CLEAR_LWA_FLAG(r3) <<
268 /* set up parameters for do_page_fault <<
269 l.ori r5,r0,0x300 // <<
270 1: <<
271 l.addi r3,r1,0 // <<
272 /* r4 set be EXCEPTION_HANDLE */ // <<
273 36
274 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX !! 37 /* These are just handy. */
275 l.lwz r6,PT_PC(r3) // !! 38 #define _SV save %sp, -STACKFRAME_SZ, %sp
276 l.lwz r6,0(r6) // !! 39 #define _RS restore
277 !! 40
278 l.srli r6,r6,26 // !! 41 #define FLUSH_ALL_KERNEL_WINDOWS \
279 l.sfeqi r6,0 // !! 42 _SV; _SV; _SV; _SV; _SV; _SV; _SV; \
280 l.bf 8f !! 43 _RS; _RS; _RS; _RS; _RS; _RS; _RS;
281 l.sfeqi r6,1 // !! 44
282 l.bf 8f !! 45 .text
283 l.sfeqi r6,3 // !! 46
284 l.bf 8f !! 47 #ifdef CONFIG_KGDB
285 l.sfeqi r6,4 // !! 48 .align 4
286 l.bf 8f !! 49 .globl arch_kgdb_breakpoint
287 l.sfeqi r6,0x11 // !! 50 .type arch_kgdb_breakpoint,#function
288 l.bf 8f !! 51 arch_kgdb_breakpoint:
289 l.sfeqi r6,0x12 // !! 52 ta 0x7d
290 l.bf 8f !! 53 retl
291 l.nop !! 54 nop
292 !! 55 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
293 l.j 9f <<
294 l.nop <<
295 <<
296 8: // offending insn is in delay slot <<
297 l.lwz r6,PT_PC(r3) // <<
298 l.addi r6,r6,4 <<
299 l.lwz r6,0(r6) // <<
300 l.srli r6,r6,26 // <<
301 9: // offending instruction opcode loaded in r <<
302 <<
303 #else <<
304 <<
305 l.mfspr r6,r0,SPR_SR // <<
306 l.andi r6,r6,SPR_SR_DSX // <<
307 l.sfne r6,r0 // <<
308 l.bnf 7f <<
309 l.lwz r6,PT_PC(r3) // <<
310 <<
311 l.addi r6,r6,4 // <<
312 7: <<
313 l.lwz r6,0(r6) // <<
314 l.srli r6,r6,26 // <<
315 #endif 56 #endif
316 57
317 l.sfgeui r6,0x33 // !! 58 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
318 l.bnf 1f !! 59 .align 4
319 l.sfleui r6,0x37 !! 60 .globl floppy_hardint
320 l.bnf 1f !! 61 floppy_hardint:
321 l.ori r6,r0,0x1 // !! 62 /*
322 l.j 2f !! 63 * This code cannot touch registers %l0 %l1 and %l2
323 l.nop !! 64 * because SAVE_ALL depends on their values. It depends
324 1: l.ori r6,r0,0x0 // !! 65 * on %l3 also, but we regenerate it before a call.
325 2: !! 66 * Other registers are:
326 !! 67 * %l3 -- base address of fdc registers
327 /* call fault.c handler in openrisc/mm !! 68 * %l4 -- pdma_vaddr
328 l.jal do_page_fault !! 69 * %l5 -- scratch for ld/st address
329 l.nop !! 70 * %l6 -- pdma_size
330 l.j _ret_from_exception !! 71 * %l7 -- scratch [floppy byte, ld/st address, aux. data]
331 l.nop !! 72 */
332 <<
333 /* ---[ 0x400: Insn Page Fault exception ]---- <<
334 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler) <<
335 CLEAR_LWA_FLAG(r3) <<
336 l.and r5,r5,r0 <<
337 l.j 1f <<
338 l.nop <<
339 <<
340 EXCEPTION_ENTRY(_insn_page_fault_handler) <<
341 CLEAR_LWA_FLAG(r3) <<
342 /* set up parameters for do_page_fault <<
343 l.ori r5,r0,0x400 // <<
344 1: <<
345 l.addi r3,r1,0 // <<
346 /* r4 set be EXCEPTION_HANDLE */ // <<
347 l.ori r6,r0,0x0 // <<
348 <<
349 /* call fault.c handler in openrisc/mm <<
350 l.jal do_page_fault <<
351 l.nop <<
352 l.j _ret_from_exception <<
353 l.nop <<
354 <<
355 <<
356 /* ---[ 0x500: Timer exception ]-------------- <<
357 <<
358 EXCEPTION_ENTRY(_timer_handler) <<
359 CLEAR_LWA_FLAG(r3) <<
360 l.jal timer_interrupt <<
361 l.addi r3,r1,0 /* pt_regs */ <<
362 <<
363 l.j _ret_from_intr <<
364 l.nop <<
365 <<
366 /* ---[ 0x600: Alignment exception ]---------- <<
367 <<
368 EXCEPTION_ENTRY(_alignment_handler) <<
369 CLEAR_LWA_FLAG(r3) <<
370 /* r4: EA of fault (set by EXCEPTION_H <<
371 l.jal do_unaligned_access <<
372 l.addi r3,r1,0 /* pt_regs */ <<
373 <<
374 l.j _ret_from_exception <<
375 l.nop <<
376 <<
377 #if 0 <<
378 EXCEPTION_ENTRY(_alignment_handler) <<
379 // l.mfspr r2,r0,SPR_EEAR_BASE /* L <<
380 l.addi r2,r4,0 <<
381 // l.mfspr r5,r0,SPR_EPCR_BASE /* L <<
382 l.lwz r5,PT_PC(r1) <<
383 <<
384 l.lwz r3,0(r5) /* Loa <<
385 l.srli r4,r3,26 /* Shi <<
386 <<
387 l.sfeqi r4,0x00 /* Che <<
388 l.bf jmp <<
389 l.sfeqi r4,0x01 <<
390 l.bf jmp <<
391 l.sfeqi r4,0x03 <<
392 l.bf jmp <<
393 l.sfeqi r4,0x04 <<
394 l.bf jmp <<
395 l.sfeqi r4,0x11 <<
396 l.bf jr <<
397 l.sfeqi r4,0x12 <<
398 l.bf jr <<
399 l.nop <<
400 l.j 1f <<
401 l.addi r5,r5,4 /* Inc <<
402 <<
403 jmp: <<
404 l.slli r4,r3,6 /* Get <<
405 l.srai r4,r4,4 <<
406 <<
407 l.lwz r3,4(r5) /* Loa <<
408 <<
409 l.add r5,r5,r4 /* Cal <<
410 <<
411 l.j 1f <<
412 l.srli r4,r3,26 /* Shi <<
413 <<
414 jr: <<
415 l.slli r4,r3,9 /* Shi <<
416 l.andi r4,r4,0x7c <<
417 <<
418 l.lwz r3,4(r5) /* Loa <<
419 <<
420 l.add r4,r4,r1 /* Loa <<
421 l.lwz r5,0(r4) <<
422 <<
423 l.srli r4,r3,26 /* Shi <<
424 73
>> 74 /* Do we have work to do? */
>> 75 sethi %hi(doing_pdma), %l7
>> 76 ld [%l7 + %lo(doing_pdma)], %l7
>> 77 cmp %l7, 0
>> 78 be floppy_dosoftint
>> 79 nop
>> 80
>> 81 /* Load fdc register base */
>> 82 sethi %hi(fdc_status), %l3
>> 83 ld [%l3 + %lo(fdc_status)], %l3
>> 84
>> 85 /* Setup register addresses */
>> 86 sethi %hi(pdma_vaddr), %l5 ! transfer buffer
>> 87 ld [%l5 + %lo(pdma_vaddr)], %l4
>> 88 sethi %hi(pdma_size), %l5 ! bytes to go
>> 89 ld [%l5 + %lo(pdma_size)], %l6
>> 90 next_byte:
>> 91 ldub [%l3], %l7
>> 92
>> 93 andcc %l7, 0x80, %g0 ! Does fifo still have data
>> 94 bz floppy_fifo_emptied ! fifo has been emptied...
>> 95 andcc %l7, 0x20, %g0 ! in non-dma mode still?
>> 96 bz floppy_overrun ! nope, overrun
>> 97 andcc %l7, 0x40, %g0 ! 0=write 1=read
>> 98 bz floppy_write
>> 99 sub %l6, 0x1, %l6
>> 100
>> 101 /* Ok, actually read this byte */
>> 102 ldub [%l3 + 1], %l7
>> 103 orcc %g0, %l6, %g0
>> 104 stb %l7, [%l4]
>> 105 bne next_byte
>> 106 add %l4, 0x1, %l4
>> 107
>> 108 b floppy_tdone
>> 109 nop
>> 110
>> 111 floppy_write:
>> 112 /* Ok, actually write this byte */
>> 113 ldub [%l4], %l7
>> 114 orcc %g0, %l6, %g0
>> 115 stb %l7, [%l3 + 1]
>> 116 bne next_byte
>> 117 add %l4, 0x1, %l4
>> 118
>> 119 /* fall through... */
>> 120 floppy_tdone:
>> 121 sethi %hi(pdma_vaddr), %l5
>> 122 st %l4, [%l5 + %lo(pdma_vaddr)]
>> 123 sethi %hi(pdma_size), %l5
>> 124 st %l6, [%l5 + %lo(pdma_size)]
>> 125 /* Flip terminal count pin */
>> 126 set auxio_register, %l7
>> 127 ld [%l7], %l7
>> 128
>> 129 ldub [%l7], %l5
>> 130
>> 131 or %l5, 0xc2, %l5
>> 132 stb %l5, [%l7]
>> 133 andn %l5, 0x02, %l5
425 134
426 1: !! 135 2:
427 // l.mtspr r0,r5,SPR_EPCR_BASE !! 136 /* Kill some time so the bits set */
428 l.sw PT_PC(r1),r5 !! 137 WRITE_PAUSE
>> 138 WRITE_PAUSE
>> 139
>> 140 stb %l5, [%l7]
>> 141
>> 142 /* Prevent recursion */
>> 143 sethi %hi(doing_pdma), %l7
>> 144 b floppy_dosoftint
>> 145 st %g0, [%l7 + %lo(doing_pdma)]
>> 146
>> 147 /* We emptied the FIFO, but we haven't read everything
>> 148 * as of yet. Store the current transfer address and
>> 149 * bytes left to read so we can continue when the next
>> 150 * fast IRQ comes in.
>> 151 */
>> 152 floppy_fifo_emptied:
>> 153 sethi %hi(pdma_vaddr), %l5
>> 154 st %l4, [%l5 + %lo(pdma_vaddr)]
>> 155 sethi %hi(pdma_size), %l7
>> 156 st %l6, [%l7 + %lo(pdma_size)]
>> 157
>> 158 /* Restore condition codes */
>> 159 wr %l0, 0x0, %psr
>> 160 WRITE_PAUSE
>> 161
>> 162 jmp %l1
>> 163 rett %l2
>> 164
>> 165 floppy_overrun:
>> 166 sethi %hi(pdma_vaddr), %l5
>> 167 st %l4, [%l5 + %lo(pdma_vaddr)]
>> 168 sethi %hi(pdma_size), %l5
>> 169 st %l6, [%l5 + %lo(pdma_size)]
>> 170 /* Prevent recursion */
>> 171 sethi %hi(doing_pdma), %l7
>> 172 st %g0, [%l7 + %lo(doing_pdma)]
>> 173
>> 174 /* fall through... */
>> 175 floppy_dosoftint:
>> 176 rd %wim, %l3
>> 177 SAVE_ALL
>> 178
>> 179 /* Set all IRQs off. */
>> 180 or %l0, PSR_PIL, %l4
>> 181 wr %l4, 0x0, %psr
>> 182 WRITE_PAUSE
>> 183 wr %l4, PSR_ET, %psr
>> 184 WRITE_PAUSE
>> 185
>> 186 mov 11, %o0 ! floppy irq level (unused anyway)
>> 187 mov %g0, %o1 ! devid is not used in fast interrupts
>> 188 call sparc_floppy_irq
>> 189 add %sp, STACKFRAME_SZ, %o2 ! struct pt_regs *regs
429 190
430 l.sfeqi r4,0x26 !! 191 RESTORE_ALL
431 l.bf lhs !! 192
432 l.sfeqi r4,0x25 !! 193 #endif /* (CONFIG_BLK_DEV_FD) */
433 l.bf lhz <<
434 l.sfeqi r4,0x22 <<
435 l.bf lws <<
436 l.sfeqi r4,0x21 <<
437 l.bf lwz <<
438 l.sfeqi r4,0x37 <<
439 l.bf sh <<
440 l.sfeqi r4,0x35 <<
441 l.bf sw <<
442 l.nop <<
443 <<
444 1: l.j 1b /* I d <<
445 l.nop <<
446 <<
447 lhs: l.lbs r5,0(r2) <<
448 l.slli r5,r5,8 <<
449 l.lbz r6,1(r2) <<
450 l.or r5,r5,r6 <<
451 l.srli r4,r3,19 <<
452 l.andi r4,r4,0x7c <<
453 l.add r4,r4,r1 <<
454 l.j align_end <<
455 l.sw 0(r4),r5 <<
456 <<
457 lhz: l.lbz r5,0(r2) <<
458 l.slli r5,r5,8 <<
459 l.lbz r6,1(r2) <<
460 l.or r5,r5,r6 <<
461 l.srli r4,r3,19 <<
462 l.andi r4,r4,0x7c <<
463 l.add r4,r4,r1 <<
464 l.j align_end <<
465 l.sw 0(r4),r5 <<
466 <<
467 lws: l.lbs r5,0(r2) <<
468 l.slli r5,r5,24 <<
469 l.lbz r6,1(r2) <<
470 l.slli r6,r6,16 <<
471 l.or r5,r5,r6 <<
472 l.lbz r6,2(r2) <<
473 l.slli r6,r6,8 <<
474 l.or r5,r5,r6 <<
475 l.lbz r6,3(r2) <<
476 l.or r5,r5,r6 <<
477 l.srli r4,r3,19 <<
478 l.andi r4,r4,0x7c <<
479 l.add r4,r4,r1 <<
480 l.j align_end <<
481 l.sw 0(r4),r5 <<
482 <<
483 lwz: l.lbz r5,0(r2) <<
484 l.slli r5,r5,24 <<
485 l.lbz r6,1(r2) <<
486 l.slli r6,r6,16 <<
487 l.or r5,r5,r6 <<
488 l.lbz r6,2(r2) <<
489 l.slli r6,r6,8 <<
490 l.or r5,r5,r6 <<
491 l.lbz r6,3(r2) <<
492 l.or r5,r5,r6 <<
493 l.srli r4,r3,19 <<
494 l.andi r4,r4,0x7c <<
495 l.add r4,r4,r1 <<
496 l.j align_end <<
497 l.sw 0(r4),r5 <<
498 <<
499 sh: <<
500 l.srli r4,r3,9 <<
501 l.andi r4,r4,0x7c <<
502 l.add r4,r4,r1 <<
503 l.lwz r5,0(r4) <<
504 l.sb 1(r2),r5 <<
505 l.srli r5,r5,8 <<
506 l.j align_end <<
507 l.sb 0(r2),r5 <<
508 <<
509 sw: <<
510 l.srli r4,r3,9 <<
511 l.andi r4,r4,0x7c <<
512 l.add r4,r4,r1 <<
513 l.lwz r5,0(r4) <<
514 l.sb 3(r2),r5 <<
515 l.srli r5,r5,8 <<
516 l.sb 2(r2),r5 <<
517 l.srli r5,r5,8 <<
518 l.sb 1(r2),r5 <<
519 l.srli r5,r5,8 <<
520 l.j align_end <<
521 l.sb 0(r2),r5 <<
522 <<
523 align_end: <<
524 l.j _ret_from_intr <<
525 l.nop <<
526 #endif <<
527 194
528 /* ---[ 0x700: Illegal insn exception ]------- !! 195 /* Bad trap handler */
>> 196 .globl bad_trap_handler
>> 197 bad_trap_handler:
>> 198 SAVE_ALL
>> 199
>> 200 wr %l0, PSR_ET, %psr
>> 201 WRITE_PAUSE
>> 202
>> 203 add %sp, STACKFRAME_SZ, %o0 ! pt_regs
>> 204 call do_hw_interrupt
>> 205 mov %l7, %o1 ! trap number
529 206
530 EXCEPTION_ENTRY(_illegal_instruction_handler) !! 207 RESTORE_ALL
531 /* r4: EA of fault (set by EXCEPTION_H !! 208
532 l.jal do_illegal_instruction !! 209 /* For now all IRQ's not registered get sent here. handler_irq() will
533 l.addi r3,r1,0 /* pt_regs */ !! 210 * see if a routine is registered to handle this interrupt and if not
534 !! 211 * it will say so on the console.
535 l.j _ret_from_exception !! 212 */
536 l.nop <<
537 <<
538 /* ---[ 0x800: External interrupt exception ]- <<
539 <<
540 EXCEPTION_ENTRY(_external_irq_handler) <<
541 #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK <<
542 l.lwz r4,PT_SR(r1) // wer <<
543 l.andi r4,r4,SPR_SR_IEE <<
544 l.sfeqi r4,0 <<
545 l.bnf 1f // ext <<
546 l.nop <<
547 <<
548 #ifdef CONFIG_PRINTK <<
549 l.addi r1,r1,-0x8 <<
550 l.movhi r3,hi(42f) <<
551 l.ori r3,r3,lo(42f) <<
552 l.sw 0x0(r1),r3 <<
553 l.jal _printk <<
554 l.sw 0x4(r1),r4 <<
555 l.addi r1,r1,0x8 <<
556 <<
557 .section .rodata, "a" <<
558 42: <<
559 .string "\n\rESR interrupt bug <<
560 .align 4 <<
561 .previous <<
562 #endif <<
563 213
564 l.ori r4,r4,SPR_SR_IEE // fix !! 214 .align 4
565 // l.sw PT_SR(r1),r4 !! 215 .globl real_irq_entry, patch_handler_irq
566 1: !! 216 real_irq_entry:
>> 217 SAVE_ALL
>> 218
>> 219 #ifdef CONFIG_SMP
>> 220 .globl patchme_maybe_smp_msg
>> 221
>> 222 cmp %l7, 11
>> 223 patchme_maybe_smp_msg:
>> 224 bgu maybe_smp4m_msg
>> 225 nop
567 #endif 226 #endif
568 CLEAR_LWA_FLAG(r3) <<
569 l.addi r3,r1,0 <<
570 l.movhi r8,hi(generic_handle_arch_irq) <<
571 l.ori r8,r8,lo(generic_handle_arch_i <<
572 l.jalr r8 <<
573 l.nop <<
574 l.j _ret_from_intr <<
575 l.nop <<
576 <<
577 /* ---[ 0x900: DTLB miss exception ]---------- <<
578 <<
579 <<
580 /* ---[ 0xa00: ITLB miss exception ]---------- <<
581 <<
582 227
583 /* ---[ 0xb00: Range exception ]-------------- !! 228 real_irq_continue:
>> 229 or %l0, PSR_PIL, %g2
>> 230 wr %g2, 0x0, %psr
>> 231 WRITE_PAUSE
>> 232 wr %g2, PSR_ET, %psr
>> 233 WRITE_PAUSE
>> 234 mov %l7, %o0 ! irq level
>> 235 patch_handler_irq:
>> 236 call handler_irq
>> 237 add %sp, STACKFRAME_SZ, %o1 ! pt_regs ptr
>> 238 or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq
>> 239 wr %g2, PSR_ET, %psr ! keep ET up
>> 240 WRITE_PAUSE
584 241
585 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00) !! 242 RESTORE_ALL
586 243
587 /* ---[ 0xc00: Syscall exception ]------------ !! 244 #ifdef CONFIG_SMP
>> 245 /* SMP per-cpu ticker interrupts are handled specially. */
>> 246 smp4m_ticker:
>> 247 bne real_irq_continue+4
>> 248 or %l0, PSR_PIL, %g2
>> 249 wr %g2, 0x0, %psr
>> 250 WRITE_PAUSE
>> 251 wr %g2, PSR_ET, %psr
>> 252 WRITE_PAUSE
>> 253 call smp4m_percpu_timer_interrupt
>> 254 add %sp, STACKFRAME_SZ, %o0
>> 255 wr %l0, PSR_ET, %psr
>> 256 WRITE_PAUSE
>> 257 RESTORE_ALL
588 258
589 /* !! 259 #define GET_PROCESSOR4M_ID(reg) \
590 * Syscalls are a special type of exception in !! 260 rd %tbr, %reg; \
591 * _explicitly_ invoked by userspace and can t !! 261 srl %reg, 12, %reg; \
592 * held to conform to the same ABI as normal f !! 262 and %reg, 3, %reg;
593 * respect to whether registers are preserved !! 263
594 * or not. !! 264 /* Here is where we check for possible SMP IPI passed to us
595 */ !! 265 * on some level other than 15 which is the NMI and only used
>> 266 * for cross calls. That has a separate entry point below.
>> 267 *
>> 268 * IPIs are sent on Level 12, 13 and 14. See IRQ_IPI_*.
>> 269 */
>> 270 maybe_smp4m_msg:
>> 271 GET_PROCESSOR4M_ID(o3)
>> 272 sethi %hi(sun4m_irq_percpu), %l5
>> 273 sll %o3, 2, %o3
>> 274 or %l5, %lo(sun4m_irq_percpu), %o5
>> 275 sethi %hi(0x70000000), %o2 ! Check all soft-IRQs
>> 276 ld [%o5 + %o3], %o1
>> 277 ld [%o1 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
>> 278 andcc %o3, %o2, %g0
>> 279 be,a smp4m_ticker
>> 280 cmp %l7, 14
>> 281 /* Soft-IRQ IPI */
>> 282 st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x70000000
>> 283 WRITE_PAUSE
>> 284 ld [%o1 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
>> 285 WRITE_PAUSE
>> 286 or %l0, PSR_PIL, %l4
>> 287 wr %l4, 0x0, %psr
>> 288 WRITE_PAUSE
>> 289 wr %l4, PSR_ET, %psr
>> 290 WRITE_PAUSE
>> 291 srl %o3, 28, %o2 ! shift for simpler checks below
>> 292 maybe_smp4m_msg_check_single:
>> 293 andcc %o2, 0x1, %g0
>> 294 beq,a maybe_smp4m_msg_check_mask
>> 295 andcc %o2, 0x2, %g0
>> 296 call smp_call_function_single_interrupt
>> 297 nop
>> 298 andcc %o2, 0x2, %g0
>> 299 maybe_smp4m_msg_check_mask:
>> 300 beq,a maybe_smp4m_msg_check_resched
>> 301 andcc %o2, 0x4, %g0
>> 302 call smp_call_function_interrupt
>> 303 nop
>> 304 andcc %o2, 0x4, %g0
>> 305 maybe_smp4m_msg_check_resched:
>> 306 /* rescheduling is done in RESTORE_ALL regardless, but incr stats */
>> 307 beq,a maybe_smp4m_msg_out
>> 308 nop
>> 309 call smp_resched_interrupt
>> 310 nop
>> 311 maybe_smp4m_msg_out:
>> 312 RESTORE_ALL
596 313
597 /* Upon syscall entry we just save the callee- !! 314 .align 4
598 * and not the call-clobbered ones. !! 315 .globl linux_trap_ipi15_sun4m
599 */ !! 316 linux_trap_ipi15_sun4m:
>> 317 SAVE_ALL
>> 318 sethi %hi(0x80000000), %o2
>> 319 GET_PROCESSOR4M_ID(o0)
>> 320 sethi %hi(sun4m_irq_percpu), %l5
>> 321 or %l5, %lo(sun4m_irq_percpu), %o5
>> 322 sll %o0, 2, %o0
>> 323 ld [%o5 + %o0], %o5
>> 324 ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
>> 325 andcc %o3, %o2, %g0
>> 326 be sun4m_nmi_error ! Must be an NMI async memory error
>> 327 st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000
>> 328 WRITE_PAUSE
>> 329 ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
>> 330 WRITE_PAUSE
>> 331 or %l0, PSR_PIL, %l4
>> 332 wr %l4, 0x0, %psr
>> 333 WRITE_PAUSE
>> 334 wr %l4, PSR_ET, %psr
>> 335 WRITE_PAUSE
>> 336 call smp4m_cross_call_irq
>> 337 nop
>> 338 b ret_trap_lockless_ipi
>> 339 clr %l6
>> 340
>> 341 .globl smp4d_ticker
>> 342 /* SMP per-cpu ticker interrupts are handled specially. */
>> 343 smp4d_ticker:
>> 344 SAVE_ALL
>> 345 or %l0, PSR_PIL, %g2
>> 346 sethi %hi(CC_ICLR), %o0
>> 347 sethi %hi(1 << 14), %o1
>> 348 or %o0, %lo(CC_ICLR), %o0
>> 349 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 14 in MXCC's ICLR */
>> 350 wr %g2, 0x0, %psr
>> 351 WRITE_PAUSE
>> 352 wr %g2, PSR_ET, %psr
>> 353 WRITE_PAUSE
>> 354 call smp4d_percpu_timer_interrupt
>> 355 add %sp, STACKFRAME_SZ, %o0
>> 356 wr %l0, PSR_ET, %psr
>> 357 WRITE_PAUSE
>> 358 RESTORE_ALL
600 359
601 _string_syscall_return: !! 360 .align 4
602 .string "syscall r9:0x%08x -> syscall( !! 361 .globl linux_trap_ipi15_sun4d
603 .align 4 !! 362 linux_trap_ipi15_sun4d:
>> 363 SAVE_ALL
>> 364 sethi %hi(CC_BASE), %o4
>> 365 sethi %hi(MXCC_ERR_ME|MXCC_ERR_PEW|MXCC_ERR_ASE|MXCC_ERR_PEE), %o2
>> 366 or %o4, (CC_EREG - CC_BASE), %o0
>> 367 ldda [%o0] ASI_M_MXCC, %o0
>> 368 andcc %o0, %o2, %g0
>> 369 bne 1f
>> 370 sethi %hi(BB_STAT2), %o2
>> 371 lduba [%o2] ASI_M_CTL, %o2
>> 372 andcc %o2, BB_STAT2_MASK, %g0
>> 373 bne 2f
>> 374 or %o4, (CC_ICLR - CC_BASE), %o0
>> 375 sethi %hi(1 << 15), %o1
>> 376 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 15 in MXCC's ICLR */
>> 377 or %l0, PSR_PIL, %l4
>> 378 wr %l4, 0x0, %psr
>> 379 WRITE_PAUSE
>> 380 wr %l4, PSR_ET, %psr
>> 381 WRITE_PAUSE
>> 382 call smp4d_cross_call_irq
>> 383 nop
>> 384 b ret_trap_lockless_ipi
>> 385 clr %l6
>> 386
>> 387 1: /* MXCC error */
>> 388 2: /* BB error */
>> 389 /* Disable PIL 15 */
>> 390 set CC_IMSK, %l4
>> 391 lduha [%l4] ASI_M_MXCC, %l5
>> 392 sethi %hi(1 << 15), %l7
>> 393 or %l5, %l7, %l5
>> 394 stha %l5, [%l4] ASI_M_MXCC
>> 395 /* FIXME */
>> 396 1: b,a 1b
>> 397
>> 398 .globl smpleon_ipi
>> 399 .extern leon_ipi_interrupt
>> 400 /* SMP per-cpu IPI interrupts are handled specially. */
>> 401 smpleon_ipi:
>> 402 SAVE_ALL
>> 403 or %l0, PSR_PIL, %g2
>> 404 wr %g2, 0x0, %psr
>> 405 WRITE_PAUSE
>> 406 wr %g2, PSR_ET, %psr
>> 407 WRITE_PAUSE
>> 408 call leonsmp_ipi_interrupt
>> 409 add %sp, STACKFRAME_SZ, %o1 ! pt_regs
>> 410 wr %l0, PSR_ET, %psr
>> 411 WRITE_PAUSE
>> 412 RESTORE_ALL
604 413
605 ENTRY(_sys_call_handler) !! 414 .align 4
606 /* r1, EPCR, ESR a already saved */ !! 415 .globl linux_trap_ipi15_leon
607 l.sw PT_GPR2(r1),r2 !! 416 linux_trap_ipi15_leon:
608 /* r3-r8 must be saved because syscall !! 417 SAVE_ALL
609 * on us being able to restart the sys !! 418 or %l0, PSR_PIL, %l4
610 * they should be clobbered, otherwise !! 419 wr %l4, 0x0, %psr
611 */ !! 420 WRITE_PAUSE
612 l.sw PT_GPR3(r1),r3 !! 421 wr %l4, PSR_ET, %psr
613 /* !! 422 WRITE_PAUSE
614 * r4 already saved !! 423 call leon_cross_call_irq
615 * r4 holds the EEAR address of the fa !! 424 nop
616 * then load the original r4 !! 425 b ret_trap_lockless_ipi
617 */ !! 426 clr %l6
618 CLEAR_LWA_FLAG(r4) <<
619 l.lwz r4,PT_GPR4(r1) <<
620 l.sw PT_GPR5(r1),r5 <<
621 l.sw PT_GPR6(r1),r6 <<
622 l.sw PT_GPR7(r1),r7 <<
623 l.sw PT_GPR8(r1),r8 <<
624 l.sw PT_GPR9(r1),r9 <<
625 /* r10 already saved */ <<
626 l.sw PT_GPR11(r1),r11 <<
627 /* orig_gpr11 must be set for syscalls <<
628 l.sw PT_ORIG_GPR11(r1),r11 <<
629 /* r12,r13 already saved */ <<
630 <<
631 /* r14-r28 (even) aren't touched by th <<
632 * so we don't need to save them. How <<
633 * to userspace via a call to switch() <<
634 * switch() effectively clobbers them. <<
635 * such functions is handled in their <<
636 * and clone, below). <<
637 <<
638 /* r30 is the only register we clobber <<
639 /* r30 already saved */ <<
640 /* l.sw PT_GPR30(r1),r30 */ <<
641 <<
642 _syscall_check_trace_enter: <<
643 /* syscalls run with interrupts enable <<
644 TRACE_IRQS_ON_SYSCALL <<
645 ENABLE_INTERRUPTS(r29) // ena <<
646 <<
647 /* If TIF_SYSCALL_TRACE is set, then w <<
648 l.lwz r30,TI_FLAGS(r10) <<
649 l.andi r30,r30,_TIF_SYSCALL_TRACE <<
650 l.sfne r30,r0 <<
651 l.bf _syscall_trace_enter <<
652 l.nop <<
653 <<
654 _syscall_check: <<
655 /* Ensure that the syscall number is r <<
656 l.sfgeui r11,__NR_syscalls <<
657 l.bf _syscall_badsys <<
658 l.nop <<
659 <<
660 _syscall_call: <<
661 l.movhi r29,hi(sys_call_table) <<
662 l.ori r29,r29,lo(sys_call_table) <<
663 l.slli r11,r11,2 <<
664 l.add r29,r29,r11 <<
665 l.lwz r29,0(r29) <<
666 <<
667 l.jalr r29 <<
668 l.nop <<
669 <<
670 _syscall_return: <<
671 /* All syscalls return here... just pa <<
672 * which does it in a round-about way. <<
673 */ <<
674 l.sw PT_GPR11(r1),r11 // <<
675 427
676 #if 0 !! 428 #endif /* CONFIG_SMP */
677 _syscall_debug: <<
678 l.movhi r3,hi(_string_syscall_return) <<
679 l.ori r3,r3,lo(_string_syscall_retur <<
680 l.ori r27,r0,2 <<
681 l.sw -4(r1),r27 <<
682 l.sw -8(r1),r11 <<
683 l.lwz r29,PT_ORIG_GPR11(r1) <<
684 l.sw -12(r1),r29 <<
685 l.lwz r29,PT_GPR9(r1) <<
686 l.sw -16(r1),r29 <<
687 l.movhi r27,hi(_printk) <<
688 l.ori r27,r27,lo(_printk) <<
689 l.jalr r27 <<
690 l.addi r1,r1,-16 <<
691 l.addi r1,r1,16 <<
692 #endif <<
693 #if 0 <<
694 _syscall_show_regs: <<
695 l.movhi r27,hi(show_registers) <<
696 l.ori r27,r27,lo(show_registers) <<
697 l.jalr r27 <<
698 l.or r3,r1,r1 <<
699 #endif <<
700 429
701 _syscall_check_trace_leave: !! 430 /* This routine handles illegal instructions and privileged
702 /* r30 is a callee-saved register so t !! 431 * instruction attempts from user code.
703 * _TIF_SYSCALL_TRACE flag from _sysca <<
704 * _syscall_trace_leave expects syscal <<
705 */ 432 */
706 l.sfne r30,r0 !! 433 .align 4
707 l.bf _syscall_trace_leave !! 434 .globl bad_instruction
708 l.nop !! 435 bad_instruction:
709 !! 436 sethi %hi(0xc1f80000), %l4
710 /* This is where the exception-return code beg !! 437 ld [%l1], %l5
711 * disabled the rest of the way here because w !! 438 sethi %hi(0x81d80000), %l7
712 * interrupts that set NEED_RESCHED or SIGNALP !! 439 and %l5, %l4, %l5
713 !! 440 cmp %l5, %l7
714 _syscall_check_work: !! 441 be 1f
715 /* Here we need to disable interrupts !! 442 SAVE_ALL
716 DISABLE_INTERRUPTS(r27,r29) !! 443
717 TRACE_IRQS_OFF !! 444 wr %l0, PSR_ET, %psr ! re-enable traps
718 l.lwz r30,TI_FLAGS(r10) !! 445 WRITE_PAUSE
719 l.andi r30,r30,_TIF_WORK_MASK !! 446
720 l.sfne r30,r0 !! 447 add %sp, STACKFRAME_SZ, %o0
721 !! 448 mov %l1, %o1
722 l.bnf _syscall_resume_userspace !! 449 mov %l2, %o2
723 l.nop !! 450 call do_illegal_instruction
724 !! 451 mov %l0, %o3
725 /* Work pending follows a different re <<
726 * make sure that all the call-saved r <<
727 * before branching... <<
728 */ <<
729 l.sw PT_GPR14(r1),r14 <<
730 l.sw PT_GPR16(r1),r16 <<
731 l.sw PT_GPR18(r1),r18 <<
732 l.sw PT_GPR20(r1),r20 <<
733 l.sw PT_GPR22(r1),r22 <<
734 l.sw PT_GPR24(r1),r24 <<
735 l.sw PT_GPR26(r1),r26 <<
736 l.sw PT_GPR28(r1),r28 <<
737 <<
738 /* _work_pending needs to be called wi <<
739 l.j _work_pending <<
740 l.nop <<
741 <<
742 _syscall_resume_userspace: <<
743 // ENABLE_INTERRUPTS(r29) <<
744 <<
745 <<
746 /* This is the hot path for returning to users <<
747 * work to be done and the branch to _work_pen <<
748 * return to userspace will be done via the no <<
749 * that path restores _all_ registers and will <<
750 * registers with whatever garbage is in pt_re <<
751 * registers are clobbered anyway and because <<
752 * in the context of the extra work that _work <<
753 452
754 /* Once again, syscalls are special and only g !! 453 RESTORE_ALL
755 * same registers as a normal function call */ <<
756 454
757 /* The assumption here is that the registers r !! 455 1: /* unimplemented flush - just skip */
758 * don't need to be restored... be sure that t !! 456 jmpl %l2, %g0
759 */ !! 457 rett %l2 + 4
>> 458
>> 459 .align 4
>> 460 .globl priv_instruction
>> 461 priv_instruction:
>> 462 SAVE_ALL
>> 463
>> 464 wr %l0, PSR_ET, %psr
>> 465 WRITE_PAUSE
>> 466
>> 467 add %sp, STACKFRAME_SZ, %o0
>> 468 mov %l1, %o1
>> 469 mov %l2, %o2
>> 470 call do_priv_instruction
>> 471 mov %l0, %o3
760 472
761 /* This is still too much... we should only be !! 473 RESTORE_ALL
762 * clobbered... we should even be using 'scrat <<
763 * we don't need to restore anything, hardly.. <<
764 */ <<
765 474
766 l.lwz r2,PT_GPR2(r1) !! 475 /* This routine handles unaligned data accesses. */
>> 476 .align 4
>> 477 .globl mna_handler
>> 478 mna_handler:
>> 479 andcc %l0, PSR_PS, %g0
>> 480 be mna_fromuser
>> 481 nop
>> 482
>> 483 SAVE_ALL
>> 484
>> 485 wr %l0, PSR_ET, %psr
>> 486 WRITE_PAUSE
>> 487
>> 488 ld [%l1], %o1
>> 489 call kernel_unaligned_trap
>> 490 add %sp, STACKFRAME_SZ, %o0
767 491
768 /* Restore args */ !! 492 RESTORE_ALL
769 /* r3-r8 are technically clobbered, bu <<
770 * to be restored... <<
771 */ <<
772 l.lwz r3,PT_GPR3(r1) <<
773 l.lwz r4,PT_GPR4(r1) <<
774 l.lwz r5,PT_GPR5(r1) <<
775 l.lwz r6,PT_GPR6(r1) <<
776 l.lwz r7,PT_GPR7(r1) <<
777 l.lwz r8,PT_GPR8(r1) <<
778 <<
779 l.lwz r9,PT_GPR9(r1) <<
780 l.lwz r10,PT_GPR10(r1) <<
781 l.lwz r11,PT_GPR11(r1) <<
782 <<
783 /* r30 is the only register we clobber <<
784 l.lwz r30,PT_GPR30(r1) <<
785 <<
786 /* Here we use r13-r19 (odd) as scratc <<
787 l.lwz r13,PT_PC(r1) <<
788 l.lwz r15,PT_SR(r1) <<
789 l.lwz r1,PT_SP(r1) <<
790 /* Interrupts need to be disabled for <<
791 * so that another interrupt doesn't c <<
792 * them before we can use them for our <<
793 DISABLE_INTERRUPTS(r17,r19) <<
794 l.mtspr r0,r13,SPR_EPCR_BASE <<
795 l.mtspr r0,r15,SPR_ESR_BASE <<
796 l.rfe <<
797 <<
798 /* End of hot path! <<
799 * Keep the below tracing and error handling o <<
800 */ <<
801 <<
802 _syscall_trace_enter: <<
803 /* Here we pass pt_regs to do_syscall_ <<
804 * that function is really getting all <<
805 * pt_regs isn't a complete set of use <<
806 * ones relevant to the syscall... <<
807 * <<
808 * Note use of delay slot for setting <<
809 */ <<
810 l.jal do_syscall_trace_enter <<
811 l.addi r3,r1,0 <<
812 493
813 /* Restore arguments (not preserved ac !! 494 mna_fromuser:
814 * so that we can do the syscall for r !! 495 SAVE_ALL
815 * hot path. <<
816 */ <<
817 l.lwz r11,PT_GPR11(r1) <<
818 l.lwz r3,PT_GPR3(r1) <<
819 l.lwz r4,PT_GPR4(r1) <<
820 l.lwz r5,PT_GPR5(r1) <<
821 l.lwz r6,PT_GPR6(r1) <<
822 l.lwz r7,PT_GPR7(r1) <<
823 <<
824 l.j _syscall_check <<
825 l.lwz r8,PT_GPR8(r1) <<
826 <<
827 _syscall_trace_leave: <<
828 l.jal do_syscall_trace_leave <<
829 l.addi r3,r1,0 <<
830 <<
831 l.j _syscall_check_work <<
832 l.nop <<
833 <<
834 _syscall_badsys: <<
835 /* Here we effectively pretend to have <<
836 * syscall that returns -ENOSYS and th <<
837 * syscall hot path. <<
838 * Note that "return value" is set in <<
839 */ <<
840 l.j _syscall_return <<
841 l.addi r11,r0,-ENOSYS <<
842 496
843 /******* END SYSCALL HANDLING *******/ !! 497 wr %l0, PSR_ET, %psr ! re-enable traps
>> 498 WRITE_PAUSE
844 499
845 /* ---[ 0xd00: Floating Point exception ]----- !! 500 ld [%l1], %o1
>> 501 call user_unaligned_trap
>> 502 add %sp, STACKFRAME_SZ, %o0
846 503
847 EXCEPTION_ENTRY(_fpe_trap_handler) !! 504 RESTORE_ALL
848 CLEAR_LWA_FLAG(r3) <<
849 505
850 /* r4: EA of fault (set by EXCEPTION_H !! 506 /* This routine handles floating point disabled traps. */
851 l.jal do_fpe_trap !! 507 .align 4
852 l.addi r3,r1,0 /* pt_regs */ !! 508 .globl fpd_trap_handler
>> 509 fpd_trap_handler:
>> 510 SAVE_ALL
>> 511
>> 512 wr %l0, PSR_ET, %psr ! re-enable traps
>> 513 WRITE_PAUSE
>> 514
>> 515 add %sp, STACKFRAME_SZ, %o0
>> 516 mov %l1, %o1
>> 517 mov %l2, %o2
>> 518 call do_fpd_trap
>> 519 mov %l0, %o3
853 520
854 l.j _ret_from_exception !! 521 RESTORE_ALL
855 l.nop <<
856 522
857 /* ---[ 0xe00: Trap exception ]--------------- !! 523 /* This routine handles Floating Point Exceptions. */
>> 524 .align 4
>> 525 .globl fpe_trap_handler
>> 526 fpe_trap_handler:
>> 527 set fpsave_magic, %l5
>> 528 cmp %l1, %l5
>> 529 be 1f
>> 530 sethi %hi(fpsave), %l5
>> 531 or %l5, %lo(fpsave), %l5
>> 532 cmp %l1, %l5
>> 533 bne 2f
>> 534 sethi %hi(fpsave_catch2), %l5
>> 535 or %l5, %lo(fpsave_catch2), %l5
>> 536 wr %l0, 0x0, %psr
>> 537 WRITE_PAUSE
>> 538 jmp %l5
>> 539 rett %l5 + 4
>> 540 1:
>> 541 sethi %hi(fpsave_catch), %l5
>> 542 or %l5, %lo(fpsave_catch), %l5
>> 543 wr %l0, 0x0, %psr
>> 544 WRITE_PAUSE
>> 545 jmp %l5
>> 546 rett %l5 + 4
858 547
859 EXCEPTION_ENTRY(_trap_handler) !! 548 2:
860 CLEAR_LWA_FLAG(r3) !! 549 SAVE_ALL
861 /* r4: EA of fault (set by EXCEPTION_H <<
862 l.jal do_trap <<
863 l.addi r3,r1,0 /* pt_regs */ <<
864 550
865 l.j _ret_from_exception !! 551 wr %l0, PSR_ET, %psr ! re-enable traps
866 l.nop !! 552 WRITE_PAUSE
867 553
868 /* ---[ 0xf00: Reserved exception ]----------- !! 554 add %sp, STACKFRAME_SZ, %o0
>> 555 mov %l1, %o1
>> 556 mov %l2, %o2
>> 557 call do_fpe_trap
>> 558 mov %l0, %o3
869 559
870 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00) !! 560 RESTORE_ALL
871 561
872 /* ---[ 0x1000: Reserved exception ]---------- !! 562 /* This routine handles Tag Overflow Exceptions. */
>> 563 .align 4
>> 564 .globl do_tag_overflow
>> 565 do_tag_overflow:
>> 566 SAVE_ALL
>> 567
>> 568 wr %l0, PSR_ET, %psr ! re-enable traps
>> 569 WRITE_PAUSE
>> 570
>> 571 add %sp, STACKFRAME_SZ, %o0
>> 572 mov %l1, %o1
>> 573 mov %l2, %o2
>> 574 call handle_tag_overflow
>> 575 mov %l0, %o3
873 576
874 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000) !! 577 RESTORE_ALL
875 578
876 /* ---[ 0x1100: Reserved exception ]---------- !! 579 /* This routine handles Watchpoint Exceptions. */
>> 580 .align 4
>> 581 .globl do_watchpoint
>> 582 do_watchpoint:
>> 583 SAVE_ALL
>> 584
>> 585 wr %l0, PSR_ET, %psr ! re-enable traps
>> 586 WRITE_PAUSE
>> 587
>> 588 add %sp, STACKFRAME_SZ, %o0
>> 589 mov %l1, %o1
>> 590 mov %l2, %o2
>> 591 call handle_watchpoint
>> 592 mov %l0, %o3
877 593
878 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100) !! 594 RESTORE_ALL
879 595
880 /* ---[ 0x1200: Reserved exception ]---------- !! 596 /* This routine handles Register Access Exceptions. */
>> 597 .align 4
>> 598 .globl do_reg_access
>> 599 do_reg_access:
>> 600 SAVE_ALL
>> 601
>> 602 wr %l0, PSR_ET, %psr ! re-enable traps
>> 603 WRITE_PAUSE
>> 604
>> 605 add %sp, STACKFRAME_SZ, %o0
>> 606 mov %l1, %o1
>> 607 mov %l2, %o2
>> 608 call handle_reg_access
>> 609 mov %l0, %o3
881 610
882 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200) !! 611 RESTORE_ALL
883 612
884 /* ---[ 0x1300: Reserved exception ]---------- !! 613 /* This routine handles Co-Processor Disabled Exceptions. */
>> 614 .align 4
>> 615 .globl do_cp_disabled
>> 616 do_cp_disabled:
>> 617 SAVE_ALL
>> 618
>> 619 wr %l0, PSR_ET, %psr ! re-enable traps
>> 620 WRITE_PAUSE
>> 621
>> 622 add %sp, STACKFRAME_SZ, %o0
>> 623 mov %l1, %o1
>> 624 mov %l2, %o2
>> 625 call handle_cp_disabled
>> 626 mov %l0, %o3
885 627
886 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300) !! 628 RESTORE_ALL
887 629
888 /* ---[ 0x1400: Reserved exception ]---------- !! 630 /* This routine handles Co-Processor Exceptions. */
>> 631 .align 4
>> 632 .globl do_cp_exception
>> 633 do_cp_exception:
>> 634 SAVE_ALL
>> 635
>> 636 wr %l0, PSR_ET, %psr ! re-enable traps
>> 637 WRITE_PAUSE
>> 638
>> 639 add %sp, STACKFRAME_SZ, %o0
>> 640 mov %l1, %o1
>> 641 mov %l2, %o2
>> 642 call handle_cp_exception
>> 643 mov %l0, %o3
889 644
890 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400) !! 645 RESTORE_ALL
891 646
892 /* ---[ 0x1500: Reserved exception ]---------- !! 647 /* This routine handles Hardware Divide By Zero Exceptions. */
>> 648 .align 4
>> 649 .globl do_hw_divzero
>> 650 do_hw_divzero:
>> 651 SAVE_ALL
>> 652
>> 653 wr %l0, PSR_ET, %psr ! re-enable traps
>> 654 WRITE_PAUSE
>> 655
>> 656 add %sp, STACKFRAME_SZ, %o0
>> 657 mov %l1, %o1
>> 658 mov %l2, %o2
>> 659 call handle_hw_divzero
>> 660 mov %l0, %o3
893 661
894 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500) !! 662 RESTORE_ALL
895 663
896 /* ---[ 0x1600: Reserved exception ]---------- !! 664 .align 4
>> 665 .globl do_flush_windows
>> 666 do_flush_windows:
>> 667 SAVE_ALL
>> 668
>> 669 wr %l0, PSR_ET, %psr
>> 670 WRITE_PAUSE
>> 671
>> 672 andcc %l0, PSR_PS, %g0
>> 673 bne dfw_kernel
>> 674 nop
>> 675
>> 676 call flush_user_windows
>> 677 nop
>> 678
>> 679 /* Advance over the trap instruction. */
>> 680 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1
>> 681 add %l1, 0x4, %l2
>> 682 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 683 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
897 684
898 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600) !! 685 RESTORE_ALL
899 686
900 /* ---[ 0x1700: Reserved exception ]---------- !! 687 .globl flush_patch_one
901 688
902 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700) !! 689 /* We get these for debugging routines using __builtin_return_address() */
>> 690 dfw_kernel:
>> 691 flush_patch_one:
>> 692 FLUSH_ALL_KERNEL_WINDOWS
>> 693
>> 694 /* Advance over the trap instruction. */
>> 695 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1
>> 696 add %l1, 0x4, %l2
>> 697 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 698 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
903 699
904 /* ---[ 0x1800: Reserved exception ]---------- !! 700 RESTORE_ALL
905 701
906 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800) !! 702 /* The getcc software trap. The user wants the condition codes from
>> 703 * the %psr in register %g1.
>> 704 */
907 705
908 /* ---[ 0x1900: Reserved exception ]---------- !! 706 .align 4
>> 707 .globl getcc_trap_handler
>> 708 getcc_trap_handler:
>> 709 srl %l0, 20, %g1 ! give user
>> 710 and %g1, 0xf, %g1 ! only ICC bits in %psr
>> 711 jmp %l2 ! advance over trap instruction
>> 712 rett %l2 + 0x4 ! like this...
>> 713
>> 714 /* The setcc software trap. The user has condition codes in %g1
>> 715 * that it would like placed in the %psr. Be careful not to flip
>> 716 * any unintentional bits!
>> 717 */
909 718
910 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900) !! 719 .align 4
>> 720 .globl setcc_trap_handler
>> 721 setcc_trap_handler:
>> 722 sll %g1, 0x14, %l4
>> 723 set PSR_ICC, %l5
>> 724 andn %l0, %l5, %l0 ! clear ICC bits in %psr
>> 725 and %l4, %l5, %l4 ! clear non-ICC bits in user value
>> 726 or %l4, %l0, %l4 ! or them in... mix mix mix
>> 727
>> 728 wr %l4, 0x0, %psr ! set new %psr
>> 729 WRITE_PAUSE ! TI scumbags...
>> 730
>> 731 jmp %l2 ! advance over trap instruction
>> 732 rett %l2 + 0x4 ! like this...
>> 733
>> 734 sun4m_nmi_error:
>> 735 /* NMI async memory error handling. */
>> 736 sethi %hi(0x80000000), %l4
>> 737 sethi %hi(sun4m_irq_global), %o5
>> 738 ld [%o5 + %lo(sun4m_irq_global)], %l5
>> 739 st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000
>> 740 WRITE_PAUSE
>> 741 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
>> 742 WRITE_PAUSE
>> 743 or %l0, PSR_PIL, %l4
>> 744 wr %l4, 0x0, %psr
>> 745 WRITE_PAUSE
>> 746 wr %l4, PSR_ET, %psr
>> 747 WRITE_PAUSE
>> 748 call sun4m_nmi
>> 749 nop
>> 750 st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000
>> 751 WRITE_PAUSE
>> 752 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
>> 753 WRITE_PAUSE
>> 754 RESTORE_ALL
911 755
912 /* ---[ 0x1a00: Reserved exception ]---------- !! 756 #ifndef CONFIG_SMP
>> 757 .align 4
>> 758 .globl linux_trap_ipi15_sun4m
>> 759 linux_trap_ipi15_sun4m:
>> 760 SAVE_ALL
>> 761
>> 762 ba sun4m_nmi_error
>> 763 nop
>> 764 #endif /* CONFIG_SMP */
>> 765
>> 766 .align 4
>> 767 .globl srmmu_fault
>> 768 srmmu_fault:
>> 769 mov 0x400, %l5
>> 770 mov 0x300, %l4
>> 771
>> 772 LEON_PI(lda [%l5] ASI_LEON_MMUREGS, %l6) ! read sfar first
>> 773 SUN_PI_(lda [%l5] ASI_M_MMUREGS, %l6) ! read sfar first
>> 774
>> 775 LEON_PI(lda [%l4] ASI_LEON_MMUREGS, %l5) ! read sfsr last
>> 776 SUN_PI_(lda [%l4] ASI_M_MMUREGS, %l5) ! read sfsr last
>> 777
>> 778 andn %l6, 0xfff, %l6
>> 779 srl %l5, 6, %l5 ! and encode all info into l7
>> 780
>> 781 and %l5, 2, %l5
>> 782 or %l5, %l6, %l6
>> 783
>> 784 or %l6, %l7, %l7 ! l7 = [addr,write,txtfault]
>> 785
>> 786 SAVE_ALL
>> 787
>> 788 mov %l7, %o1
>> 789 mov %l7, %o2
>> 790 and %o1, 1, %o1 ! arg2 = text_faultp
>> 791 mov %l7, %o3
>> 792 and %o2, 2, %o2 ! arg3 = writep
>> 793 andn %o3, 0xfff, %o3 ! arg4 = faulting address
913 794
914 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00) !! 795 wr %l0, PSR_ET, %psr
>> 796 WRITE_PAUSE
915 797
916 /* ---[ 0x1b00: Reserved exception ]---------- !! 798 call do_sparc_fault
>> 799 add %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr
917 800
918 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00) !! 801 RESTORE_ALL
919 802
920 /* ---[ 0x1c00: Reserved exception ]---------- !! 803 .align 4
>> 804 sunos_execv:
>> 805 .globl sunos_execv
>> 806 b sys_execve
>> 807 clr %i2
>> 808
>> 809 .align 4
>> 810 .globl sys_sigstack
>> 811 sys_sigstack:
>> 812 mov %o7, %l5
>> 813 mov %fp, %o2
>> 814 call do_sys_sigstack
>> 815 mov %l5, %o7
>> 816
>> 817 .align 4
>> 818 .globl sys_sigreturn
>> 819 sys_sigreturn:
>> 820 call do_sigreturn
>> 821 add %sp, STACKFRAME_SZ, %o0
>> 822
>> 823 ld [%curptr + TI_FLAGS], %l5
>> 824 andcc %l5, _TIF_SYSCALL_TRACE, %g0
>> 825 be 1f
>> 826 nop
921 827
922 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00) !! 828 call syscall_trace
>> 829 mov 1, %o1
923 830
924 /* ---[ 0x1d00: Reserved exception ]---------- !! 831 1:
>> 832 /* We don't want to muck with user registers like a
>> 833 * normal syscall, just return.
>> 834 */
>> 835 RESTORE_ALL
925 836
926 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00) !! 837 .align 4
>> 838 .globl sys_rt_sigreturn
>> 839 sys_rt_sigreturn:
>> 840 call do_rt_sigreturn
>> 841 add %sp, STACKFRAME_SZ, %o0
>> 842
>> 843 ld [%curptr + TI_FLAGS], %l5
>> 844 andcc %l5, _TIF_SYSCALL_TRACE, %g0
>> 845 be 1f
>> 846 nop
>> 847
>> 848 add %sp, STACKFRAME_SZ, %o0
>> 849 call syscall_trace
>> 850 mov 1, %o1
927 851
928 /* ---[ 0x1e00: Reserved exception ]---------- !! 852 1:
>> 853 /* We are returning to a signal handler. */
>> 854 RESTORE_ALL
929 855
930 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00) !! 856 /* Now that we have a real sys_clone, sys_fork() is
>> 857 * implemented in terms of it. Our _real_ implementation
>> 858 * of SunOS vfork() will use sys_vfork().
>> 859 *
>> 860 * XXX These three should be consolidated into mostly shared
>> 861 * XXX code just like on sparc64... -DaveM
>> 862 */
>> 863 .align 4
>> 864 .globl sys_fork, flush_patch_two
>> 865 sys_fork:
>> 866 mov %o7, %l5
>> 867 flush_patch_two:
>> 868 FLUSH_ALL_KERNEL_WINDOWS;
>> 869 ld [%curptr + TI_TASK], %o4
>> 870 rd %psr, %g4
>> 871 WRITE_PAUSE
>> 872 rd %wim, %g5
>> 873 WRITE_PAUSE
>> 874 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
>> 875 add %sp, STACKFRAME_SZ, %o0
>> 876 call sparc_fork
>> 877 mov %l5, %o7
>> 878
>> 879 /* Whee, kernel threads! */
>> 880 .globl sys_clone, flush_patch_three
>> 881 sys_clone:
>> 882 mov %o7, %l5
>> 883 flush_patch_three:
>> 884 FLUSH_ALL_KERNEL_WINDOWS;
>> 885 ld [%curptr + TI_TASK], %o4
>> 886 rd %psr, %g4
>> 887 WRITE_PAUSE
>> 888 rd %wim, %g5
>> 889 WRITE_PAUSE
>> 890 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
>> 891 add %sp, STACKFRAME_SZ, %o0
>> 892 call sparc_clone
>> 893 mov %l5, %o7
>> 894
>> 895 /* Whee, real vfork! */
>> 896 .globl sys_vfork, flush_patch_four
>> 897 sys_vfork:
>> 898 flush_patch_four:
>> 899 FLUSH_ALL_KERNEL_WINDOWS;
>> 900 ld [%curptr + TI_TASK], %o4
>> 901 rd %psr, %g4
>> 902 WRITE_PAUSE
>> 903 rd %wim, %g5
>> 904 WRITE_PAUSE
>> 905 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
>> 906 sethi %hi(sparc_vfork), %l1
>> 907 jmpl %l1 + %lo(sparc_vfork), %g0
>> 908 add %sp, STACKFRAME_SZ, %o0
>> 909
>> 910 .align 4
>> 911 linux_sparc_ni_syscall:
>> 912 sethi %hi(sys_ni_syscall), %l7
>> 913 b do_syscall
>> 914 or %l7, %lo(sys_ni_syscall), %l7
>> 915
>> 916 linux_syscall_trace:
>> 917 add %sp, STACKFRAME_SZ, %o0
>> 918 call syscall_trace
>> 919 mov 0, %o1
>> 920 cmp %o0, 0
>> 921 bne 3f
>> 922 mov -ENOSYS, %o0
>> 923
>> 924 /* Syscall tracing can modify the registers. */
>> 925 ld [%sp + STACKFRAME_SZ + PT_G1], %g1
>> 926 sethi %hi(sys_call_table), %l7
>> 927 ld [%sp + STACKFRAME_SZ + PT_I0], %i0
>> 928 or %l7, %lo(sys_call_table), %l7
>> 929 ld [%sp + STACKFRAME_SZ + PT_I1], %i1
>> 930 ld [%sp + STACKFRAME_SZ + PT_I2], %i2
>> 931 ld [%sp + STACKFRAME_SZ + PT_I3], %i3
>> 932 ld [%sp + STACKFRAME_SZ + PT_I4], %i4
>> 933 ld [%sp + STACKFRAME_SZ + PT_I5], %i5
>> 934 cmp %g1, NR_syscalls
>> 935 bgeu 3f
>> 936 mov -ENOSYS, %o0
>> 937
>> 938 sll %g1, 2, %l4
>> 939 mov %i0, %o0
>> 940 ld [%l7 + %l4], %l7
>> 941 mov %i1, %o1
>> 942 mov %i2, %o2
>> 943 mov %i3, %o3
>> 944 b 2f
>> 945 mov %i4, %o4
>> 946
>> 947 .globl ret_from_fork
>> 948 ret_from_fork:
>> 949 call schedule_tail
>> 950 ld [%g3 + TI_TASK], %o0
>> 951 b ret_sys_call
>> 952 ld [%sp + STACKFRAME_SZ + PT_I0], %o0
>> 953
>> 954 .globl ret_from_kernel_thread
>> 955 ret_from_kernel_thread:
>> 956 call schedule_tail
>> 957 ld [%g3 + TI_TASK], %o0
>> 958 ld [%sp + STACKFRAME_SZ + PT_G1], %l0
>> 959 call %l0
>> 960 ld [%sp + STACKFRAME_SZ + PT_G2], %o0
>> 961 rd %psr, %l1
>> 962 ld [%sp + STACKFRAME_SZ + PT_PSR], %l0
>> 963 andn %l0, PSR_CWP, %l0
>> 964 nop
>> 965 and %l1, PSR_CWP, %l1
>> 966 or %l0, %l1, %l0
>> 967 st %l0, [%sp + STACKFRAME_SZ + PT_PSR]
>> 968 b ret_sys_call
>> 969 mov 0, %o0
>> 970
>> 971 /* Linux native system calls enter here... */
>> 972 .align 4
>> 973 .globl linux_sparc_syscall
>> 974 linux_sparc_syscall:
>> 975 sethi %hi(PSR_SYSCALL), %l4
>> 976 or %l0, %l4, %l0
>> 977 /* Direct access to user regs, must faster. */
>> 978 cmp %g1, NR_syscalls
>> 979 bgeu linux_sparc_ni_syscall
>> 980 sll %g1, 2, %l4
>> 981 ld [%l7 + %l4], %l7
>> 982
>> 983 do_syscall:
>> 984 SAVE_ALL_HEAD
>> 985 rd %wim, %l3
>> 986
>> 987 wr %l0, PSR_ET, %psr
>> 988 mov %i0, %o0
>> 989 mov %i1, %o1
>> 990 mov %i2, %o2
>> 991
>> 992 ld [%curptr + TI_FLAGS], %l5
>> 993 mov %i3, %o3
>> 994 andcc %l5, _TIF_SYSCALL_TRACE, %g0
>> 995 mov %i4, %o4
>> 996 bne linux_syscall_trace
>> 997 mov %i0, %l6
>> 998 2:
>> 999 call %l7
>> 1000 mov %i5, %o5
931 1001
932 /* ---[ 0x1f00: Reserved exception ]---------- !! 1002 3:
>> 1003 st %o0, [%sp + STACKFRAME_SZ + PT_I0]
933 1004
934 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00) !! 1005 ret_sys_call:
>> 1006 ld [%curptr + TI_FLAGS], %l5
>> 1007 cmp %o0, -ERESTART_RESTARTBLOCK
>> 1008 ld [%sp + STACKFRAME_SZ + PT_PSR], %g3
>> 1009 set PSR_C, %g2
>> 1010 bgeu 1f
>> 1011 andcc %l5, _TIF_SYSCALL_TRACE, %g0
>> 1012
>> 1013 /* System call success, clear Carry condition code. */
>> 1014 andn %g3, %g2, %g3
>> 1015 st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
>> 1016 bne linux_syscall_trace2
>> 1017 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */
>> 1018 add %l1, 0x4, %l2 /* npc = npc+4 */
>> 1019 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 1020 b ret_trap_entry
>> 1021 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
>> 1022 1:
>> 1023 /* System call failure, set Carry condition code.
>> 1024 * Also, get abs(errno) to return to the process.
>> 1025 */
>> 1026 sub %g0, %o0, %o0
>> 1027 or %g3, %g2, %g3
>> 1028 st %o0, [%sp + STACKFRAME_SZ + PT_I0]
>> 1029 st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
>> 1030 bne linux_syscall_trace2
>> 1031 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */
>> 1032 add %l1, 0x4, %l2 /* npc = npc+4 */
>> 1033 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 1034 b ret_trap_entry
>> 1035 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
>> 1036
>> 1037 linux_syscall_trace2:
>> 1038 add %sp, STACKFRAME_SZ, %o0
>> 1039 mov 1, %o1
>> 1040 call syscall_trace
>> 1041 add %l1, 0x4, %l2 /* npc = npc+4 */
>> 1042 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 1043 b ret_trap_entry
>> 1044 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
935 1045
936 /* =========================================== <<
937 1046
938 _resume_userspace: !! 1047 /* Saving and restoring the FPU state is best done from lowlevel code.
939 DISABLE_INTERRUPTS(r3,r4) !! 1048 *
940 TRACE_IRQS_OFF !! 1049 * void fpsave(unsigned long *fpregs, unsigned long *fsr,
941 l.lwz r4,TI_FLAGS(r10) !! 1050 * void *fpqueue, unsigned long *fpqdepth)
942 l.andi r13,r4,_TIF_WORK_MASK !! 1051 */
943 l.sfeqi r13,0 <<
944 l.bf _restore_all <<
945 l.nop <<
946 1052
947 _work_pending: !! 1053 .globl fpsave
948 l.lwz r5,PT_ORIG_GPR11(r1) !! 1054 fpsave:
949 l.sfltsi r5,0 !! 1055 st %fsr, [%o1] ! this can trap on us if fpu is in bogon state
950 l.bnf 1f !! 1056 ld [%o1], %g1
951 l.nop !! 1057 set 0x2000, %g4
952 l.andi r5,r5,0 !! 1058 andcc %g1, %g4, %g0
953 1: !! 1059 be 2f
954 l.jal do_work_pending !! 1060 mov 0, %g2
955 l.ori r3,r1,0 /* pt_ <<
956 1061
957 l.sfeqi r11,0 !! 1062 /* We have an fpqueue to save. */
958 l.bf _restore_all <<
959 l.nop <<
960 l.sfltsi r11,0 <<
961 l.bnf 1f <<
962 l.nop <<
963 l.and r11,r11,r0 <<
964 l.ori r11,r11,__NR_restart_syscall <<
965 l.j _syscall_check_trace_enter <<
966 l.nop <<
967 1: 1063 1:
968 l.lwz r11,PT_ORIG_GPR11(r1) !! 1064 std %fq, [%o2]
969 /* Restore arg registers */ !! 1065 fpsave_magic:
970 l.lwz r3,PT_GPR3(r1) !! 1066 st %fsr, [%o1]
971 l.lwz r4,PT_GPR4(r1) !! 1067 ld [%o1], %g3
972 l.lwz r5,PT_GPR5(r1) !! 1068 andcc %g3, %g4, %g0
973 l.lwz r6,PT_GPR6(r1) !! 1069 add %g2, 1, %g2
974 l.lwz r7,PT_GPR7(r1) !! 1070 bne 1b
975 l.j _syscall_check_trace_enter !! 1071 add %o2, 8, %o2
976 l.lwz r8,PT_GPR8(r1) <<
977 <<
978 _restore_all: <<
979 #ifdef CONFIG_TRACE_IRQFLAGS <<
980 l.lwz r4,PT_SR(r1) <<
981 l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE) <<
982 l.sfeq r3,r0 /* skip trace <<
983 l.bf skip_hardirqs_on <<
984 l.nop <<
985 TRACE_IRQS_ON <<
986 skip_hardirqs_on: <<
987 #endif <<
988 RESTORE_ALL <<
989 /* This returns to userspace code */ <<
990 1072
>> 1073 2:
>> 1074 st %g2, [%o3]
991 1075
992 ENTRY(_ret_from_intr) !! 1076 std %f0, [%o0 + 0x00]
993 ENTRY(_ret_from_exception) !! 1077 std %f2, [%o0 + 0x08]
994 l.lwz r4,PT_SR(r1) !! 1078 std %f4, [%o0 + 0x10]
995 l.andi r3,r4,SPR_SR_SM !! 1079 std %f6, [%o0 + 0x18]
996 l.sfeqi r3,0 !! 1080 std %f8, [%o0 + 0x20]
997 l.bnf _restore_all !! 1081 std %f10, [%o0 + 0x28]
998 l.nop !! 1082 std %f12, [%o0 + 0x30]
999 l.j _resume_userspace !! 1083 std %f14, [%o0 + 0x38]
1000 l.nop !! 1084 std %f16, [%o0 + 0x40]
1001 !! 1085 std %f18, [%o0 + 0x48]
1002 ENTRY(ret_from_fork) !! 1086 std %f20, [%o0 + 0x50]
1003 l.jal schedule_tail !! 1087 std %f22, [%o0 + 0x58]
1004 l.nop !! 1088 std %f24, [%o0 + 0x60]
1005 !! 1089 std %f26, [%o0 + 0x68]
1006 /* Check if we are a kernel thread */ !! 1090 std %f28, [%o0 + 0x70]
1007 l.sfeqi r20,0 !! 1091 retl
1008 l.bf 1f !! 1092 std %f30, [%o0 + 0x78]
1009 l.nop !! 1093
1010 !! 1094 /* Thanks for Theo Deraadt and the authors of the Sprite/netbsd/openbsd
1011 /* ...we are a kernel thread so invok !! 1095 * code for pointing out this possible deadlock, while we save state
1012 l.jalr r20 !! 1096 * above we could trap on the fsr store so our low level fpu trap
1013 l.or r3,r22,r0 !! 1097 * code has to know how to deal with this.
>> 1098 */
>> 1099 fpsave_catch:
>> 1100 b fpsave_magic + 4
>> 1101 st %fsr, [%o1]
>> 1102
>> 1103 fpsave_catch2:
>> 1104 b fpsave + 4
>> 1105 st %fsr, [%o1]
>> 1106
>> 1107 /* void fpload(unsigned long *fpregs, unsigned long *fsr); */
>> 1108
>> 1109 .globl fpload
>> 1110 fpload:
>> 1111 ldd [%o0 + 0x00], %f0
>> 1112 ldd [%o0 + 0x08], %f2
>> 1113 ldd [%o0 + 0x10], %f4
>> 1114 ldd [%o0 + 0x18], %f6
>> 1115 ldd [%o0 + 0x20], %f8
>> 1116 ldd [%o0 + 0x28], %f10
>> 1117 ldd [%o0 + 0x30], %f12
>> 1118 ldd [%o0 + 0x38], %f14
>> 1119 ldd [%o0 + 0x40], %f16
>> 1120 ldd [%o0 + 0x48], %f18
>> 1121 ldd [%o0 + 0x50], %f20
>> 1122 ldd [%o0 + 0x58], %f22
>> 1123 ldd [%o0 + 0x60], %f24
>> 1124 ldd [%o0 + 0x68], %f26
>> 1125 ldd [%o0 + 0x70], %f28
>> 1126 ldd [%o0 + 0x78], %f30
>> 1127 ld [%o1], %fsr
>> 1128 retl
>> 1129 nop
>> 1130
>> 1131 /* __ndelay and __udelay take two arguments:
>> 1132 * 0 - nsecs or usecs to delay
>> 1133 * 1 - per_cpu udelay_val (loops per jiffy)
>> 1134 *
>> 1135 * Note that ndelay gives HZ times higher resolution but has a 10ms
>> 1136 * limit. udelay can handle up to 1s.
>> 1137 */
>> 1138 .globl __ndelay
>> 1139 __ndelay:
>> 1140 save %sp, -STACKFRAME_SZ, %sp
>> 1141 mov %i0, %o0 ! round multiplier up so large ns ok
>> 1142 mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ)
>> 1143 umul %o0, %o1, %o0
>> 1144 rd %y, %o1
>> 1145 mov %i1, %o1 ! udelay_val
>> 1146 umul %o0, %o1, %o0
>> 1147 rd %y, %o1
>> 1148 ba delay_continue
>> 1149 mov %o1, %o0 ! >>32 later for better resolution
>> 1150
>> 1151 .globl __udelay
>> 1152 __udelay:
>> 1153 save %sp, -STACKFRAME_SZ, %sp
>> 1154 mov %i0, %o0
>> 1155 sethi %hi(0x10c7), %o1 ! round multiplier up so large us ok
>> 1156 or %o1, %lo(0x10c7), %o1 ! 2**32 / 1 000 000
>> 1157 umul %o0, %o1, %o0
>> 1158 rd %y, %o1
>> 1159 mov %i1, %o1 ! udelay_val
>> 1160 umul %o0, %o1, %o0
>> 1161 rd %y, %o1
>> 1162 sethi %hi(0x028f4b62), %l0 ! Add in rounding constant * 2**32,
>> 1163 or %g0, %lo(0x028f4b62), %l0
>> 1164 addcc %o0, %l0, %o0 ! 2**32 * 0.009 999
>> 1165 bcs,a 3f
>> 1166 add %o1, 0x01, %o1
>> 1167 3:
>> 1168 mov HZ, %o0 ! >>32 earlier for wider range
>> 1169 umul %o0, %o1, %o0
>> 1170 rd %y, %o1
1014 1171
>> 1172 delay_continue:
>> 1173 cmp %o0, 0x0
1015 1: 1174 1:
1016 /* _syscall_returns expect r11 to con !! 1175 bne 1b
1017 l.lwz r11,PT_GPR11(r1) !! 1176 subcc %o0, 1, %o0
>> 1177
>> 1178 ret
>> 1179 restore
>> 1180 EXPORT_SYMBOL(__udelay)
>> 1181 EXPORT_SYMBOL(__ndelay)
1018 1182
1019 /* The syscall fast path return expec !! 1183 /* Handle a software breakpoint */
1020 * r14-r28 to be untouched, so we res !! 1184 /* We have to inform parent that child has stopped */
1021 * will have been effectively clobber !! 1185 .align 4
1022 * via the call to switch() !! 1186 .globl breakpoint_trap
1023 */ !! 1187 breakpoint_trap:
1024 l.lwz r14,PT_GPR14(r1) !! 1188 rd %wim,%l3
1025 l.lwz r16,PT_GPR16(r1) !! 1189 SAVE_ALL
1026 l.lwz r18,PT_GPR18(r1) !! 1190 wr %l0, PSR_ET, %psr
1027 l.lwz r20,PT_GPR20(r1) !! 1191 WRITE_PAUSE
1028 l.lwz r22,PT_GPR22(r1) !! 1192
1029 l.lwz r24,PT_GPR24(r1) !! 1193 st %i0, [%sp + STACKFRAME_SZ + PT_G0] ! for restarting syscalls
1030 l.lwz r26,PT_GPR26(r1) !! 1194 call sparc_breakpoint
1031 l.lwz r28,PT_GPR28(r1) !! 1195 add %sp, STACKFRAME_SZ, %o0
1032 <<
1033 l.j _syscall_return <<
1034 l.nop <<
1035 <<
1036 /* ========================================== <<
1037 <<
1038 /* <<
1039 * This routine switches between two differen <<
1040 * state of one is saved on its kernel stack. <<
1041 * of the other is restored from its kernel s <<
1042 * management hardware is updated to the seco <<
1043 * Finally, we can return to the second proce <<
1044 * <<
1045 * Note: there are two ways to get to the "go <<
1046 * of this code; either by coming in via the <<
1047 * or via "fork" which must set up an environ <<
1048 * to the "_switch" path. If you change this <<
1049 * SAVE_REGS macro), you'll have to change th <<
1050 */ <<
1051 1196
>> 1197 RESTORE_ALL
1052 1198
1053 /* _switch MUST never lay on page boundry, ca !! 1199 #ifdef CONFIG_KGDB
1054 * effective addresses and beeing interrupted !! 1200 ENTRY(kgdb_trap_low)
1055 * dTLB miss seems to never accour in the bad !! 1201 rd %wim,%l3
1056 * are from task structures which are always !! 1202 SAVE_ALL
1057 * !! 1203 wr %l0, PSR_ET, %psr
1058 * The problem happens in RESTORE_ALL where w !! 1204 WRITE_PAUSE
1059 * register, then load the previous register !! 1205
1060 * the l.rfe instruction. If get TLB miss in !! 1206 mov %l7, %o0 ! trap_level
1061 * garbled and we end up calling l.rfe with t !! 1207 call kgdb_trap
1062 * holds for ESR) !! 1208 add %sp, STACKFRAME_SZ, %o1 ! struct pt_regs *regs
1063 * <<
1064 * To avoid this problems it is sufficient to <<
1065 * some nice round number smaller than it's s <<
1066 */ <<
1067 1209
1068 /* ABI rules apply here... we either enter _s !! 1210 RESTORE_ALL
1069 * an imaginary call to which we shall return !! 1211 ENDPROC(kgdb_trap_low)
1070 * way, we are a function call and only need !! 1212 #endif
1071 * registers when we return. As such, we don <<
1072 * on the stack that we won't be returning as <<
1073 */ <<
1074 1213
1075 .align 0x400 !! 1214 .align 4
1076 ENTRY(_switch) !! 1215 .globl flush_patch_exception
1077 /* We don't store SR as _switch only !! 1216 flush_patch_exception:
1078 * the SR will be the same going in a !! 1217 FLUSH_ALL_KERNEL_WINDOWS;
1079 !! 1218 ldd [%o0], %o6
1080 /* Set up new pt_regs struct for savi !! 1219 jmpl %o7 + 0xc, %g0 ! see asm-sparc/processor.h
1081 l.addi r1,r1,-(INT_FRAME_SIZE) !! 1220 mov 1, %g1 ! signal EFAULT condition
1082 !! 1221
1083 /* No need to store r1/PT_SP as it go !! 1222 .align 4
1084 l.sw PT_GPR2(r1),r2 !! 1223 .globl kill_user_windows, kuw_patch1_7win
1085 l.sw PT_GPR9(r1),r9 !! 1224 .globl kuw_patch1
1086 !! 1225 kuw_patch1_7win: sll %o3, 6, %o3
1087 /* Save callee-saved registers to the !! 1226
1088 l.sw PT_GPR14(r1),r14 !! 1227 /* No matter how much overhead this routine has in the worst
1089 l.sw PT_GPR16(r1),r16 !! 1228 * case scenario, it is several times better than taking the
1090 l.sw PT_GPR18(r1),r18 !! 1229 * traps with the old method of just doing flush_user_windows().
1091 l.sw PT_GPR20(r1),r20 <<
1092 l.sw PT_GPR22(r1),r22 <<
1093 l.sw PT_GPR24(r1),r24 <<
1094 l.sw PT_GPR26(r1),r26 <<
1095 l.sw PT_GPR28(r1),r28 <<
1096 l.sw PT_GPR30(r1),r30 <<
1097 <<
1098 l.addi r11,r10,0 <<
1099 <<
1100 /* We use thread_info->ksp for storin <<
1101 * structure so that we can get back <<
1102 * to lose the value of thread_info-> <<
1103 * pt_regs->sp so that we can easily <<
1104 * live again... <<
1105 */ 1230 */
>> 1231 kill_user_windows:
>> 1232 ld [%g6 + TI_UWINMASK], %o0 ! get current umask
>> 1233 orcc %g0, %o0, %g0 ! if no bits set, we are done
>> 1234 be 3f ! nothing to do
>> 1235 rd %psr, %o5 ! must clear interrupts
>> 1236 or %o5, PSR_PIL, %o4 ! or else that could change
>> 1237 wr %o4, 0x0, %psr ! the uwinmask state
>> 1238 WRITE_PAUSE ! burn them cycles
>> 1239 1:
>> 1240 ld [%g6 + TI_UWINMASK], %o0 ! get consistent state
>> 1241 orcc %g0, %o0, %g0 ! did an interrupt come in?
>> 1242 be 4f ! yep, we are done
>> 1243 rd %wim, %o3 ! get current wim
>> 1244 srl %o3, 1, %o4 ! simulate a save
>> 1245 kuw_patch1:
>> 1246 sll %o3, 7, %o3 ! compute next wim
>> 1247 or %o4, %o3, %o3 ! result
>> 1248 andncc %o0, %o3, %o0 ! clean this bit in umask
>> 1249 bne kuw_patch1 ! not done yet
>> 1250 srl %o3, 1, %o4 ! begin another save simulation
>> 1251 wr %o3, 0x0, %wim ! set the new wim
>> 1252 st %g0, [%g6 + TI_UWINMASK] ! clear uwinmask
>> 1253 4:
>> 1254 wr %o5, 0x0, %psr ! re-enable interrupts
>> 1255 WRITE_PAUSE ! burn baby burn
>> 1256 3:
>> 1257 retl ! return
>> 1258 st %g0, [%g6 + TI_W_SAVED] ! no windows saved
>> 1259
>> 1260 .align 4
>> 1261 .globl restore_current
>> 1262 restore_current:
>> 1263 LOAD_CURRENT(g6, o0)
>> 1264 retl
>> 1265 nop
>> 1266
>> 1267 #ifdef CONFIG_PCIC_PCI
>> 1268 #include <asm/pcic.h>
>> 1269
>> 1270 .align 4
>> 1271 .globl linux_trap_ipi15_pcic
>> 1272 linux_trap_ipi15_pcic:
>> 1273 rd %wim, %l3
>> 1274 SAVE_ALL
1106 1275
1107 /* Save the old value of thread_info- !! 1276 /*
1108 l.lwz r29,TI_KSP(r10) !! 1277 * First deactivate NMI
1109 l.sw PT_SP(r1),r29 !! 1278 * or we cannot drop ET, cannot get window spill traps.
1110 !! 1279 * The busy loop is necessary because the PIO error
1111 /* Swap kernel stack pointers */ !! 1280 * sometimes does not go away quickly and we trap again.
1112 l.sw TI_KSP(r10),r1 <<
1113 l.or r10,r4,r0 <<
1114 l.lwz r1,TI_KSP(r10) <<
1115 <<
1116 /* Restore the old value of thread_in <<
1117 l.lwz r29,PT_SP(r1) <<
1118 l.sw TI_KSP(r10),r29 <<
1119 <<
1120 /* ...and restore the registers, exce <<
1121 * has already been set above. <<
1122 */ <<
1123 l.lwz r2,PT_GPR2(r1) <<
1124 l.lwz r9,PT_GPR9(r1) <<
1125 /* No need to restore r10 */ <<
1126 /* ...and do not restore r11 */ <<
1127 <<
1128 /* Restore callee-saved registers */ <<
1129 l.lwz r14,PT_GPR14(r1) <<
1130 l.lwz r16,PT_GPR16(r1) <<
1131 l.lwz r18,PT_GPR18(r1) <<
1132 l.lwz r20,PT_GPR20(r1) <<
1133 l.lwz r22,PT_GPR22(r1) <<
1134 l.lwz r24,PT_GPR24(r1) <<
1135 l.lwz r26,PT_GPR26(r1) <<
1136 l.lwz r28,PT_GPR28(r1) <<
1137 l.lwz r30,PT_GPR30(r1) <<
1138 <<
1139 /* Unwind stack to pre-switch state * <<
1140 l.addi r1,r1,(INT_FRAME_SIZE) <<
1141 <<
1142 /* Return via the link-register back <<
1143 * that may be either schedule(), ret <<
1144 * ret_from_kernel_thread(). If we a <<
1145 * we are expected to have set up the <<
1146 * hence we do so here unconditionall <<
1147 */ 1281 */
1148 l.lwz r3,TI_TASK(r3) /* Lo !! 1282 sethi %hi(pcic_regs), %o1
1149 l.jr r9 !! 1283 ld [%o1 + %lo(pcic_regs)], %o2
1150 l.nop <<
1151 <<
1152 /* ========================================== <<
1153 1284
1154 /* These all use the delay slot for setting t !! 1285 ! Get pending status for printouts later.
1155 * jump is always happening after the l.addi !! 1286 ld [%o2 + PCI_SYS_INT_PENDING], %o0
1156 * <<
1157 * These are all just wrappers that don't tou <<
1158 * return from the "real" syscall function wi <<
1159 * code that did the l.jal that brought us he <<
1160 */ <<
1161 1287
1162 /* fork requires that we save all the callee- !! 1288 mov PCI_SYS_INT_PENDING_CLEAR_ALL, %o1
1163 * are all effectively clobbered by the call !! 1289 stb %o1, [%o2 + PCI_SYS_INT_PENDING_CLEAR]
1164 * all the registers that aren't touched by t !! 1290 1:
1165 * weren't saved there. !! 1291 ld [%o2 + PCI_SYS_INT_PENDING], %o1
1166 */ !! 1292 andcc %o1, ((PCI_SYS_INT_PENDING_PIO|PCI_SYS_INT_PENDING_PCI)>>24), %g0
>> 1293 bne 1b
>> 1294 nop
>> 1295
>> 1296 or %l0, PSR_PIL, %l4
>> 1297 wr %l4, 0x0, %psr
>> 1298 WRITE_PAUSE
>> 1299 wr %l4, PSR_ET, %psr
>> 1300 WRITE_PAUSE
1167 1301
1168 _fork_save_extra_regs_and_call: !! 1302 call pcic_nmi
1169 l.sw PT_GPR14(r1),r14 !! 1303 add %sp, STACKFRAME_SZ, %o1 ! struct pt_regs *regs
1170 l.sw PT_GPR16(r1),r16 !! 1304 RESTORE_ALL
1171 l.sw PT_GPR18(r1),r18 <<
1172 l.sw PT_GPR20(r1),r20 <<
1173 l.sw PT_GPR22(r1),r22 <<
1174 l.sw PT_GPR24(r1),r24 <<
1175 l.sw PT_GPR26(r1),r26 <<
1176 l.jr r29 <<
1177 l.sw PT_GPR28(r1),r28 <<
1178 <<
1179 ENTRY(__sys_clone) <<
1180 l.movhi r29,hi(sys_clone) <<
1181 l.j _fork_save_extra_regs_and_cal <<
1182 l.ori r29,r29,lo(sys_clone) <<
1183 <<
1184 ENTRY(__sys_clone3) <<
1185 l.movhi r29,hi(sys_clone3) <<
1186 l.j _fork_save_extra_regs_and_cal <<
1187 l.ori r29,r29,lo(sys_clone3) <<
1188 <<
1189 ENTRY(__sys_fork) <<
1190 l.movhi r29,hi(sys_fork) <<
1191 l.j _fork_save_extra_regs_and_cal <<
1192 l.ori r29,r29,lo(sys_fork) <<
1193 <<
1194 ENTRY(sys_rt_sigreturn) <<
1195 l.jal _sys_rt_sigreturn <<
1196 l.addi r3,r1,0 <<
1197 l.sfne r30,r0 <<
1198 l.bnf _no_syscall_trace <<
1199 l.nop <<
1200 l.jal do_syscall_trace_leave <<
1201 l.addi r3,r1,0 <<
1202 _no_syscall_trace: <<
1203 l.j _resume_userspace <<
1204 l.nop <<
1205 <<
1206 /* This is a catch-all syscall for atomic ins <<
1207 * The functions takes a variable number of p <<
1208 * particular flavour of atomic you want... p <<
1209 * the atomic in question. Currently, this f <<
1210 * following variants: <<
1211 * <<
1212 * XCHG: <<
1213 * @flag: 1 <<
1214 * @ptr1: <<
1215 * @ptr2: <<
1216 * Atomically exchange the values in pointers <<
1217 * <<
1218 */ <<
1219 1305
1220 ENTRY(sys_or1k_atomic) !! 1306 .globl pcic_nmi_trap_patch
1221 /* FIXME: This ignores r3 and always !! 1307 pcic_nmi_trap_patch:
1222 DISABLE_INTERRUPTS(r17,r19) !! 1308 sethi %hi(linux_trap_ipi15_pcic), %l3
1223 l.lwz r29,0(r4) !! 1309 jmpl %l3 + %lo(linux_trap_ipi15_pcic), %g0
1224 l.lwz r27,0(r5) !! 1310 rd %psr, %l0
1225 l.sw 0(r4),r27 !! 1311 .word 0
1226 l.sw 0(r5),r29 !! 1312
1227 ENABLE_INTERRUPTS(r17) !! 1313 #endif /* CONFIG_PCIC_PCI */
1228 l.jr r9 !! 1314
1229 l.or r11,r0,r0 !! 1315 .globl flushw_all
>> 1316 flushw_all:
>> 1317 save %sp, -0x40, %sp
>> 1318 save %sp, -0x40, %sp
>> 1319 save %sp, -0x40, %sp
>> 1320 save %sp, -0x40, %sp
>> 1321 save %sp, -0x40, %sp
>> 1322 save %sp, -0x40, %sp
>> 1323 save %sp, -0x40, %sp
>> 1324 restore
>> 1325 restore
>> 1326 restore
>> 1327 restore
>> 1328 restore
>> 1329 restore
>> 1330 ret
>> 1331 restore
>> 1332
>> 1333 #ifdef CONFIG_SMP
>> 1334 ENTRY(hard_smp_processor_id)
>> 1335 661: rd %tbr, %g1
>> 1336 srl %g1, 12, %o0
>> 1337 and %o0, 3, %o0
>> 1338 .section .cpuid_patch, "ax"
>> 1339 /* Instruction location. */
>> 1340 .word 661b
>> 1341 /* SUN4D implementation. */
>> 1342 lda [%g0] ASI_M_VIKING_TMP1, %o0
>> 1343 nop
>> 1344 nop
>> 1345 /* LEON implementation. */
>> 1346 rd %asr17, %o0
>> 1347 srl %o0, 0x1c, %o0
>> 1348 nop
>> 1349 .previous
>> 1350 retl
>> 1351 nop
>> 1352 ENDPROC(hard_smp_processor_id)
>> 1353 #endif
1230 1354
1231 /* ========================================== !! 1355 /* End of entry.S */
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