1 /* SPDX-License-Identifier: GPL-2.0-or-later * !! 1 /* ld script for sparc32/sparc64 kernel */
2 /* <<
3 * OpenRISC vmlinux.lds.S <<
4 * <<
5 * Linux architectural port borrowing liberall <<
6 * others. All original copyrights apply as p <<
7 * declaration. <<
8 * <<
9 * Modifications for the OpenRISC architecture <<
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@ <<
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@so <<
12 * <<
13 * ld script for OpenRISC architecture <<
14 */ <<
15 <<
16 /* TODO <<
17 * - clean up __offset & stuff <<
18 * - change all 8192 alignment to <<
19 * - recheck if all alignments ar <<
20 */ <<
21 2
22 # define LOAD_OFFSET PAGE_OFFSET !! 3 #include <asm-generic/vmlinux.lds.h>
23 # define LOAD_BASE PAGE_OFFSET <<
24 4
25 #include <asm/page.h> 5 #include <asm/page.h>
26 #include <asm/cache.h> <<
27 #include <asm/thread_info.h> 6 #include <asm/thread_info.h>
28 #include <asm-generic/vmlinux.lds.h> <<
29 7
30 #ifdef __OR1K__ !! 8 #ifdef CONFIG_SPARC32
31 #define __OUTPUT_FORMAT "elf32-or1k" !! 9 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEADERS
>> 10 #define TEXTSTART 0xf0004000
>> 11
>> 12 #define SMP_CACHE_BYTES_SHIFT 5
>> 13
32 #else 14 #else
33 #define __OUTPUT_FORMAT "elf32-or32" !! 15 #define SMP_CACHE_BYTES_SHIFT 6
>> 16 #define INITIAL_ADDRESS 0x4000
>> 17 #define TEXTSTART 0x0000000000404000
>> 18
34 #endif 19 #endif
35 20
36 OUTPUT_FORMAT(__OUTPUT_FORMAT, __OUTPUT_FORMAT !! 21 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
>> 22
>> 23 #ifdef CONFIG_SPARC32
>> 24 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
>> 25 OUTPUT_ARCH(sparc)
>> 26 ENTRY(_start)
37 jiffies = jiffies_64 + 4; 27 jiffies = jiffies_64 + 4;
>> 28 #else
>> 29 /* sparc64 */
>> 30 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc")
>> 31 OUTPUT_ARCH(sparc:v9a)
>> 32 ENTRY(_start)
>> 33 jiffies = jiffies_64;
>> 34 #endif
38 35
39 SECTIONS 36 SECTIONS
40 { 37 {
41 /* Read-only sections, merged into tex !! 38 /* swapper_low_pmd_dir is sparc64 only */
42 . = LOAD_BASE ; !! 39 swapper_low_pmd_dir = 0x0000000000402000;
43 !! 40 . = INITIAL_ADDRESS;
44 _text = .; !! 41 .text TEXTSTART :
45 <<
46 /* _s_kernel_ro must be page aligned * <<
47 . = ALIGN(PAGE_SIZE); <<
48 _s_kernel_ro = .; <<
49 <<
50 .text : AT(ADDR(.tex <<
51 { 42 {
52 _stext = .; !! 43 _text = .;
53 TEXT_TEXT !! 44 HEAD_TEXT
54 SCHED_TEXT !! 45 TEXT_TEXT
55 LOCK_TEXT !! 46 SCHED_TEXT
56 KPROBES_TEXT !! 47 LOCK_TEXT
57 IRQENTRY_TEXT !! 48 KPROBES_TEXT
58 SOFTIRQENTRY_TEXT !! 49 IRQENTRY_TEXT
59 *(.fixup) !! 50 *(.gnu.warning)
60 *(.text.__*) !! 51 } = 0
61 _etext = .; !! 52 _etext = .;
62 } <<
63 /* TODO: Check if fixup and text.__* a <<
64 * fixup is definitely necessary <<
65 */ <<
66 <<
67 _sdata = .; <<
68 53
69 /* Page alignment required for RO_DATA <<
70 RO_DATA(PAGE_SIZE) 54 RO_DATA(PAGE_SIZE)
71 _e_kernel_ro = .; <<
72 55
73 /* Whatever comes after _e_kernel_ro h !! 56 /* Start of data section */
>> 57 _sdata = .;
74 58
75 /* 32 here is cacheline size... rechec !! 59 .data1 : {
76 RW_DATA(32, PAGE_SIZE, PAGE_SIZE) !! 60 *(.data1)
>> 61 }
>> 62 RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE)
77 63
78 _edata = .; !! 64 /* End of data section */
>> 65 _edata = .;
79 66
80 EXCEPTION_TABLE(4) !! 67 .fixup : {
>> 68 __start___fixup = .;
>> 69 *(.fixup)
>> 70 __stop___fixup = .;
>> 71 }
>> 72 EXCEPTION_TABLE(16)
>> 73 NOTES
81 74
82 /* Init code and data */ <<
83 . = ALIGN(PAGE_SIZE); 75 . = ALIGN(PAGE_SIZE);
84 __init_begin = .; !! 76 __init_begin = ALIGN(PAGE_SIZE);
85 <<
86 HEAD_TEXT_SECTION <<
87 <<
88 /* Page aligned */ <<
89 INIT_TEXT_SECTION(PAGE_SIZE) 77 INIT_TEXT_SECTION(PAGE_SIZE)
90 !! 78 __init_text_end = .;
91 /* Align __setup_start on 16 byte boun <<
92 INIT_DATA_SECTION(16) 79 INIT_DATA_SECTION(16)
93 80
94 PERCPU_SECTION(L1_CACHE_BYTES) !! 81 . = ALIGN(4);
>> 82 .tsb_ldquad_phys_patch : {
>> 83 __tsb_ldquad_phys_patch = .;
>> 84 *(.tsb_ldquad_phys_patch)
>> 85 __tsb_ldquad_phys_patch_end = .;
>> 86 }
>> 87
>> 88 .tsb_phys_patch : {
>> 89 __tsb_phys_patch = .;
>> 90 *(.tsb_phys_patch)
>> 91 __tsb_phys_patch_end = .;
>> 92 }
95 93
96 __init_end = .; !! 94 .cpuid_patch : {
>> 95 __cpuid_patch = .;
>> 96 *(.cpuid_patch)
>> 97 __cpuid_patch_end = .;
>> 98 }
97 99
98 BSS_SECTION(0, 0, 0x20) !! 100 .sun4v_1insn_patch : {
>> 101 __sun4v_1insn_patch = .;
>> 102 *(.sun4v_1insn_patch)
>> 103 __sun4v_1insn_patch_end = .;
>> 104 }
>> 105 .sun4v_2insn_patch : {
>> 106 __sun4v_2insn_patch = .;
>> 107 *(.sun4v_2insn_patch)
>> 108 __sun4v_2insn_patch_end = .;
>> 109 }
>> 110 .leon_1insn_patch : {
>> 111 __leon_1insn_patch = .;
>> 112 *(.leon_1insn_patch)
>> 113 __leon_1insn_patch_end = .;
>> 114 }
>> 115 .swapper_tsb_phys_patch : {
>> 116 __swapper_tsb_phys_patch = .;
>> 117 *(.swapper_tsb_phys_patch)
>> 118 __swapper_tsb_phys_patch_end = .;
>> 119 }
>> 120 .swapper_4m_tsb_phys_patch : {
>> 121 __swapper_4m_tsb_phys_patch = .;
>> 122 *(.swapper_4m_tsb_phys_patch)
>> 123 __swapper_4m_tsb_phys_patch_end = .;
>> 124 }
>> 125 .popc_3insn_patch : {
>> 126 __popc_3insn_patch = .;
>> 127 *(.popc_3insn_patch)
>> 128 __popc_3insn_patch_end = .;
>> 129 }
>> 130 .popc_6insn_patch : {
>> 131 __popc_6insn_patch = .;
>> 132 *(.popc_6insn_patch)
>> 133 __popc_6insn_patch_end = .;
>> 134 }
>> 135 .pause_3insn_patch : {
>> 136 __pause_3insn_patch = .;
>> 137 *(.pause_3insn_patch)
>> 138 __pause_3insn_patch_end = .;
>> 139 }
>> 140 PERCPU_SECTION(SMP_CACHE_BYTES)
99 141
100 _end = .; !! 142 . = ALIGN(PAGE_SIZE);
>> 143 __init_end = .;
>> 144 BSS_SECTION(0, 0, 0)
>> 145 _end = . ;
101 146
102 /* Throw in the debugging sections */ <<
103 STABS_DEBUG 147 STABS_DEBUG
104 DWARF_DEBUG 148 DWARF_DEBUG
105 ELF_DETAILS <<
106 149
107 /* Sections to be discarded -- must be <<
108 DISCARDS 150 DISCARDS
109 } 151 }
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