1 /* SPDX-License-Identifier: GPL-2.0-or-later * !! 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * OpenRISC memset.S !! 3 * linux/arch/alpha/lib/memset.S
4 * 4 *
5 * Hand-optimized assembler version of memset !! 5 * This is an efficient (and small) implementation of the C library "memset()"
6 * Algorithm inspired by several other arch-sp !! 6 * function for the alpha.
7 * in the kernel tree <<
8 * 7 *
9 * Copyright (C) 2015 Olof Kindgren <olof.kindg !! 8 * (C) Copyright 1996 Linus Torvalds
>> 9 *
>> 10 * This routine is "moral-ware": you are free to use it any way you wish, and
>> 11 * the only obligation I put on you is a moral one: if you make any improvements
>> 12 * to the routine, please send me your improvements for me to use similarly.
>> 13 *
>> 14 * The scheduling comments are according to the EV5 documentation (and done by
>> 15 * hand, so they might well be incorrect, please do tell me about it..)
10 */ 16 */
11 !! 17 #include <linux/export.h>
12 .global memset !! 18 .set noat
13 .type memset, @function !! 19 .set noreorder
14 memset: !! 20 .text
15 /* arguments: !! 21 .globl memset
16 * r3 = *s !! 22 .globl __memset
17 * r4 = c !! 23 .globl ___memset
18 * r5 = n !! 24 .globl __memset16
19 * r13, r15, r17, r19 used as temp reg !! 25 .globl __constant_c_memset
20 */ !! 26
21 !! 27 .ent ___memset
22 /* Exit if n == 0 */ !! 28 .align 5
23 l.sfeqi r5, 0 !! 29 ___memset:
24 l.bf 4f !! 30 .frame $30,0,$26,0
25 !! 31 .prologue 0
26 /* Truncate c to char */ !! 32
27 l.andi r13, r4, 0xff !! 33 and $17,255,$1 /* E1 */
28 !! 34 insbl $17,1,$17 /* .. E0 */
29 /* Skip word extension if c is 0 */ !! 35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
30 l.sfeqi r13, 0 !! 36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
31 l.bf 1f !! 37
32 /* Check for at least two whole words !! 38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
33 l.sfleui r5, 7 !! 39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
34 !! 40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
35 /* Extend char c to 32-bit word cccc i !! 41 ldq_u $31,0($30) /* .. E1 */
36 l.slli r15, r13, 16 // r13 = !! 42
37 l.or r13, r13, r15 // r13 = !! 43 .align 5
38 l.slli r15, r13, 8 // r13 = !! 44 __constant_c_memset:
39 l.or r13, r13, r15 // r13 = !! 45 addq $18,$16,$6 /* E0 */
40 !! 46 bis $16,$16,$0 /* .. E1 */
41 1: l.addi r19, r3, 0 // Set r19 !! 47 xor $16,$6,$1 /* E0 */
42 /* Jump to byte copy loop if less than !! 48 ble $18,end /* .. E1 */
43 l.bf 3f !! 49
44 l.or r17, r5, r0 // Set r17 !! 50 bic $1,7,$1 /* E0 */
45 !! 51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
46 /* Mask out two LSBs to check alignmen !! 52 and $16,7,$3 /* E0 */
47 l.andi r15, r3, 0x3 !! 53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
48 !! 54
49 /* lsb == 00, jump to word copy loop * !! 55 ldq_u $4,0($16) /* E0 */
50 l.sfeqi r15, 0 !! 56 bis $16,$16,$5 /* .. E1 */
51 l.bf 2f !! 57 insql $17,$16,$2 /* E0 */
52 l.addi r19, r3, 0 // Set r19 !! 58 subq $3,8,$3 /* .. E1 */
53 !! 59
54 /* lsb == 01,10 or 11 */ !! 60 addq $18,$3,$18 /* E0 $18 is new count ($3 is negative) */
55 l.sb 0(r3), r13 // *src = !! 61 mskql $4,$16,$4 /* .. E1 (and possible load stall) */
56 l.addi r17, r17, -1 // Decrea !! 62 subq $16,$3,$16 /* E0 $16 is new aligned destination */
57 !! 63 bis $2,$4,$1 /* .. E1 */
58 l.sfeqi r15, 3 !! 64
59 l.bf 2f !! 65 bis $31,$31,$31 /* E0 */
60 l.addi r19, r3, 1 // src += !! 66 ldq_u $31,0($30) /* .. E1 */
61 !! 67 stq_u $1,0($5) /* E0 */
62 /* lsb == 01 or 10 */ !! 68 bis $31,$31,$31 /* .. E1 */
63 l.sb 1(r3), r13 // *(src+ !! 69
64 l.addi r17, r17, -1 // Decrea !! 70 .align 4
65 !! 71 aligned:
66 l.sfeqi r15, 2 !! 72 sra $18,3,$3 /* E0 */
67 l.bf 2f !! 73 and $18,7,$18 /* .. E1 */
68 l.addi r19, r3, 2 // src += !! 74 bis $16,$16,$5 /* E0 */
69 !! 75 beq $3,no_quad /* .. E1 */
70 /* lsb == 01 */ !! 76
71 l.sb 2(r3), r13 // *(src+ !! 77 .align 3
72 l.addi r17, r17, -1 // Decrea !! 78 loop:
73 l.addi r19, r3, 3 // src += !! 79 stq $17,0($5) /* E0 */
74 !! 80 subq $3,1,$3 /* .. E1 */
75 /* Word copy loop */ !! 81 addq $5,8,$5 /* E0 */
76 2: l.sw 0(r19), r13 // *src = !! 82 bne $3,loop /* .. E1 */
77 l.addi r17, r17, -4 // Decrea !! 83
78 l.sfgeui r17, 4 !! 84 no_quad:
79 l.bf 2b !! 85 bis $31,$31,$31 /* E0 */
80 l.addi r19, r19, 4 // Increa !! 86 beq $18,end /* .. E1 */
81 !! 87 ldq $7,0($5) /* E0 */
82 /* When n > 0, copy the remaining byte !! 88 mskqh $7,$6,$2 /* .. E1 (and load stall) */
83 l.sfeqi r17, 0 !! 89
84 l.bf 4f !! 90 insqh $17,$6,$4 /* E0 */
85 !! 91 bis $2,$4,$1 /* .. E1 */
86 /* Byte copy loop */ !! 92 stq $1,0($5) /* E0 */
87 3: l.addi r17, r17, -1 // Decrea !! 93 ret $31,($26),1 /* .. E1 */
88 l.sb 0(r19), r13 // *src = !! 94
89 l.sfnei r17, 0 !! 95 .align 3
90 l.bf 3b !! 96 within_one_quad:
91 l.addi r19, r19, 1 // Increa !! 97 ldq_u $1,0($16) /* E0 */
92 !! 98 insql $17,$16,$2 /* E1 */
93 4: l.jr r9 !! 99 mskql $1,$16,$4 /* E0 (after load stall) */
94 l.ori r11, r3, 0 !! 100 bis $2,$4,$2 /* E0 */
>> 101
>> 102 mskql $2,$6,$4 /* E0 */
>> 103 mskqh $1,$6,$2 /* .. E1 */
>> 104 bis $2,$4,$1 /* E0 */
>> 105 stq_u $1,0($16) /* E0 */
>> 106
>> 107 end:
>> 108 ret $31,($26),1 /* E1 */
>> 109 .end ___memset
>> 110 EXPORT_SYMBOL(___memset)
>> 111 EXPORT_SYMBOL(__constant_c_memset)
>> 112
>> 113 .align 5
>> 114 .ent __memset16
>> 115 __memset16:
>> 116 .prologue 0
>> 117
>> 118 inswl $17,0,$1 /* E0 */
>> 119 inswl $17,2,$2 /* E0 */
>> 120 inswl $17,4,$3 /* E0 */
>> 121 or $1,$2,$1 /* .. E1 */
>> 122 inswl $17,6,$4 /* E0 */
>> 123 or $1,$3,$1 /* .. E1 */
>> 124 or $1,$4,$17 /* E0 */
>> 125 br __constant_c_memset /* .. E1 */
>> 126
>> 127 .end __memset16
>> 128 EXPORT_SYMBOL(__memset16)
>> 129
>> 130 memset = ___memset
>> 131 __memset = ___memset
>> 132 EXPORT_SYMBOL(memset)
>> 133 EXPORT_SYMBOL(__memset)
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