1 // SPDX-License-Identifier: GPL-2.0-or-later !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * OpenRISC cache.c !! 3 * linux/arch/m68k/mm/cache.c
4 * 4 *
5 * Linux architectural port borrowing liberall !! 5 * Instruction cache handling
6 * others. All original copyrights apply as p <<
7 * declaration. <<
8 * 6 *
9 * Modifications for the OpenRISC architecture !! 7 * Copyright (C) 1995 Hamish Macdonald
10 * Copyright (C) 2015 Jan Henrik Weinstock <ja <<
11 */ 8 */
12 9
13 #include <asm/spr.h> !! 10 #include <linux/module.h>
14 #include <asm/spr_defs.h> <<
15 #include <asm/cache.h> <<
16 #include <asm/cacheflush.h> 11 #include <asm/cacheflush.h>
17 #include <asm/tlbflush.h> !! 12 #include <asm/traps.h>
18 13
19 static __always_inline void cache_loop(struct !! 14
>> 15 static unsigned long virt_to_phys_slow(unsigned long vaddr)
20 { 16 {
21 unsigned long paddr = page_to_pfn(page !! 17 if (CPU_IS_060) {
22 unsigned long line = paddr & ~(L1_CACH !! 18 unsigned long paddr;
23 19
24 while (line < paddr + PAGE_SIZE) { !! 20 /* The PLPAR instruction causes an access error if the translation
25 mtspr(reg, line); !! 21 * is not possible. To catch this we use the same exception mechanism
26 line += L1_CACHE_BYTES; !! 22 * as for user space accesses in <asm/uaccess.h>. */
>> 23 asm volatile (".chip 68060\n"
>> 24 "1: plpar (%0)\n"
>> 25 ".chip 68k\n"
>> 26 "2:\n"
>> 27 ".section .fixup,\"ax\"\n"
>> 28 " .even\n"
>> 29 "3: sub.l %0,%0\n"
>> 30 " jra 2b\n"
>> 31 ".previous\n"
>> 32 ".section __ex_table,\"a\"\n"
>> 33 " .align 4\n"
>> 34 " .long 1b,3b\n"
>> 35 ".previous"
>> 36 : "=a" (paddr)
>> 37 : "" (vaddr));
>> 38 return paddr;
>> 39 } else if (CPU_IS_040) {
>> 40 unsigned long mmusr;
>> 41
>> 42 asm volatile (".chip 68040\n\t"
>> 43 "ptestr (%1)\n\t"
>> 44 "movec %%mmusr, %0\n\t"
>> 45 ".chip 68k"
>> 46 : "=r" (mmusr)
>> 47 : "a" (vaddr));
>> 48
>> 49 if (mmusr & MMU_R_040)
>> 50 return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
>> 51 } else {
>> 52 WARN_ON_ONCE(!CPU_IS_040_OR_060);
27 } 53 }
>> 54 return 0;
28 } 55 }
29 56
30 void local_dcache_page_flush(struct page *page !! 57 /* Push n pages at kernel virtual address and clear the icache */
>> 58 /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
>> 59 void flush_icache_user_range(unsigned long address, unsigned long endaddr)
31 { 60 {
32 cache_loop(page, SPR_DCBFR); !! 61 if (CPU_IS_COLDFIRE) {
>> 62 unsigned long start, end;
>> 63 start = address & ICACHE_SET_MASK;
>> 64 end = endaddr & ICACHE_SET_MASK;
>> 65 if (start > end) {
>> 66 flush_cf_icache(0, end);
>> 67 end = ICACHE_MAX_ADDR;
>> 68 }
>> 69 flush_cf_icache(start, end);
>> 70 } else if (CPU_IS_040_OR_060) {
>> 71 address &= PAGE_MASK;
>> 72
>> 73 do {
>> 74 asm volatile ("nop\n\t"
>> 75 ".chip 68040\n\t"
>> 76 "cpushp %%bc,(%0)\n\t"
>> 77 ".chip 68k"
>> 78 : : "a" (virt_to_phys_slow(address)));
>> 79 address += PAGE_SIZE;
>> 80 } while (address < endaddr);
>> 81 } else {
>> 82 unsigned long tmp;
>> 83 asm volatile ("movec %%cacr,%0\n\t"
>> 84 "orw %1,%0\n\t"
>> 85 "movec %0,%%cacr"
>> 86 : "=&d" (tmp)
>> 87 : "di" (FLUSH_I));
>> 88 }
33 } 89 }
34 EXPORT_SYMBOL(local_dcache_page_flush); <<
35 90
36 void local_icache_page_inv(struct page *page) !! 91 void flush_icache_range(unsigned long address, unsigned long endaddr)
37 { 92 {
38 cache_loop(page, SPR_ICBIR); !! 93 set_fc(SUPER_DATA);
>> 94 flush_icache_user_range(address, endaddr);
>> 95 set_fc(USER_DATA);
39 } 96 }
40 EXPORT_SYMBOL(local_icache_page_inv); !! 97 EXPORT_SYMBOL(flush_icache_range);
41 98
42 void update_cache(struct vm_area_struct *vma, !! 99 void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
43 pte_t *pte) !! 100 unsigned long addr, int len)
44 { 101 {
45 unsigned long pfn = pte_val(*pte) >> P !! 102 if (CPU_IS_COLDFIRE) {
46 struct folio *folio = page_folio(pfn_t !! 103 unsigned long start, end;
47 int dirty = !test_and_set_bit(PG_dc_cl !! 104 start = addr & ICACHE_SET_MASK;
48 !! 105 end = (addr + len) & ICACHE_SET_MASK;
49 /* !! 106 if (start > end) {
50 * Since icaches do not snoop for upda !! 107 flush_cf_icache(0, end);
51 * must write back and invalidate any !! 108 end = ICACHE_MAX_ADDR;
52 * can skip data pages, since they wil !! 109 }
53 */ !! 110 flush_cf_icache(start, end);
54 if ((vma->vm_flags & VM_EXEC) && dirty !! 111
55 unsigned int nr = folio_nr_pag !! 112 } else if (CPU_IS_040_OR_060) {
56 !! 113 asm volatile ("nop\n\t"
57 while (nr--) !! 114 ".chip 68040\n\t"
58 sync_icache_dcache(fol !! 115 "cpushp %%bc,(%0)\n\t"
>> 116 ".chip 68k"
>> 117 : : "a" (page_to_phys(page)));
>> 118 } else {
>> 119 unsigned long tmp;
>> 120 asm volatile ("movec %%cacr,%0\n\t"
>> 121 "orw %1,%0\n\t"
>> 122 "movec %0,%%cacr"
>> 123 : "=&d" (tmp)
>> 124 : "di" (FLUSH_I));
59 } 125 }
60 } 126 }
61 127
62 128
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