1 /* SPDX-License-Identifier: GPL-2.0-or-later * !! 1 /* $Id: entry.S,v 1.141 2001/12/05 23:56:32 davem Exp $
2 /* !! 2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 * Linux/PA-RISC Project (http://www.parisc-li <<
4 * 3 *
5 * kernel entry points (interruptions, system !! 4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1999,2000 Philipp Rumpf !! 5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1999 SuSE GmbH Nuernberg !! 6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 2000 Hewlett-Packard (John M !! 7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 * Copyright (C) 1999 Hewlett-Packard (Frank <<
10 */ 8 */
11 9
12 #include <asm/asm-offsets.h> !! 10 #include <linux/config.h>
13 !! 11 #include <linux/errno.h>
14 /* we have the following possibilities to act <<
15 * - handle in assembly and use shadowed regi <<
16 * - save registers to kernel stack and handl <<
17 12
18 !! 13 #include <asm/head.h>
19 #include <asm/psw.h> !! 14 #include <asm/asi.h>
20 #include <asm/cache.h> /* for L1_CACH !! 15 #include <asm/smp.h>
21 #include <asm/assembly.h> /* for LDREG/S !! 16 #include <asm/ptrace.h>
>> 17 #include <asm/page.h>
22 #include <asm/signal.h> 18 #include <asm/signal.h>
23 #include <asm/unistd.h> !! 19 #include <asm/pgtable.h>
24 #include <asm/ldcw.h> !! 20 #include <asm/processor.h>
25 #include <asm/traps.h> !! 21 #include <asm/visasm.h>
26 #include <asm/thread_info.h> !! 22 #include <asm/estate.h>
27 #include <asm/alternative.h> !! 23 #include <asm/auxio.h>
28 #include <asm/spinlock_types.h> !! 24 #include <asm/sfafsr.h>
29 <<
30 #include <linux/linkage.h> <<
31 #include <linux/pgtable.h> <<
32 <<
33 #ifdef CONFIG_64BIT <<
34 .level 2.0w <<
35 #else <<
36 .level 2.0 <<
37 #endif <<
38 <<
39 /* <<
40 * We need seven instructions after a TLB inse <<
41 * The PA8800/PA8900 processors are an excepti <<
42 * The RFI changes both IAOQ_Back and IAOQ_Fro <<
43 */ <<
44 #ifdef CONFIG_64BIT <<
45 #define NUM_PIPELINE_INSNS 12 <<
46 #else <<
47 #define NUM_PIPELINE_INSNS 7 <<
48 #endif <<
49 <<
50 /* Insert num nops */ <<
51 .macro insert_nops num <<
52 .rept \num <<
53 nop <<
54 .endr <<
55 .endm <<
56 <<
57 /* Get aligned page_table_lock address <<
58 .macro get_ptl reg <<
59 mfctl %cr28,\reg <<
60 .endm <<
61 <<
62 /* space_to_prot macro creates a prot <<
63 <<
64 #if (SPACEID_SHIFT) == 0 <<
65 .macro space_to_prot spc prot <<
66 depd,z \spc,62,31,\prot <<
67 .endm <<
68 #else <<
69 .macro space_to_prot spc prot <<
70 extrd,u \spc,(64 - (SPACEID_SHIFT)),32 <<
71 .endm <<
72 #endif <<
73 /* <<
74 * The "get_stack" macros are responsi <<
75 * kernel stack value. <<
76 * <<
77 * If sr7 == 0 <<
78 * Already using a kernel sta <<
79 * get_stack_use_r30 macro to <<
80 * on the stack, and store re <<
81 * else <<
82 * Need to set up a kernel st <<
83 * get_stack_use_cr30 macro t <<
84 * to the pt_regs structure c <<
85 * task pointer pointed to by <<
86 * pointer from the task stru <<
87 * <<
88 * Note that we use shadowed registers <<
89 * we can save %r26 and %r29. %r26 is <<
90 * %r8 (a shadowed register) which tem <<
91 * either the fault type ("code") or t <<
92 * to use a non-shadowed register to c <<
93 * the rfir in virt_map. We use %r26 s <<
94 * up being passed as the argument to <<
95 * or handle_interruption. %r29 is use <<
96 * the register save area, and once ag <<
97 * be a non-shadowed register so that <<
98 */ <<
99 <<
100 .macro get_stack_use_cr30 <<
101 <<
102 /* we save the registers in the task s <<
103 <<
104 copy %r30, %r17 <<
105 mfctl %cr30, %r1 <<
106 tophys %r1,%r9 /* task_struct <<
107 LDREG TASK_STACK(%r9),%r30 <<
108 ldo PT_SZ_ALGN(%r30),%r30 <<
109 mtsp %r0,%sr7 /* clear sr7 a <<
110 mtsp %r16,%sr3 <<
111 ldo TASK_REGS(%r9),%r9 <<
112 STREG %r17,PT_GR30(%r9) <<
113 STREG %r29,PT_GR29(%r9) <<
114 STREG %r26,PT_GR26(%r9) <<
115 STREG %r16,PT_SR7(%r9) <<
116 copy %r9,%r29 <<
117 .endm <<
118 <<
119 .macro get_stack_use_r30 <<
120 <<
121 /* we put a struct pt_regs on the stac <<
122 <<
123 tophys %r30,%r9 <<
124 copy %r30,%r1 <<
125 ldo PT_SZ_ALGN(%r30),%r30 <<
126 STREG %r1,PT_GR30(%r9) <<
127 STREG %r29,PT_GR29(%r9) <<
128 STREG %r26,PT_GR26(%r9) <<
129 STREG %r16,PT_SR7(%r9) <<
130 copy %r9,%r29 <<
131 .endm <<
132 <<
133 .macro rest_stack <<
134 LDREG PT_GR1(%r29), %r1 <<
135 LDREG PT_GR30(%r29),%r30 <<
136 LDREG PT_GR29(%r29),%r29 <<
137 .endm <<
138 <<
139 /* default interruption handler <<
140 * (calls traps.c:handle_interruption) <<
141 .macro def code <<
142 b intr_save <<
143 ldi \code, %r8 <<
144 .align 32 <<
145 .endm <<
146 <<
147 /* Interrupt interruption handler <<
148 * (calls irq.c:do_cpu_irq_mask) */ <<
149 .macro extint code <<
150 b intr_extint <<
151 mfsp %sr7,%r16 <<
152 .align 32 <<
153 .endm <<
154 <<
155 .import os_hpmc, code <<
156 <<
157 /* HPMC handler */ <<
158 .macro hpmc code <<
159 nop /* must be a N <<
160 load32 PA(os_hpmc), %r3 <<
161 bv,n 0(%r3) <<
162 nop <<
163 .word 0 /* checksum (w <<
164 .word 0 /* address of <<
165 .word 0 /* length of h <<
166 .endm <<
167 <<
168 /* <<
169 * Performance Note: Instructions will <<
170 * this part of the code later on, onc <<
171 * that the tlb miss handlers are clos <<
172 */ <<
173 <<
174 /* Register definitions for tlb miss h <<
175 <<
176 va = r8 /* virtual address for <<
177 spc = r24 /* space for which the <<
178 <<
179 #ifndef CONFIG_64BIT <<
180 <<
181 /* <<
182 * itlb miss interruption handler (par <<
183 */ <<
184 <<
185 .macro itlb_11 code <<
186 <<
187 mfctl %pcsq, spc <<
188 b itlb_miss_11 <<
189 mfctl %pcoq, va <<
190 <<
191 .align 32 <<
192 .endm <<
193 #endif <<
194 <<
195 /* <<
196 * itlb miss interruption handler (par <<
197 */ <<
198 <<
199 .macro itlb_20 code <<
200 mfctl %pcsq, spc <<
201 #ifdef CONFIG_64BIT <<
202 b itlb_miss_20w <<
203 #else <<
204 b itlb_miss_20 <<
205 #endif <<
206 mfctl %pcoq, va <<
207 <<
208 .align 32 <<
209 .endm <<
210 <<
211 #ifndef CONFIG_64BIT <<
212 /* <<
213 * naitlb miss interruption handler (p <<
214 */ <<
215 <<
216 .macro naitlb_11 code <<
217 <<
218 mfctl %isr,spc <<
219 b naitlb_miss_11 <<
220 mfctl %ior,va <<
221 <<
222 .align 32 <<
223 .endm <<
224 #endif <<
225 <<
226 /* <<
227 * naitlb miss interruption handler (p <<
228 */ <<
229 <<
230 .macro naitlb_20 code <<
231 <<
232 mfctl %isr,spc <<
233 #ifdef CONFIG_64BIT <<
234 b naitlb_miss_20w <<
235 #else <<
236 b naitlb_miss_20 <<
237 #endif <<
238 mfctl %ior,va <<
239 <<
240 .align 32 <<
241 .endm <<
242 <<
243 #ifndef CONFIG_64BIT <<
244 /* <<
245 * dtlb miss interruption handler (par <<
246 */ <<
247 25
248 .macro dtlb_11 code !! 26 /* #define SYSCALL_TRACING 1 */
249 27
250 mfctl %isr, spc !! 28 #define curptr g6
251 b dtlb_miss_11 <<
252 mfctl %ior, va <<
253 29
254 .align 32 !! 30 #define NR_SYSCALLS 256 /* Each OS is different... */
255 .endm <<
256 #endif <<
257 <<
258 /* <<
259 * dtlb miss interruption handler (par <<
260 */ <<
261 <<
262 .macro dtlb_20 code <<
263 <<
264 mfctl %isr, spc <<
265 #ifdef CONFIG_64BIT <<
266 b dtlb_miss_20w <<
267 #else <<
268 b dtlb_miss_20 <<
269 #endif <<
270 mfctl %ior, va <<
271 31
>> 32 .text
272 .align 32 33 .align 32
273 .endm <<
274 <<
275 #ifndef CONFIG_64BIT <<
276 /* nadtlb miss interruption handler (p <<
277 34
278 .macro nadtlb_11 code !! 35 .globl sparc64_vpte_patchme1
>> 36 .globl sparc64_vpte_patchme2
>> 37 /*
>> 38 * On a second level vpte miss, check whether the original fault is to the OBP
>> 39 * range (note that this is only possible for instruction miss, data misses to
>> 40 * obp range do not use vpte). If so, go back directly to the faulting address.
>> 41 * This is because we want to read the tpc, otherwise we have no way of knowing
>> 42 * the 8k aligned faulting address if we are using >8k kernel pagesize. This also
>> 43 * ensures no vpte range addresses are dropped into tlb while obp is executing
>> 44 * (see inherit_locked_prom_mappings() rant).
>> 45 */
>> 46 sparc64_vpte_nucleus:
>> 47 mov 0xf, %g5
>> 48 sllx %g5, 28, %g5 ! Load 0xf0000000
>> 49 cmp %g4, %g5 ! Is addr >= LOW_OBP_ADDRESS?
>> 50 blu,pn %xcc, sparc64_vpte_patchme1
>> 51 mov 0x1, %g5
>> 52 sllx %g5, 32, %g5 ! Load 0x100000000
>> 53 cmp %g4, %g5 ! Is addr < HI_OBP_ADDRESS?
>> 54 blu,pn %xcc, obp_iaddr_patch
>> 55 nop
>> 56 sparc64_vpte_patchme1:
>> 57 sethi %hi(0), %g5 ! This has to be patched
>> 58 sparc64_vpte_patchme2:
>> 59 or %g5, %lo(0), %g5 ! This is patched too
>> 60 ba,pt %xcc, sparc64_kpte_continue ! Part of dtlb_backend
>> 61 add %g1, %g1, %g1 ! Finish PMD offset adjustment
>> 62
>> 63 vpte_noent:
>> 64 mov TLB_SFSR, %g1 ! Restore %g1 value
>> 65 stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS
>> 66 done ! Slick trick
>> 67
>> 68 .globl obp_iaddr_patch
>> 69 .globl obp_daddr_patch
>> 70
>> 71 obp_iaddr_patch:
>> 72 sethi %hi(0), %g5 ! This and following is patched
>> 73 or %g5, %lo(0), %g5 ! g5 now holds obp pmd base physaddr
>> 74 wrpr %g0, 1, %tl ! Behave as if we are at TL0
>> 75 rdpr %tpc, %g4 ! Find original faulting iaddr
>> 76 srlx %g4, 13, %g4 ! Throw out context bits
>> 77 sllx %g4, 13, %g4 ! g4 has vpn + ctx0 now
>> 78 mov TLB_SFSR, %g1 ! Restore %g1 value
>> 79 stxa %g4, [%g1 + %g1] ASI_IMMU ! Restore previous TAG_ACCESS
>> 80 srlx %g4, 23, %g6 ! Find pmd number
>> 81 and %g6, 0x7ff, %g6 ! Find pmd number
>> 82 sllx %g6, 2, %g6 ! Find pmd offset
>> 83 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pmd, ie pagetable physaddr
>> 84 brz,pn %g5, longpath ! Kill the PROM ? :-)
>> 85 sllx %g5, 11, %g5 ! Shift into place
>> 86 srlx %g4, 13, %g6 ! find pte number in pagetable
>> 87 and %g6, 0x3ff, %g6 ! find pte number in pagetable
>> 88 sllx %g6, 3, %g6 ! find pte offset in pagetable
>> 89 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pte
>> 90 brgez,pn %g5, longpath ! Kill the PROM ? :-)
>> 91 nop
>> 92 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! put into tlb
>> 93 retry ! go back to original fault
>> 94
>> 95 obp_daddr_patch:
>> 96 sethi %hi(0), %g5 ! This and following is patched
>> 97 or %g5, %lo(0), %g5 ! g5 now holds obp pmd base physaddr
>> 98 srlx %g4, 23, %g6 ! Find pmd number
>> 99 and %g6, 0x7ff, %g6 ! Find pmd number
>> 100 sllx %g6, 2, %g6 ! Find pmd offset
>> 101 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pmd, ie pagetable physaddr
>> 102 brz,pn %g5, longpath
>> 103 sllx %g5, 11, %g5 ! Shift into place
>> 104 srlx %g4, 13, %g6 ! find pte number in pagetable
>> 105 and %g6, 0x3ff, %g6 ! find pte number in pagetable
>> 106 sllx %g6, 3, %g6 ! find pte offset in pagetable
>> 107 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pte
>> 108 brgez,pn %g5, longpath
>> 109 nop
>> 110 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! put into tlb
>> 111 retry
279 112
280 mfctl %isr,spc !! 113 /*
281 b nadtlb_miss_11 !! 114 * On a first level data miss, check whether this is to the OBP range (note that
282 mfctl %ior,va !! 115 * such accesses can be made by prom, as well as by kernel using prom_getproperty
>> 116 * on "address"), and if so, do not use vpte access ... rather, use information
>> 117 * saved during inherit_prom_mappings() using 8k pagesize.
>> 118 */
>> 119 kvmap:
>> 120 mov 0xf, %g5
>> 121 sllx %g5, 28, %g5 ! Load 0xf0000000
>> 122 cmp %g4, %g5 ! Is addr >= LOW_OBP_ADDRESS?
>> 123 blu,pn %xcc, vmalloc_addr
>> 124 mov 0x1, %g5
>> 125 sllx %g5, 32, %g5 ! Load 0x100000000
>> 126 cmp %g4, %g5 ! Is addr < HI_OBP_ADDRESS?
>> 127 blu,pn %xcc, obp_daddr_patch
>> 128 nop
>> 129 vmalloc_addr: ! vmalloc addr accessed
>> 130 ldxa [%g3 + %g6] ASI_N, %g5 ! Yep, load k-vpte
>> 131 brgez,pn %g5, longpath ! Valid, load into TLB
>> 132 nop
>> 133 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
>> 134 retry
>> 135
>> 136 /* This is trivial with the new code... */
>> 137 .globl do_fpdis
>> 138 do_fpdis:
>> 139 sethi %hi(TSTATE_PEF), %g4 ! IEU0
>> 140 rdpr %tstate, %g5
>> 141 andcc %g5, %g4, %g0
>> 142 be,pt %xcc, 1f
>> 143 nop
>> 144 rd %fprs, %g5
>> 145 andcc %g5, FPRS_FEF, %g0
>> 146 be,pt %xcc, 1f
>> 147 nop
>> 148
>> 149 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
>> 150 sethi %hi(109f), %g7
>> 151 ba,pt %xcc, etrap
>> 152 109: or %g7, %lo(109b), %g7
>> 153 add %g0, %g0, %g0
>> 154 ba,a,pt %xcc, rtrap_clr_l6
>> 155
>> 156 1: ldub [%g6 + AOFF_task_thread + AOFF_thread_fpsaved], %g5 ! Load Group
>> 157 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
>> 158 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
>> 159 be,a,pt %icc, 1f ! CTI
>> 160 clr %g7 ! IEU0
>> 161 ldx [%g6 + AOFF_task_thread + AOFF_thread_gsr], %g7 ! Load Group
>> 162 1: andcc %g5, FPRS_DL, %g0 ! IEU1
>> 163 bne,pn %icc, 2f ! CTI
>> 164 fzero %f0 ! FPA
>> 165 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
>> 166 bne,pn %icc, 1f ! CTI
>> 167 fzero %f2 ! FPA
>> 168 faddd %f0, %f2, %f4
>> 169 fmuld %f0, %f2, %f6
>> 170 faddd %f0, %f2, %f8
>> 171 fmuld %f0, %f2, %f10
>> 172 faddd %f0, %f2, %f12
>> 173 fmuld %f0, %f2, %f14
>> 174 faddd %f0, %f2, %f16
>> 175 fmuld %f0, %f2, %f18
>> 176 faddd %f0, %f2, %f20
>> 177 fmuld %f0, %f2, %f22
>> 178 faddd %f0, %f2, %f24
>> 179 fmuld %f0, %f2, %f26
>> 180 faddd %f0, %f2, %f28
>> 181 fmuld %f0, %f2, %f30
>> 182 faddd %f0, %f2, %f32
>> 183 fmuld %f0, %f2, %f34
>> 184 faddd %f0, %f2, %f36
>> 185 fmuld %f0, %f2, %f38
>> 186 faddd %f0, %f2, %f40
>> 187 fmuld %f0, %f2, %f42
>> 188 faddd %f0, %f2, %f44
>> 189 fmuld %f0, %f2, %f46
>> 190 faddd %f0, %f2, %f48
>> 191 fmuld %f0, %f2, %f50
>> 192 faddd %f0, %f2, %f52
>> 193 fmuld %f0, %f2, %f54
>> 194 faddd %f0, %f2, %f56
>> 195 fmuld %f0, %f2, %f58
>> 196 b,pt %xcc, fpdis_exit2
>> 197 faddd %f0, %f2, %f60
>> 198 1: mov SECONDARY_CONTEXT, %g3
>> 199 add %g6, AOFF_task_fpregs + 0x80, %g1
>> 200 faddd %f0, %f2, %f4
>> 201 fmuld %f0, %f2, %f6
>> 202 ldxa [%g3] ASI_DMMU, %g5
>> 203 add %g6, AOFF_task_fpregs + 0xc0, %g2
>> 204 stxa %g0, [%g3] ASI_DMMU
>> 205 membar #Sync
>> 206 faddd %f0, %f2, %f8
>> 207 fmuld %f0, %f2, %f10
>> 208 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
>> 209 ldda [%g2] ASI_BLK_S, %f48
>> 210 faddd %f0, %f2, %f12
>> 211 fmuld %f0, %f2, %f14
>> 212 faddd %f0, %f2, %f16
>> 213 fmuld %f0, %f2, %f18
>> 214 faddd %f0, %f2, %f20
>> 215 fmuld %f0, %f2, %f22
>> 216 faddd %f0, %f2, %f24
>> 217 fmuld %f0, %f2, %f26
>> 218 faddd %f0, %f2, %f28
>> 219 fmuld %f0, %f2, %f30
>> 220 b,pt %xcc, fpdis_exit
>> 221 membar #Sync
>> 222 2: andcc %g5, FPRS_DU, %g0
>> 223 bne,pt %icc, 3f
>> 224 fzero %f32
>> 225 mov SECONDARY_CONTEXT, %g3
>> 226 fzero %f34
>> 227 ldxa [%g3] ASI_DMMU, %g5
>> 228 add %g6, AOFF_task_fpregs, %g1
>> 229 stxa %g0, [%g3] ASI_DMMU
>> 230 membar #Sync
>> 231 add %g6, AOFF_task_fpregs + 0x40, %g2
>> 232 faddd %f32, %f34, %f36
>> 233 fmuld %f32, %f34, %f38
>> 234 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
>> 235 ldda [%g2] ASI_BLK_S, %f16
>> 236 faddd %f32, %f34, %f40
>> 237 fmuld %f32, %f34, %f42
>> 238 faddd %f32, %f34, %f44
>> 239 fmuld %f32, %f34, %f46
>> 240 faddd %f32, %f34, %f48
>> 241 fmuld %f32, %f34, %f50
>> 242 faddd %f32, %f34, %f52
>> 243 fmuld %f32, %f34, %f54
>> 244 faddd %f32, %f34, %f56
>> 245 fmuld %f32, %f34, %f58
>> 246 faddd %f32, %f34, %f60
>> 247 fmuld %f32, %f34, %f62
>> 248 ba,pt %xcc, fpdis_exit
>> 249 membar #Sync
>> 250 3: mov SECONDARY_CONTEXT, %g3
>> 251 add %g6, AOFF_task_fpregs, %g1
>> 252 ldxa [%g3] ASI_DMMU, %g5
>> 253 mov 0x40, %g2
>> 254 stxa %g0, [%g3] ASI_DMMU
>> 255 membar #Sync
>> 256 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
>> 257 ldda [%g1 + %g2] ASI_BLK_S, %f16
>> 258 add %g1, 0x80, %g1
>> 259 ldda [%g1] ASI_BLK_S, %f32
>> 260 ldda [%g1 + %g2] ASI_BLK_S, %f48
>> 261 membar #Sync
>> 262 fpdis_exit:
>> 263 stxa %g5, [%g3] ASI_DMMU
>> 264 membar #Sync
>> 265 fpdis_exit2:
>> 266 wr %g7, 0, %gsr
>> 267 ldx [%g6 + AOFF_task_thread + AOFF_thread_xfsr], %fsr
>> 268 rdpr %tstate, %g3
>> 269 or %g3, %g4, %g3 ! anal...
>> 270 wrpr %g3, %tstate
>> 271 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
>> 272 retry
283 273
284 .align 32 274 .align 32
285 .endm !! 275 fp_other_bounce:
286 #endif !! 276 call do_fpother
287 !! 277 add %sp, PTREGS_OFF, %o0
288 /* nadtlb miss interruption handler (p !! 278 ba,pt %xcc, rtrap
289 !! 279 clr %l6
290 .macro nadtlb_20 code <<
291 <<
292 mfctl %isr,spc <<
293 #ifdef CONFIG_64BIT <<
294 b nadtlb_miss_20w <<
295 #else <<
296 b nadtlb_miss_20 <<
297 #endif <<
298 mfctl %ior,va <<
299 280
>> 281 .globl do_fpother_check_fitos
300 .align 32 282 .align 32
301 .endm !! 283 do_fpother_check_fitos:
302 !! 284 sethi %hi(fp_other_bounce - 4), %g7
303 #ifndef CONFIG_64BIT !! 285 or %g7, %lo(fp_other_bounce - 4), %g7
304 /* !! 286
305 * dirty bit trap interruption handler !! 287 /* NOTE: Need to preserve %g7 until we fully commit
306 */ !! 288 * to the fitos fixup.
307 !! 289 */
308 .macro dbit_11 code !! 290 stx %fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
309 !! 291 rdpr %tstate, %g3
310 mfctl %isr,spc !! 292 andcc %g3, TSTATE_PRIV, %g0
311 b dbit_trap_11 !! 293 bne,pn %xcc, do_fptrap_after_fsr
312 mfctl %ior,va !! 294 nop
>> 295 ldx [%g6 + AOFF_task_thread + AOFF_thread_xfsr], %g3
>> 296 srlx %g3, 14, %g1
>> 297 and %g1, 7, %g1
>> 298 cmp %g1, 2 ! Unfinished FP-OP
>> 299 bne,pn %xcc, do_fptrap_after_fsr
>> 300 sethi %hi(1 << 23), %g1 ! Inexact
>> 301 andcc %g3, %g1, %g0
>> 302 bne,pn %xcc, do_fptrap_after_fsr
>> 303 rdpr %tpc, %g1
>> 304 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
>> 305 #define FITOS_MASK 0xc1f83fe0
>> 306 #define FITOS_COMPARE 0x81a01880
>> 307 sethi %hi(FITOS_MASK), %g1
>> 308 or %g1, %lo(FITOS_MASK), %g1
>> 309 and %g3, %g1, %g1
>> 310 sethi %hi(FITOS_COMPARE), %g2
>> 311 or %g2, %lo(FITOS_COMPARE), %g2
>> 312 cmp %g1, %g2
>> 313 bne,pn %xcc, do_fptrap_after_fsr
>> 314 nop
>> 315 std %f62, [%g6 + AOFF_task_fpregs + (62 * 4)]
>> 316 sethi %hi(fitos_table_1), %g1
>> 317 and %g3, 0x1f, %g2
>> 318 or %g1, %lo(fitos_table_1), %g1
>> 319 sllx %g2, 2, %g2
>> 320 jmpl %g1 + %g2, %g0
>> 321 ba,pt %xcc, fitos_emul_continue
>> 322
>> 323 fitos_table_1:
>> 324 fitod %f0, %f62
>> 325 fitod %f1, %f62
>> 326 fitod %f2, %f62
>> 327 fitod %f3, %f62
>> 328 fitod %f4, %f62
>> 329 fitod %f5, %f62
>> 330 fitod %f6, %f62
>> 331 fitod %f7, %f62
>> 332 fitod %f8, %f62
>> 333 fitod %f9, %f62
>> 334 fitod %f10, %f62
>> 335 fitod %f11, %f62
>> 336 fitod %f12, %f62
>> 337 fitod %f13, %f62
>> 338 fitod %f14, %f62
>> 339 fitod %f15, %f62
>> 340 fitod %f16, %f62
>> 341 fitod %f17, %f62
>> 342 fitod %f18, %f62
>> 343 fitod %f19, %f62
>> 344 fitod %f20, %f62
>> 345 fitod %f21, %f62
>> 346 fitod %f22, %f62
>> 347 fitod %f23, %f62
>> 348 fitod %f24, %f62
>> 349 fitod %f25, %f62
>> 350 fitod %f26, %f62
>> 351 fitod %f27, %f62
>> 352 fitod %f28, %f62
>> 353 fitod %f29, %f62
>> 354 fitod %f30, %f62
>> 355 fitod %f31, %f62
>> 356
>> 357 fitos_emul_continue:
>> 358 sethi %hi(fitos_table_2), %g1
>> 359 srl %g3, 25, %g2
>> 360 or %g1, %lo(fitos_table_2), %g1
>> 361 and %g2, 0x1f, %g2
>> 362 sllx %g2, 2, %g2
>> 363 jmpl %g1 + %g2, %g0
>> 364 ba,pt %xcc, fitos_emul_fini
>> 365
>> 366 fitos_table_2:
>> 367 fdtos %f62, %f0
>> 368 fdtos %f62, %f1
>> 369 fdtos %f62, %f2
>> 370 fdtos %f62, %f3
>> 371 fdtos %f62, %f4
>> 372 fdtos %f62, %f5
>> 373 fdtos %f62, %f6
>> 374 fdtos %f62, %f7
>> 375 fdtos %f62, %f8
>> 376 fdtos %f62, %f9
>> 377 fdtos %f62, %f10
>> 378 fdtos %f62, %f11
>> 379 fdtos %f62, %f12
>> 380 fdtos %f62, %f13
>> 381 fdtos %f62, %f14
>> 382 fdtos %f62, %f15
>> 383 fdtos %f62, %f16
>> 384 fdtos %f62, %f17
>> 385 fdtos %f62, %f18
>> 386 fdtos %f62, %f19
>> 387 fdtos %f62, %f20
>> 388 fdtos %f62, %f21
>> 389 fdtos %f62, %f22
>> 390 fdtos %f62, %f23
>> 391 fdtos %f62, %f24
>> 392 fdtos %f62, %f25
>> 393 fdtos %f62, %f26
>> 394 fdtos %f62, %f27
>> 395 fdtos %f62, %f28
>> 396 fdtos %f62, %f29
>> 397 fdtos %f62, %f30
>> 398 fdtos %f62, %f31
>> 399
>> 400 fitos_emul_fini:
>> 401 ldd [%g6 + AOFF_task_fpregs + (62 * 4)], %f62
>> 402 done
313 403
>> 404 .globl do_fptrap
314 .align 32 405 .align 32
315 .endm !! 406 do_fptrap:
316 #endif !! 407 stx %fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
>> 408 do_fptrap_after_fsr:
>> 409 ldub [%g6 + AOFF_task_thread + AOFF_thread_fpsaved], %g3
>> 410 rd %fprs, %g1
>> 411 or %g3, %g1, %g3
>> 412 stb %g3, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
>> 413 rd %gsr, %g3
>> 414 stx %g3, [%g6 + AOFF_task_thread + AOFF_thread_gsr]
>> 415 mov SECONDARY_CONTEXT, %g3
>> 416 add %g6, AOFF_task_fpregs, %g2
>> 417 ldxa [%g3] ASI_DMMU, %g5
>> 418 stxa %g0, [%g3] ASI_DMMU
>> 419 membar #Sync
>> 420 andcc %g1, FPRS_DL, %g0
>> 421 be,pn %icc, 4f
>> 422 mov 0x40, %g3
>> 423 stda %f0, [%g2] ASI_BLK_S
>> 424 stda %f16, [%g2 + %g3] ASI_BLK_S
>> 425 andcc %g1, FPRS_DU, %g0
>> 426 be,pn %icc, 5f
>> 427 4: add %g2, 128, %g2
>> 428 stda %f32, [%g2] ASI_BLK_S
>> 429 stda %f48, [%g2 + %g3] ASI_BLK_S
>> 430 5: mov SECONDARY_CONTEXT, %g1
>> 431 membar #Sync
>> 432 stxa %g5, [%g1] ASI_DMMU
>> 433 membar #Sync
>> 434 ba,pt %xcc, etrap
>> 435 wr %g0, 0, %fprs
317 436
318 /* !! 437 /* The registers for cross calls will be:
319 * dirty bit trap interruption handler <<
320 */ <<
321 <<
322 .macro dbit_20 code <<
323 <<
324 mfctl %isr,spc <<
325 #ifdef CONFIG_64BIT <<
326 b dbit_trap_20w <<
327 #else <<
328 b dbit_trap_20 <<
329 #endif <<
330 mfctl %ior,va <<
331 <<
332 .align 32 <<
333 .endm <<
334 <<
335 /* In LP64, the space contains part of <<
336 * fault. We have to extract this and <<
337 * zeroing the corresponding bits in t <<
338 .macro space_adjust spc,va <<
339 #ifdef CONFIG_64BIT <<
340 extrd,u \spc,63,SPACEID_SHIFT, <<
341 depd %r0,63,SPACEID_SHIFT,\ <<
342 depd \tmp,31,SPACEID_SHIFT, <<
343 #endif <<
344 .endm <<
345 <<
346 .import swapper_pg_dir,code <<
347 <<
348 /* Get the pgd. For faults on space z <<
349 * is simply swapper_pg_dir. For user <<
350 * pgd is stored in %cr25 */ <<
351 .macro get_pgd spc,re <<
352 ldil L%PA(swapper_pg_dir),\ <<
353 ldo R%PA(swapper_pg_dir)(\ <<
354 or,COND(=) %r0,\spc,%r0 <<
355 mfctl %cr25,\reg <<
356 .endm <<
357 <<
358 /* <<
359 space_check(spc,tmp,fault) <<
360 <<
361 spc - The space we saw the fau <<
362 tmp - The place to store the c <<
363 fault - Function to call on fa <<
364 <<
365 Only allow faults on different <<
366 currently active one if we're <<
367 <<
368 */ <<
369 .macro space_check spc,tm <<
370 mfsp %sr7,\tmp <<
371 /* check against %r0 which is same val <<
372 or,COND(<>) %r0,\spc,%r0 /* use <<
373 * as <<
374 * che <<
375 copy \spc,\tmp <<
376 or,COND(=) %r0,\tmp,%r0 /* nul <<
377 cmpb,COND(<>),n \tmp,\spc,\fault <<
378 .endm <<
379 <<
380 /* Look up a PTE in a 2-Level scheme ( <<
381 * level if the entry isn't present <<
382 * 438 *
383 * NOTE: we use ldw even for LP64, sin !! 439 * DATA 0: [low 32-bits] Address of function to call, jmp to this
384 * can address up to 1TB !! 440 * [high 32-bits] MMU Context Argument 0, place in %g5
385 */ !! 441 * DATA 1: Address Argument 1, place in %g6
386 .macro L2_ptep pmd,pte,index, !! 442 * DATA 2: Address Argument 2, place in %g7
387 #if CONFIG_PGTABLE_LEVELS == 3 <<
388 extru_safe \va,31-ASM_PMD_SHIFT,A <<
389 #else <<
390 extru_safe \va,31-ASM_PGDIR_SHIFT <<
391 #endif <<
392 dep %r0,31,PAGE_SHIFT,\pmd <<
393 #if CONFIG_PGTABLE_LEVELS < 3 <<
394 copy %r0,\pte <<
395 #endif <<
396 ldw,s \index(\pmd),\pmd <<
397 bb,>=,n \pmd,_PxD_PRESENT_BIT, <<
398 dep %r0,31,PxD_FLAG_SHIFT, <<
399 SHLREG \pmd,PxD_VALUE_SHIFT,\ <<
400 extru_safe \va,31-PAGE_SHIFT,ASM_ <<
401 dep %r0,31,PAGE_SHIFT,\pmd <<
402 shladd \index,BITS_PER_PTE_EN <<
403 .endm <<
404 <<
405 /* Look up PTE in a 3-Level scheme. */ <<
406 .macro L3_ptep pgd,pte,index, <<
407 #if CONFIG_PGTABLE_LEVELS == 3 <<
408 copy %r0,\pte <<
409 extrd,u \va,63-ASM_PGDIR_SHIFT <<
410 ldw,s \index(\pgd),\pgd <<
411 bb,>=,n \pgd,_PxD_PRESENT_BIT, <<
412 shld \pgd,PxD_VALUE_SHIFT,\ <<
413 #endif <<
414 L2_ptep \pgd,\pte,\index,\va,\ <<
415 .endm <<
416 <<
417 /* Acquire page_table_lock and check p <<
418 .macro ptl_lock spc,pt <<
419 #ifdef CONFIG_TLB_PTLOCK <<
420 98: cmpib,COND(=),n 0,\spc,2f <<
421 get_ptl \tmp <<
422 1: LDCW 0(\tmp),\tmp1 <<
423 cmpib,COND(=) 0,\tmp1,1b <<
424 nop <<
425 LDREG 0(\ptp),\pte <<
426 bb,<,n \pte,_PAGE_PRESENT_BIT <<
427 b \fault <<
428 stw \tmp1,0(\tmp) <<
429 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, <<
430 #endif <<
431 2: LDREG 0(\ptp),\pte <<
432 bb,>=,n \pte,_PAGE_PRESENT_BIT <<
433 3: <<
434 .endm <<
435 <<
436 /* Release page_table_lock if for user <<
437 store to ensure all prior accesses <<
438 releasing the lock. Note stw may no <<
439 provide one extra nop when CONFIG_T <<
440 .macro ptl_unlock spc,tm <<
441 #ifdef CONFIG_TLB_PTLOCK <<
442 98: get_ptl \tmp <<
443 ldi __ARCH_SPIN_LOCK_UNLOC <<
444 or,COND(=) %r0,\spc,%r0 <<
445 stw,ma \tmp2,0(\tmp) <<
446 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, <<
447 insert_nops NUM_PIPELINE_INSNS - 4 <<
448 #else <<
449 insert_nops NUM_PIPELINE_INSNS - 1 <<
450 #endif <<
451 .endm <<
452 <<
453 /* Set the _PAGE_ACCESSED bit of the P <<
454 * don't needlessly dirty the cache li <<
455 .macro update_accessed ptp,pt <<
456 ldi _PAGE_ACCESSED,\tmp1 <<
457 or \tmp1,\pte,\tmp <<
458 and,COND(<>) \tmp1,\pte,%r0 <<
459 STREG \tmp,0(\ptp) <<
460 .endm <<
461 <<
462 /* Set the dirty bit (and accessed bit <<
463 * clever, this is only used from the <<
464 .macro update_dirty ptp,pt <<
465 ldi _PAGE_ACCESSED|_PAGE_D <<
466 or \tmp,\pte,\pte <<
467 STREG \pte,0(\ptp) <<
468 .endm <<
469 <<
470 /* We have (depending on the page size <<
471 * - 38 to 52-bit Physical Page Number <<
472 * - 12 to 26-bit page offset <<
473 */ <<
474 /* bitshift difference between a PFN ( <<
475 * to a CPU TLB 4k PFN (4k => 12 bits <<
476 #define PAGE_ADD_SHIFT (PAGE_ <<
477 #define PAGE_ADD_HUGE_SHIFT (REAL_ <<
478 #define PFN_START_BIT (63-ASM_PFN_PT <<
479 <<
480 /* Drop prot bits and convert to page <<
481 .macro convert_for_tlb_insert <<
482 #ifdef CONFIG_HUGETLB_PAGE <<
483 copy \pte,\tmp <<
484 extrd,u \tmp,PFN_START_BIT,PFN <<
485 <<
486 depdi _PAGE_SIZE_ENCODING_DE <<
487 (63-58)+PAGE_A <<
488 extrd,u,*= \tmp,_PAGE_HPAGE_BIT+3 <<
489 depdi _HUGE_PAGE_SIZE_ENCODI <<
490 (63-58)+PAGE_A <<
491 #else /* Huge pages disabled */ <<
492 extrd,u \pte,PFN_START_BIT,PFN <<
493 depdi _PAGE_SIZE_ENCODING_DE <<
494 (63-58)+PAGE_A <<
495 #endif <<
496 .endm <<
497 <<
498 /* Convert the pte and prot to tlb ins <<
499 * this happens is quite subtle, read <<
500 .macro make_insert_tlb spc,pt <<
501 space_to_prot \spc \prot /* c <<
502 /* The following is the real subtlety. <<
503 * T <-> _PAGE_REFTRAP <<
504 * D <-> _PAGE_DIRTY <<
505 * B <-> _PAGE_DMB (memory break) <<
506 * <<
507 * Then incredible subtlety: The acces <<
508 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE <<
509 * See 3-14 of the parisc 2.0 manual <<
510 * <<
511 * Finally, _PAGE_READ goes in the top <<
512 * trigger an access rights trap in us <<
513 * tries to read an unreadable page */ <<
514 #if _PAGE_SPECIAL_BIT == _PAGE_DMB_BIT <<
515 /* need to drop DMB bit, as it's used <<
516 depi 0,_PAGE_SPECIAL_BIT,1, <<
517 #endif <<
518 depd \pte,8,7,\prot <<
519 <<
520 /* PAGE_USER indicates the page can be <<
521 * so deposit X1|11 to PL1|PL2 (rememb <<
522 * contains _PAGE_READ) */ <<
523 extrd,u,*= \pte,_PAGE_USER_BIT+32 <<
524 depdi 7,11,3,\prot <<
525 /* If we're a gateway page, drop PL2 b <<
526 * to kernel privilege (so we can exec <<
527 * Any privilege promotion page always <<
528 extrd,u,*= \pte,_PAGE_GATEWAY_BIT <<
529 depd %r0,11,2,\prot /* If <<
530 <<
531 /* Enforce uncacheable pages. <<
532 * This should ONLY be use for MMIO on <<
533 * Memory/DMA is cache coherent on all <<
534 * (that means T-class is NOT supporte <<
535 * on most of those machines only hand <<
536 */ <<
537 extrd,u,*= \pte,_PAGE_NO_CACHE_BI <<
538 depdi 1,12,1,\prot <<
539 <<
540 /* Drop prot bits and convert to page <<
541 convert_for_tlb_insert20 \pte \tmp <<
542 .endm <<
543 <<
544 /* Identical macro to make_insert_tlb <<
545 * makes the tlb entry for the differe <<
546 * insertion instructions */ <<
547 .macro make_insert_tlb_11 <<
548 #if _PAGE_SPECIAL_BIT == _PAGE_DMB_BIT <<
549 /* need to drop DMB bit, as it's used <<
550 depi 0,_PAGE_SPECIAL_BIT,1, <<
551 #endif <<
552 zdep \spc,30,15,\prot <<
553 dep \pte,8,7,\prot <<
554 extru,= \pte,_PAGE_NO_CACHE_BI <<
555 depi 1,12,1,\prot <<
556 extru,= \pte,_PAGE_USER_BIT,1, <<
557 depi 7,11,3,\prot /* Set <<
558 extru,= \pte,_PAGE_GATEWAY_BIT <<
559 depi 0,11,2,\prot /* If <<
560 <<
561 /* Get rid of prot bits and convert to <<
562 <<
563 depi 0,31,ASM_PFN_PTE_SHIFT <<
564 SHRREG \pte,(ASM_PFN_PTE_SHIF <<
565 .endm <<
566 <<
567 /* This is for ILP32 PA2.0 only. The <<
568 * to extend into I/O space if the add <<
569 * so we extend the f's into the top w <<
570 * this case */ <<
571 .macro f_extend pte,tm <<
572 extrd,s \pte,42,4,\tmp <<
573 addi,<> 1,\tmp,%r0 <<
574 extrd,s \pte,63,25,\pte <<
575 .endm <<
576 <<
577 /* The alias region is comprised of a <<
578 * aligned to 8 MB. It is used to clea <<
579 * using kernel virtual addresses cong <<
580 * virtual address. <<
581 * 443 *
582 * To use the alias page, you set %r26 !! 444 * With this method we can do most of the cross-call tlb/cache
583 * entry (identifying the physical pag !! 445 * flushing very quickly.
584 * the from tlb entry (or nothing if o <<
585 * clear_user_page_asm) */ <<
586 .macro do_alias spc,tm <<
587 cmpib,COND(<>),n 0,\spc,\fault <<
588 ldil L%(TMPALIAS_MAP_START) <<
589 copy \va,\tmp1 <<
590 depi_safe 0,31,TMPALIAS_SIZE_BIT <<
591 cmpb,COND(<>),n \tmp,\tmp1,\fault <<
592 mfctl %cr19,\tmp /* iir <<
593 /* get the opcode (first six bits) int <<
594 extrw,u \tmp,5,6,\tmp <<
595 /* <<
596 * Only setting the T bit prevents dat <<
597 * Setting access rights to zero preve <<
598 * 446 *
599 * Note subtlety here: _PAGE_GATEWAY, !! 447 * Current CPU's IRQ worklist table is locked into %g1,
600 * to type field and _PAGE_READ goes t !! 448 * don't touch.
601 */ 449 */
602 ldi (_PAGE_REFTRAP|_PAGE_R !! 450 .text
603 /* !! 451 .align 32
604 * so if the opcode is one (i.e. this !! 452 .globl do_ivec
605 * instruction) nullify the next load !! 453 do_ivec:
606 * Otherwise this is a normal data ope !! 454 mov 0x40, %g3
607 */ !! 455 ldxa [%g3 + %g0] ASI_INTR_R, %g3
608 cmpiclr,= 0x01,\tmp,%r0 !! 456 sethi %hi(KERNBASE), %g4
609 ldi (_PAGE_DIRTY|_PAGE_REA !! 457 cmp %g3, %g4
610 .ifc \patype,20 !! 458 bgeu,pn %xcc, do_ivec_xcall
611 depd,z \prot,8,7,\prot !! 459 srlx %g3, 32, %g5
612 .else !! 460 stxa %g0, [%g0] ASI_INTR_RECEIVE
613 .ifc \patype,11 !! 461 membar #Sync
614 depw,z \prot,8,7,\prot !! 462
615 .else !! 463 sethi %hi(ivector_table), %g2
616 .error "undefined PA type to do_alias" !! 464 sllx %g3, 5, %g3
617 .endif !! 465 or %g2, %lo(ivector_table), %g2
618 .endif !! 466 add %g2, %g3, %g3
619 /* !! 467 ldx [%g3 + 0x08], %g2 /* irq_info */
620 * OK, it is in the temp alias region, !! 468 ldub [%g3 + 0x04], %g4 /* pil */
621 * Check "subtle" note in pacache.S re !! 469 brz,pn %g2, do_ivec_spurious
622 */ !! 470 mov 1, %g2
623 extrw,u,= \va,31-TMPALIAS_SIZE_B !! 471
624 or,COND(tr) %r23,%r0,\pte !! 472 sllx %g2, %g4, %g2
625 or %r26,%r0,\pte !! 473 sllx %g4, 2, %g4
626 !! 474 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
627 /* convert phys addr in \pte (from r23 !! 475 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
628 SHRREG \pte,PAGE_SHIFT+PAGE_A !! 476 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
629 depi_safe _PAGE_SIZE_ENCODING_DE !! 477 wr %g2, 0x0, %set_softint
630 .endm !! 478 retry
631 !! 479 do_ivec_xcall:
632 !! 480 mov 0x50, %g1
633 /* !! 481
634 * Fault_vectors are architecturally r !! 482 ldxa [%g1 + %g0] ASI_INTR_R, %g1
635 * boundary !! 483 srl %g3, 0, %g3
636 */ !! 484 mov 0x60, %g7
637 !! 485 ldxa [%g7 + %g0] ASI_INTR_R, %g7
638 .section .text.hot !! 486 stxa %g0, [%g0] ASI_INTR_RECEIVE
639 .align 2048 !! 487 membar #Sync
640 !! 488 ba,pt %xcc, 1f
641 ENTRY(fault_vector_20) !! 489 nop
642 /* First vector is invalid (0) */ <<
643 .ascii "cows can fly" <<
644 .byte 0 <<
645 .align 32 <<
646 <<
647 hpmc 1 <<
648 def 2 <<
649 def 3 <<
650 extint 4 <<
651 def 5 <<
652 itlb_20 PARISC_ITLB_TRAP <<
653 def 7 <<
654 def 8 <<
655 def 9 <<
656 def 10 <<
657 def 11 <<
658 def 12 <<
659 def 13 <<
660 def 14 <<
661 dtlb_20 15 <<
662 naitlb_20 16 <<
663 nadtlb_20 17 <<
664 def 18 <<
665 def 19 <<
666 dbit_20 20 <<
667 def 21 <<
668 def 22 <<
669 def 23 <<
670 def 24 <<
671 def 25 <<
672 def 26 <<
673 def 27 <<
674 def 28 <<
675 def 29 <<
676 def 30 <<
677 def 31 <<
678 END(fault_vector_20) <<
679 <<
680 #ifndef CONFIG_64BIT <<
681 <<
682 .align 2048 <<
683 <<
684 ENTRY(fault_vector_11) <<
685 /* First vector is invalid (0) */ <<
686 .ascii "cows can fly" <<
687 .byte 0 <<
688 .align 32 <<
689 <<
690 hpmc 1 <<
691 def 2 <<
692 def 3 <<
693 extint 4 <<
694 def 5 <<
695 itlb_11 PARISC_ITLB_TRAP <<
696 def 7 <<
697 def 8 <<
698 def 9 <<
699 def 10 <<
700 def 11 <<
701 def 12 <<
702 def 13 <<
703 def 14 <<
704 dtlb_11 15 <<
705 naitlb_11 16 <<
706 nadtlb_11 17 <<
707 def 18 <<
708 def 19 <<
709 dbit_11 20 <<
710 def 21 <<
711 def 22 <<
712 def 23 <<
713 def 24 <<
714 def 25 <<
715 def 26 <<
716 def 27 <<
717 def 28 <<
718 def 29 <<
719 def 30 <<
720 def 31 <<
721 END(fault_vector_11) <<
722 <<
723 #endif <<
724 /* Fault vector is separately protecte <<
725 .align PAGE_SIZE <<
726 490
727 .import handle_interruption,co !! 491 .align 32
728 .import do_cpu_irq_mask,code !! 492 1: jmpl %g3, %g0
>> 493 nop
729 494
730 /* !! 495 do_ivec_spurious:
731 * Child Returns here !! 496 stw %g3, [%g6 + 0x00] /* irq_work(cpu, 0) = bucket */
>> 497 rdpr %pstate, %g5
>> 498
>> 499 wrpr %g5, PSTATE_IG | PSTATE_AG, %pstate
>> 500 sethi %hi(109f), %g7
>> 501 ba,pt %xcc, etrap
>> 502 109: or %g7, %lo(109b), %g7
>> 503 call catch_disabled_ivec
>> 504 add %sp, PTREGS_OFF, %o0
>> 505 ba,pt %xcc, rtrap
>> 506 clr %l6
>> 507
>> 508 .globl save_alternate_globals
>> 509 save_alternate_globals: /* %o0 = save_area */
>> 510 rdpr %pstate, %o5
>> 511 andn %o5, PSTATE_IE, %o1
>> 512 wrpr %o1, PSTATE_AG, %pstate
>> 513 stx %g0, [%o0 + 0x00]
>> 514 stx %g1, [%o0 + 0x08]
>> 515 stx %g2, [%o0 + 0x10]
>> 516 stx %g3, [%o0 + 0x18]
>> 517 stx %g4, [%o0 + 0x20]
>> 518 stx %g5, [%o0 + 0x28]
>> 519 stx %g6, [%o0 + 0x30]
>> 520 stx %g7, [%o0 + 0x38]
>> 521 wrpr %o1, PSTATE_IG, %pstate
>> 522 stx %g0, [%o0 + 0x40]
>> 523 stx %g1, [%o0 + 0x48]
>> 524 stx %g2, [%o0 + 0x50]
>> 525 stx %g3, [%o0 + 0x58]
>> 526 stx %g4, [%o0 + 0x60]
>> 527 stx %g5, [%o0 + 0x68]
>> 528 stx %g6, [%o0 + 0x70]
>> 529 stx %g7, [%o0 + 0x78]
>> 530 wrpr %o1, PSTATE_MG, %pstate
>> 531 stx %g0, [%o0 + 0x80]
>> 532 stx %g1, [%o0 + 0x88]
>> 533 stx %g2, [%o0 + 0x90]
>> 534 stx %g3, [%o0 + 0x98]
>> 535 stx %g4, [%o0 + 0xa0]
>> 536 stx %g5, [%o0 + 0xa8]
>> 537 stx %g6, [%o0 + 0xb0]
>> 538 stx %g7, [%o0 + 0xb8]
>> 539 wrpr %o5, 0x0, %pstate
>> 540 retl
>> 541 nop
>> 542
>> 543 .globl restore_alternate_globals
>> 544 restore_alternate_globals: /* %o0 = save_area */
>> 545 rdpr %pstate, %o5
>> 546 andn %o5, PSTATE_IE, %o1
>> 547 wrpr %o1, PSTATE_AG, %pstate
>> 548 ldx [%o0 + 0x00], %g0
>> 549 ldx [%o0 + 0x08], %g1
>> 550 ldx [%o0 + 0x10], %g2
>> 551 ldx [%o0 + 0x18], %g3
>> 552 ldx [%o0 + 0x20], %g4
>> 553 ldx [%o0 + 0x28], %g5
>> 554 ldx [%o0 + 0x30], %g6
>> 555 ldx [%o0 + 0x38], %g7
>> 556 wrpr %o1, PSTATE_IG, %pstate
>> 557 ldx [%o0 + 0x40], %g0
>> 558 ldx [%o0 + 0x48], %g1
>> 559 ldx [%o0 + 0x50], %g2
>> 560 ldx [%o0 + 0x58], %g3
>> 561 ldx [%o0 + 0x60], %g4
>> 562 ldx [%o0 + 0x68], %g5
>> 563 ldx [%o0 + 0x70], %g6
>> 564 ldx [%o0 + 0x78], %g7
>> 565 wrpr %o1, PSTATE_MG, %pstate
>> 566 ldx [%o0 + 0x80], %g0
>> 567 ldx [%o0 + 0x88], %g1
>> 568 ldx [%o0 + 0x90], %g2
>> 569 ldx [%o0 + 0x98], %g3
>> 570 ldx [%o0 + 0xa0], %g4
>> 571 ldx [%o0 + 0xa8], %g5
>> 572 ldx [%o0 + 0xb0], %g6
>> 573 ldx [%o0 + 0xb8], %g7
>> 574 wrpr %o5, 0x0, %pstate
>> 575 retl
>> 576 nop
>> 577
>> 578 .globl getcc, setcc
>> 579 getcc:
>> 580 ldx [%o0 + PT_V9_TSTATE], %o1
>> 581 srlx %o1, 32, %o1
>> 582 and %o1, 0xf, %o1
>> 583 retl
>> 584 stx %o1, [%o0 + PT_V9_G1]
>> 585 setcc:
>> 586 ldx [%o0 + PT_V9_TSTATE], %o1
>> 587 ldx [%o0 + PT_V9_G1], %o2
>> 588 or %g0, %ulo(TSTATE_ICC), %o3
>> 589 sllx %o3, 32, %o3
>> 590 andn %o1, %o3, %o1
>> 591 sllx %o2, 32, %o2
>> 592 and %o2, %o3, %o2
>> 593 or %o1, %o2, %o1
>> 594 retl
>> 595 stx %o1, [%o0 + PT_V9_TSTATE]
>> 596
>> 597 .globl utrap, utrap_ill
>> 598 utrap: brz,pn %g1, etrap
>> 599 nop
>> 600 save %sp, -128, %sp
>> 601 rdpr %tstate, %l6
>> 602 rdpr %cwp, %l7
>> 603 andn %l6, TSTATE_CWP, %l6
>> 604 wrpr %l6, %l7, %tstate
>> 605 rdpr %tpc, %l6
>> 606 rdpr %tnpc, %l7
>> 607 wrpr %g1, 0, %tnpc
>> 608 done
>> 609 utrap_ill:
>> 610 call bad_trap
>> 611 add %sp, PTREGS_OFF, %o0
>> 612 ba,pt %xcc, rtrap
>> 613 clr %l6
>> 614
>> 615 #ifdef CONFIG_BLK_DEV_FD
>> 616 .globl floppy_hardint
>> 617 floppy_hardint:
>> 618 wr %g0, (1 << 11), %clear_softint
>> 619 sethi %hi(doing_pdma), %g1
>> 620 ld [%g1 + %lo(doing_pdma)], %g2
>> 621 brz,pn %g2, floppy_dosoftint
>> 622 sethi %hi(fdc_status), %g3
>> 623 ldx [%g3 + %lo(fdc_status)], %g3
>> 624 sethi %hi(pdma_vaddr), %g5
>> 625 ldx [%g5 + %lo(pdma_vaddr)], %g4
>> 626 sethi %hi(pdma_size), %g5
>> 627 ldx [%g5 + %lo(pdma_size)], %g5
>> 628
>> 629 next_byte:
>> 630 lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7
>> 631 andcc %g7, 0x80, %g0
>> 632 be,pn %icc, floppy_fifo_emptied
>> 633 andcc %g7, 0x20, %g0
>> 634 be,pn %icc, floppy_overrun
>> 635 andcc %g7, 0x40, %g0
>> 636 be,pn %icc, floppy_write
>> 637 sub %g5, 1, %g5
>> 638
>> 639 inc %g3
>> 640 lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7
>> 641 dec %g3
>> 642 orcc %g0, %g5, %g0
>> 643 stb %g7, [%g4]
>> 644 bne,pn %xcc, next_byte
>> 645 add %g4, 1, %g4
>> 646
>> 647 b,pt %xcc, floppy_tdone
>> 648 nop
>> 649
>> 650 floppy_write:
>> 651 ldub [%g4], %g7
>> 652 orcc %g0, %g5, %g0
>> 653 inc %g3
>> 654 stba %g7, [%g3] ASI_PHYS_BYPASS_EC_E
>> 655 dec %g3
>> 656 bne,pn %xcc, next_byte
>> 657 add %g4, 1, %g4
>> 658
>> 659 floppy_tdone:
>> 660 sethi %hi(pdma_vaddr), %g1
>> 661 stx %g4, [%g1 + %lo(pdma_vaddr)]
>> 662 sethi %hi(pdma_size), %g1
>> 663 stx %g5, [%g1 + %lo(pdma_size)]
>> 664 sethi %hi(auxio_register), %g1
>> 665 ldx [%g1 + %lo(auxio_register)], %g7
>> 666 lduba [%g7] ASI_PHYS_BYPASS_EC_E, %g5
>> 667 or %g5, AUXIO_AUX1_FTCNT, %g5
>> 668 /* andn %g5, AUXIO_AUX1_MASK, %g5 */
>> 669 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E
>> 670 andn %g5, AUXIO_AUX1_FTCNT, %g5
>> 671 /* andn %g5, AUXIO_AUX1_MASK, %g5 */
>> 672
>> 673 nop; nop; nop; nop; nop; nop;
>> 674 nop; nop; nop; nop; nop; nop;
>> 675
>> 676 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E
>> 677 sethi %hi(doing_pdma), %g1
>> 678 b,pt %xcc, floppy_dosoftint
>> 679 st %g0, [%g1 + %lo(doing_pdma)]
>> 680
>> 681 floppy_fifo_emptied:
>> 682 sethi %hi(pdma_vaddr), %g1
>> 683 stx %g4, [%g1 + %lo(pdma_vaddr)]
>> 684 sethi %hi(pdma_size), %g1
>> 685 stx %g5, [%g1 + %lo(pdma_size)]
>> 686 sethi %hi(irq_action), %g1
>> 687 or %g1, %lo(irq_action), %g1
>> 688 ldx [%g1 + (11 << 3)], %g3 ! irqaction[floppy_irq]
>> 689 ldx [%g3 + 0x08], %g4 ! action->flags>>48==ino
>> 690 sethi %hi(ivector_table), %g3
>> 691 srlx %g4, 48, %g4
>> 692 or %g3, %lo(ivector_table), %g3
>> 693 sllx %g4, 5, %g4
>> 694 ldx [%g3 + %g4], %g4 ! &ivector_table[ino]
>> 695 ldx [%g4 + 0x10], %g4 ! bucket->iclr
>> 696 stwa %g0, [%g4] ASI_PHYS_BYPASS_EC_E ! ICLR_IDLE
>> 697 membar #Sync ! probably not needed...
>> 698 retry
>> 699
>> 700 floppy_overrun:
>> 701 sethi %hi(pdma_vaddr), %g1
>> 702 stx %g4, [%g1 + %lo(pdma_vaddr)]
>> 703 sethi %hi(pdma_size), %g1
>> 704 stx %g5, [%g1 + %lo(pdma_size)]
>> 705 sethi %hi(doing_pdma), %g1
>> 706 st %g0, [%g1 + %lo(doing_pdma)]
>> 707
>> 708 floppy_dosoftint:
>> 709 rdpr %pil, %g2
>> 710 wrpr %g0, 15, %pil
>> 711 sethi %hi(109f), %g7
>> 712 b,pt %xcc, etrap_irq
>> 713 109: or %g7, %lo(109b), %g7
>> 714
>> 715 mov 11, %o0
>> 716 mov 0, %o1
>> 717 call sparc_floppy_irq
>> 718 add %sp, PTREGS_OFF, %o2
>> 719
>> 720 b,pt %xcc, rtrap
>> 721 clr %l6
>> 722
>> 723 #endif /* CONFIG_BLK_DEV_FD */
>> 724
>> 725 /* XXX Here is stuff we still need to write... -DaveM XXX */
>> 726 .globl netbsd_syscall
>> 727 netbsd_syscall:
>> 728 retl
>> 729 nop
>> 730
>> 731 /* We need to carefully read the error status, ACK
>> 732 * the errors, prevent recursive traps, and pass the
>> 733 * information on to C code for logging.
732 * 734 *
733 * copy_thread moved args into task sa !! 735 * We pass the AFAR in as-is, and we encode the status
>> 736 * information as described in asm-sparc64/sfafsr.h
734 */ 737 */
735 !! 738 .globl __spitfire_access_error
736 ENTRY(ret_from_kernel_thread) !! 739 __spitfire_access_error:
737 /* Call schedule_tail first though */ !! 740 /* Disable ESTATE error reporting so that we do not
738 BL schedule_tail, %r2 !! 741 * take recursive traps and RED state the processor.
739 nop !! 742 */
740 !! 743 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
741 mfctl %cr30,%r1 /* task_struct !! 744 membar #Sync
742 LDREG TASK_PT_GR25(%r1), %r26 !! 745
743 #ifdef CONFIG_64BIT !! 746 mov UDBE_UE, %g1
744 LDREG TASK_PT_GR27(%r1), %r27 !! 747 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
745 #endif !! 748
746 LDREG TASK_PT_GR26(%r1), %r1 !! 749 /* __spitfire_cee_trap branches here with AFSR in %g4 and
747 ble 0(%sr7, %r1) !! 750 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
748 copy %r31, %r2 !! 751 * ESTATE Error Enable register.
749 b finish_child_return !! 752 */
750 nop !! 753 __spitfire_cee_trap_continue:
751 END(ret_from_kernel_thread) !! 754 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
752 !! 755
753 !! 756 rdpr %tt, %g3
754 /* !! 757 and %g3, 0x1ff, %g3 ! Paranoia
755 * struct task_struct *_switch_to(stru !! 758 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
756 * struct task_struct *next) !! 759 or %g4, %g3, %g4
>> 760 rdpr %tl, %g3
>> 761 cmp %g3, 1
>> 762 mov 1, %g3
>> 763 bleu %xcc, 1f
>> 764 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
>> 765
>> 766 or %g4, %g3, %g4
>> 767
>> 768 /* Read in the UDB error register state, clearing the
>> 769 * sticky error bits as-needed. We only clear them if
>> 770 * the UE bit is set. Likewise, __spitfire_cee_trap
>> 771 * below will only do so if the CE bit is set.
757 * 772 *
758 * switch kernel stacks and return pre !! 773 * NOTE: UltraSparc-I/II have high and low UDB error
759 ENTRY_CFI(_switch_to) !! 774 * registers, corresponding to the two UDB units
760 STREG %r2, -RP_OFFSET(%r30) !! 775 * present on those chips. UltraSparc-IIi only
761 !! 776 * has a single UDB, called "SDB" in the manual.
762 callee_save_float !! 777 * For IIi the upper UDB register always reads
763 callee_save !! 778 * as zero so for our purposes things will just
764 !! 779 * work with the checks below.
765 load32 _switch_to_ret, %r2 !! 780 */
766 !! 781 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
767 STREG %r2, TASK_PT_KPC(%r26) !! 782 and %g3, 0x3ff, %g7 ! Paranoia
768 LDREG TASK_PT_KPC(%r25), %r2 !! 783 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
769 !! 784 or %g4, %g7, %g4
770 STREG %r30, TASK_PT_KSP(%r26) !! 785 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
771 LDREG TASK_PT_KSP(%r25), %r30 !! 786 be,pn %xcc, 1f
772 bv %r0(%r2) !! 787 nop
773 mtctl %r25,%cr30 !! 788 stxa %g3, [%g0] ASI_UDB_ERROR_W
774 !! 789 membar #Sync
775 ENTRY(_switch_to_ret) !! 790
776 mtctl %r0, %cr0 /* Nee !! 791 1: mov 0x18, %g3
777 callee_rest !! 792 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
778 callee_rest_float !! 793 and %g3, 0x3ff, %g7 ! Paranoia
779 !! 794 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
780 LDREG -RP_OFFSET(%r30), %r2 !! 795 or %g4, %g7, %g4
781 bv %r0(%r2) !! 796 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
782 copy %r26, %r28 !! 797 be,pn %xcc, 1f
783 ENDPROC_CFI(_switch_to) !! 798 nop
784 !! 799 mov 0x18, %g7
785 /* !! 800 stxa %g3, [%g7] ASI_UDB_ERROR_W
786 * Common rfi return path for interrup !! 801 membar #Sync
787 * sys_rt_sigreturn (sometimes). The !! 802
788 * return via this path if the signal !! 803 1: /* Ok, now that we've latched the error state,
789 * was running; if the process was blo !! 804 * clear the sticky bits in the AFSR.
790 * normal syscall_exit path is used. !! 805 */
791 * proceses exit via intr_restore. !! 806 stxa %g4, [%g0] ASI_AFSR
>> 807 membar #Sync
>> 808
>> 809 rdpr %tl, %g2
>> 810 cmp %g2, 1
>> 811 rdpr %pil, %g2
>> 812 bleu,pt %xcc, 1f
>> 813 wrpr %g0, 15, %pil
>> 814
>> 815 ba,pt %xcc, etraptl1
>> 816 rd %pc, %g7
>> 817
>> 818 ba,pt %xcc, 2f
>> 819 nop
>> 820
>> 821 1: ba,pt %xcc, etrap_irq
>> 822 rd %pc, %g7
>> 823
>> 824 2: mov %l4, %o1
>> 825 mov %l5, %o2
>> 826 call spitfire_access_error
>> 827 add %sp, PTREGS_OFF, %o0
>> 828 ba,pt %xcc, rtrap
>> 829 clr %l6
>> 830
>> 831 /* This is the trap handler entry point for ECC correctable
>> 832 * errors. They are corrected, but we listen for the trap
>> 833 * so that the event can be logged.
792 * 834 *
793 * XXX If any syscalls that change a p !! 835 * Disrupting errors are either:
794 * this way, then we will need to copy !! 836 * 1) single-bit ECC errors during UDB reads to system
795 * adjust IASQ[0..1]. !! 837 * memory
>> 838 * 2) data parity errors during write-back events
796 * 839 *
797 */ !! 840 * As far as I can make out from the manual, the CEE trap
798 !! 841 * is only for correctable errors during memory read
799 .align PAGE_SIZE !! 842 * accesses by the front-end of the processor.
800 <<
801 ENTRY_CFI(syscall_exit_rfi) <<
802 mfctl %cr30,%r16 /* tas <<
803 ldo TASK_REGS(%r16),%r16 <<
804 /* Force iaoq to userspace, as the use <<
805 * context via sigcontext. Also Filter <<
806 */ <<
807 LDREG PT_IAOQ0(%r16),%r19 <<
808 depi PRIV_USER,31,2,%r19 <<
809 STREG %r19,PT_IAOQ0(%r16) <<
810 LDREG PT_IAOQ1(%r16),%r19 <<
811 depi PRIV_USER,31,2,%r19 <<
812 STREG %r19,PT_IAOQ1(%r16) <<
813 LDREG PT_PSW(%r16),%r19 <<
814 load32 USER_PSW_MASK,%r1 <<
815 #ifdef CONFIG_64BIT <<
816 load32 USER_PSW_HI_MASK,%r20 <<
817 depd %r20,31,32,%r1 <<
818 #endif <<
819 and %r19,%r1,%r19 /* Mask out bits <<
820 load32 USER_PSW,%r1 <<
821 or %r19,%r1,%r19 /* Make sure def <<
822 STREG %r19,PT_PSW(%r16) <<
823 <<
824 /* <<
825 * If we aren't being traced, we never <<
826 * (we don't store them in the sigcont <<
827 * to "proper" values now (otherwise w <<
828 * whatever was last stored in the tas <<
829 * be inconsistent if an interrupt occ <<
830 * page). Note that we may be "trashin <<
831 * them, but we don't support the user <<
832 */ <<
833 <<
834 STREG %r0,PT_SR2(%r16) <<
835 mfsp %sr3,%r19 <<
836 STREG %r19,PT_SR0(%r16) <<
837 STREG %r19,PT_SR1(%r16) <<
838 STREG %r19,PT_SR3(%r16) <<
839 STREG %r19,PT_SR4(%r16) <<
840 STREG %r19,PT_SR5(%r16) <<
841 STREG %r19,PT_SR6(%r16) <<
842 STREG %r19,PT_SR7(%r16) <<
843 <<
844 ENTRY(intr_return) <<
845 /* check for reschedule */ <<
846 mfctl %cr30,%r1 <<
847 LDREG TASK_TI_FLAGS(%r1),%r19 /* sch <<
848 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_ <<
849 <<
850 .import do_notify_resume,code <<
851 intr_check_sig: <<
852 /* As above */ <<
853 mfctl %cr30,%r1 <<
854 LDREG TASK_TI_FLAGS(%r1),%r19 <<
855 ldi (_TIF_USER_WORK_MASK & ~_TIF_N <<
856 and,COND(<>) %r19, %r20, %r0 <<
857 b,n intr_restore /* skip past i <<
858 <<
859 /* This check is critical to having LW <<
860 * working. The IASQ is zero on the ga <<
861 * page and we cannot deliver any sign <<
862 * we get off the gateway page. <<
863 * 843 *
864 * Only do signals if we are returning !! 844 * The code below is only for trap level 1 CEE events,
865 */ !! 845 * as it is the only situation where we can safely record
866 LDREG PT_IASQ0(%r16), %r20 !! 846 * and log. For trap level >1 we just clear the CE bit
867 cmpib,COND(=),n LINUX_GATEWAY_SPACE, % !! 847 * in the AFSR and return.
868 LDREG PT_IASQ1(%r16), %r20 <<
869 cmpib,COND(=),n LINUX_GATEWAY_SPACE, % <<
870 <<
871 copy %r0, %r25 <<
872 #ifdef CONFIG_64BIT <<
873 ldo -16(%r30),%r29 <<
874 #endif <<
875 <<
876 /* NOTE: We need to enable interrupts <<
877 * signals. We used to do this earlier <<
878 * stack overflows. */ <<
879 ssm PSW_SM_I, %r0 <<
880 <<
881 BL do_notify_resume,%r2 <<
882 copy %r16, %r26 <<
883 <<
884 b,n intr_check_sig <<
885 <<
886 intr_restore: <<
887 copy %r16,%r29 <<
888 ldo PT_FR31(%r29),%r1 <<
889 rest_fp %r1 <<
890 rest_general %r29 <<
891 <<
892 /* inverse of virt_map */ <<
893 pcxt_ssm_bug <<
894 rsm PSW_SM_QUIET,%r0 <<
895 tophys_r1 %r29 <<
896 <<
897 /* Restore space id's and special cr's <<
898 * structure pointed to by r29 <<
899 */ <<
900 rest_specials %r29 <<
901 <<
902 /* IMPORTANT: rest_stack restores r29 <<
903 * It also restores r1 and r30. <<
904 */ <<
905 rest_stack <<
906 <<
907 rfi <<
908 nop <<
909 <<
910 #ifndef CONFIG_PREEMPTION <<
911 # define intr_do_preempt intr_restore <<
912 #endif /* !CONFIG_PREEMPTION */ <<
913 <<
914 .import schedule,code <<
915 intr_do_resched: <<
916 /* Only call schedule on return to use <<
917 * to kernel space, we may schedule if <<
918 * we jump back to intr_restore. <<
919 */ <<
920 LDREG PT_IASQ0(%r16), %r20 <<
921 cmpib,COND(=) 0, %r20, intr_do_preem <<
922 nop <<
923 LDREG PT_IASQ1(%r16), %r20 <<
924 cmpib,COND(=) 0, %r20, intr_do_preem <<
925 nop <<
926 <<
927 /* NOTE: We need to enable interrupts <<
928 * to do this earlier but it caused ke <<
929 ssm PSW_SM_I, %r0 <<
930 <<
931 #ifdef CONFIG_64BIT <<
932 ldo -16(%r30),%r29 /* Ref <<
933 #endif <<
934 <<
935 ldil L%intr_check_sig, %r2 <<
936 #ifndef CONFIG_64BIT <<
937 b schedule <<
938 #else <<
939 load32 schedule, %r20 <<
940 bv %r0(%r20) <<
941 #endif <<
942 ldo R%intr_check_sig(%r2), %r2 <<
943 <<
944 /* preempt the current task on returni <<
945 * mode from an interrupt, iff need_re <<
946 * and preempt_count is 0. otherwise, <<
947 * our merry way back to the current r <<
948 */ <<
949 #ifdef CONFIG_PREEMPTION <<
950 .import preempt_schedule_irq,code <<
951 intr_do_preempt: <<
952 rsm PSW_SM_I, %r0 /* dis <<
953 <<
954 /* current_thread_info()->preempt_coun <<
955 mfctl %cr30, %r1 <<
956 ldw TI_PRE_COUNT(%r1), %r19 <<
957 cmpib,<> 0, %r19, intr_restore <<
958 nop /* pre <<
959 <<
960 /* check if we interrupted a critical <<
961 LDREG PT_PSW(%r16), %r20 <<
962 bb,<,n %r20, 31 - PSW_SM_I, intr_rest <<
963 nop <<
964 <<
965 /* ssm PSW_SM_I done later in intr_res <<
966 #ifdef CONFIG_MLONGCALLS <<
967 ldil L%intr_restore, %r2 <<
968 load32 preempt_schedule_irq, %r1 <<
969 bv %r0(%r1) <<
970 ldo R%intr_restore(%r2), %r2 <<
971 #else <<
972 ldil L%intr_restore, %r1 <<
973 BL preempt_schedule_irq, %r2 <<
974 ldo R%intr_restore(%r1), %r2 <<
975 #endif <<
976 #endif /* CONFIG_PREEMPTION */ <<
977 <<
978 /* <<
979 * External interrupts. <<
980 */ <<
981 <<
982 intr_extint: <<
983 cmpib,COND(=),n 0,%r16,1f <<
984 <<
985 get_stack_use_cr30 <<
986 b,n 2f <<
987 <<
988 1: <<
989 get_stack_use_r30 <<
990 2: <<
991 save_specials %r29 <<
992 virt_map <<
993 save_general %r29 <<
994 <<
995 ldo PT_FR0(%r29), %r24 <<
996 save_fp %r24 <<
997 <<
998 loadgp <<
999 <<
1000 copy %r29, %r26 /* arg0 is pt <<
1001 copy %r29, %r16 /* save pt_re <<
1002 <<
1003 ldil L%intr_return, %r2 <<
1004 <<
1005 #ifdef CONFIG_64BIT <<
1006 ldo -16(%r30),%r29 /* Reference <<
1007 #endif <<
1008 <<
1009 b do_cpu_irq_mask <<
1010 ldo R%intr_return(%r2), %r2 /* re <<
1011 ENDPROC_CFI(syscall_exit_rfi) <<
1012 <<
1013 <<
1014 /* Generic interruptions (illegal ins <<
1015 <<
1016 ENTRY_CFI(intr_save) /* for os_hpm <<
1017 mfsp %sr7,%r16 <<
1018 cmpib,COND(=),n 0,%r16,1f <<
1019 get_stack_use_cr30 <<
1020 b 2f <<
1021 copy %r8,%r26 <<
1022 <<
1023 1: <<
1024 get_stack_use_r30 <<
1025 copy %r8,%r26 <<
1026 <<
1027 2: <<
1028 save_specials %r29 <<
1029 <<
1030 /* If this trap is a itlb miss, skip <<
1031 cmpib,COND(=),n PARISC_ITLB_TR <<
1032 <<
1033 <<
1034 mfctl %isr, %r16 <<
1035 nop /* serialize mfctl on <<
1036 mfctl %ior, %r17 <<
1037 <<
1038 <<
1039 #ifdef CONFIG_64BIT <<
1040 /* <<
1041 * If the interrupted code was runnin <<
1042 * clear the b bits (bits 0 & 1) in t <<
1043 * save_specials left ipsw value in r <<
1044 */ <<
1045 extrd,u,*<> %r8,PSW_W_BIT,1,%r0 <<
1046 depdi 0,1,2,%r17 <<
1047 <<
1048 /* adjust isr/ior: get high bits from <<
1049 space_adjust %r16,%r17,%r1 <<
1050 #endif <<
1051 STREG %r16, PT_ISR(%r29) <<
1052 STREG %r17, PT_IOR(%r29) <<
1053 <<
1054 #if defined(CONFIG_64BIT) <<
1055 b,n intr_save2 <<
1056 <<
1057 skip_save_ior: <<
1058 /* We have a itlb miss, and when exec <<
1059 * need to adjust iasq/iaoq here in t <<
1060 * above. <<
1061 */ <<
1062 bb,COND(>=),n %r8,PSW_W_BIT,intr_sa <<
1063 LDREG PT_IASQ0(%r29), %r16 <<
1064 LDREG PT_IAOQ0(%r29), %r17 <<
1065 /* adjust iasq/iaoq */ <<
1066 space_adjust %r16,%r17,%r1 <<
1067 STREG %r16, PT_IASQ0(%r29) <<
1068 STREG %r17, PT_IAOQ0(%r29) <<
1069 #else <<
1070 skip_save_ior: <<
1071 #endif <<
1072 <<
1073 intr_save2: <<
1074 virt_map <<
1075 save_general %r29 <<
1076 <<
1077 ldo PT_FR0(%r29), %r25 <<
1078 save_fp %r25 <<
1079 <<
1080 loadgp <<
1081 <<
1082 copy %r29, %r25 /* ar <<
1083 #ifdef CONFIG_64BIT <<
1084 ldo -16(%r30),%r29 /* Re <<
1085 #endif <<
1086 <<
1087 ldil L%intr_check_sig, %r2 <<
1088 copy %r25, %r16 /* sa <<
1089 <<
1090 b handle_interruption <<
1091 ldo R%intr_check_sig(%r2) <<
1092 ENDPROC_CFI(intr_save) <<
1093 <<
1094 <<
1095 /* <<
1096 * Note for all tlb miss handlers: <<
1097 * 848 *
1098 * cr24 contains a pointer to the ker !! 849 * This is just like __spiftire_access_error above, but it
1099 * page directory. !! 850 * specifically handles correctable errors. If an
>> 851 * uncorrectable error is indicated in the AFSR we
>> 852 * will branch directly above to __spitfire_access_error
>> 853 * to handle it instead. Uncorrectable therefore takes
>> 854 * priority over correctable, and the error logging
>> 855 * C code will notice this case by inspecting the
>> 856 * trap type.
>> 857 */
>> 858 .globl __spitfire_cee_trap
>> 859 __spitfire_cee_trap:
>> 860 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
>> 861 mov 1, %g3
>> 862 sllx %g3, SFAFSR_UE_SHIFT, %g3
>> 863 andcc %g4, %g3, %g0 ! Check for UE
>> 864 bne,pn %xcc, __spitfire_access_error
>> 865 nop
>> 866
>> 867 /* Ok, in this case we only have a correctable error.
>> 868 * Indicate we only wish to capture that state in register
>> 869 * %g1, and we only disable CE error reporting unlike UE
>> 870 * handling which disables all errors.
>> 871 */
>> 872 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
>> 873 andn %g3, ESTATE_ERR_CE, %g3
>> 874 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
>> 875 membar #Sync
>> 876
>> 877 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
>> 878 ba,pt %xcc, __spitfire_cee_trap_continue
>> 879 mov UDBE_CE, %g1
>> 880
>> 881 .globl __spitfire_data_access_exception
>> 882 .globl __spitfire_data_access_exception_tl1
>> 883 __spitfire_data_access_exception_tl1:
>> 884 rdpr %pstate, %g4
>> 885 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
>> 886 mov TLB_SFSR, %g3
>> 887 mov DMMU_SFAR, %g5
>> 888 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
>> 889 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
>> 890 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
>> 891 membar #Sync
>> 892 rdpr %tt, %g3
>> 893 cmp %g3, 0x80 ! first win spill/fill trap
>> 894 blu,pn %xcc, 1f
>> 895 cmp %g3, 0xff ! last win spill/fill trap
>> 896 bgu,pn %xcc, 1f
>> 897 nop
>> 898 ba,pt %xcc, winfix_dax
>> 899 rdpr %tpc, %g3
>> 900 1: sethi %hi(109f), %g7
>> 901 ba,pt %xcc, etraptl1
>> 902 109: or %g7, %lo(109b), %g7
>> 903 mov %l4, %o1
>> 904 mov %l5, %o2
>> 905 call spitfire_data_access_exception_tl1
>> 906 add %sp, PTREGS_OFF, %o0
>> 907 ba,pt %xcc, rtrap
>> 908 clr %l6
>> 909
>> 910 __spitfire_data_access_exception:
>> 911 rdpr %pstate, %g4
>> 912 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
>> 913 mov TLB_SFSR, %g3
>> 914 mov DMMU_SFAR, %g5
>> 915 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
>> 916 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
>> 917 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
>> 918 membar #Sync
>> 919 sethi %hi(109f), %g7
>> 920 ba,pt %xcc, etrap
>> 921 109: or %g7, %lo(109b), %g7
>> 922 mov %l4, %o1
>> 923 mov %l5, %o2
>> 924 call spitfire_data_access_exception
>> 925 add %sp, PTREGS_OFF, %o0
>> 926 ba,pt %xcc, rtrap
>> 927 clr %l6
>> 928
>> 929 .globl __spitfire_insn_access_exception
>> 930 .globl __spitfire_insn_access_exception_tl1
>> 931 __spitfire_insn_access_exception_tl1:
>> 932 rdpr %pstate, %g4
>> 933 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
>> 934 mov TLB_SFSR, %g3
>> 935 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
>> 936 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
>> 937 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
>> 938 membar #Sync
>> 939 sethi %hi(109f), %g7
>> 940 ba,pt %xcc, etraptl1
>> 941 109: or %g7, %lo(109b), %g7
>> 942 mov %l4, %o1
>> 943 mov %l5, %o2
>> 944 call spitfire_insn_access_exception_tl1
>> 945 add %sp, PTREGS_OFF, %o0
>> 946 ba,pt %xcc, rtrap
>> 947 clr %l6
>> 948
>> 949 __spitfire_insn_access_exception:
>> 950 rdpr %pstate, %g4
>> 951 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
>> 952 mov TLB_SFSR, %g3
>> 953 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
>> 954 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
>> 955 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
>> 956 membar #Sync
>> 957 sethi %hi(109f), %g7
>> 958 ba,pt %xcc, etrap
>> 959 109: or %g7, %lo(109b), %g7
>> 960 mov %l4, %o1
>> 961 mov %l5, %o2
>> 962 call spitfire_insn_access_exception
>> 963 add %sp, PTREGS_OFF, %o0
>> 964 ba,pt %xcc, rtrap
>> 965 clr %l6
>> 966
>> 967 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1100 * 968 *
1101 * cr25 contains a pointer to the cur !! 969 * %g1: (TL>=0) ? 1 : 0
1102 * space page directory. !! 970 * %g2: scratch
>> 971 * %g3: scratch
>> 972 * %g4: AFSR
>> 973 * %g5: AFAR
>> 974 * %g6: current thread ptr
>> 975 * %g7: scratch
>> 976 */
>> 977 #define CHEETAH_LOG_ERROR \
>> 978 /* Put "TL1" software bit into AFSR. */ \
>> 979 and %g1, 0x1, %g1; \
>> 980 sllx %g1, 63, %g2; \
>> 981 or %g4, %g2, %g4; \
>> 982 /* Get log entry pointer for this cpu at this trap level. */ \
>> 983 BRANCH_IF_JALAPENO(g2,g3,50f) \
>> 984 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
>> 985 srlx %g2, 17, %g2; \
>> 986 ba,pt %xcc, 60f; \
>> 987 and %g2, 0x3ff, %g2; \
>> 988 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
>> 989 srlx %g2, 17, %g2; \
>> 990 and %g2, 0x1f, %g2; \
>> 991 60: sllx %g2, 9, %g2; \
>> 992 sethi %hi(cheetah_error_log), %g3; \
>> 993 ldx [%g3 + %lo(cheetah_error_log)], %g3; \
>> 994 brz,pn %g3, 80f; \
>> 995 nop; \
>> 996 add %g3, %g2, %g3; \
>> 997 sllx %g1, 8, %g1; \
>> 998 add %g3, %g1, %g1; \
>> 999 /* %g1 holds pointer to the top of the logging scoreboard */ \
>> 1000 ldx [%g1 + 0x0], %g7; \
>> 1001 cmp %g7, -1; \
>> 1002 bne,pn %xcc, 80f; \
>> 1003 nop; \
>> 1004 stx %g4, [%g1 + 0x0]; \
>> 1005 stx %g5, [%g1 + 0x8]; \
>> 1006 add %g1, 0x10, %g1; \
>> 1007 /* %g1 now points to D-cache logging area */ \
>> 1008 set 0x3ff8, %g2; /* DC_addr mask */ \
>> 1009 and %g5, %g2, %g2; /* DC_addr bits of AFAR */ \
>> 1010 srlx %g5, 12, %g3; \
>> 1011 or %g3, 1, %g3; /* PHYS tag + valid */ \
>> 1012 10: ldxa [%g2] ASI_DCACHE_TAG, %g7; \
>> 1013 cmp %g3, %g7; /* TAG match? */ \
>> 1014 bne,pt %xcc, 13f; \
>> 1015 nop; \
>> 1016 /* Yep, what we want, capture state. */ \
>> 1017 stx %g2, [%g1 + 0x20]; \
>> 1018 stx %g7, [%g1 + 0x28]; \
>> 1019 /* A membar Sync is required before and after utag access. */ \
>> 1020 membar #Sync; \
>> 1021 ldxa [%g2] ASI_DCACHE_UTAG, %g7; \
>> 1022 membar #Sync; \
>> 1023 stx %g7, [%g1 + 0x30]; \
>> 1024 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7; \
>> 1025 stx %g7, [%g1 + 0x38]; \
>> 1026 clr %g3; \
>> 1027 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7; \
>> 1028 stx %g7, [%g1]; \
>> 1029 add %g3, (1 << 5), %g3; \
>> 1030 cmp %g3, (4 << 5); \
>> 1031 bl,pt %xcc, 12b; \
>> 1032 add %g1, 0x8, %g1; \
>> 1033 ba,pt %xcc, 20f; \
>> 1034 add %g1, 0x20, %g1; \
>> 1035 13: sethi %hi(1 << 14), %g7; \
>> 1036 add %g2, %g7, %g2; \
>> 1037 srlx %g2, 14, %g7; \
>> 1038 cmp %g7, 4; \
>> 1039 bl,pt %xcc, 10b; \
>> 1040 nop; \
>> 1041 add %g1, 0x40, %g1; \
>> 1042 20: /* %g1 now points to I-cache logging area */ \
>> 1043 set 0x1fe0, %g2; /* IC_addr mask */ \
>> 1044 and %g5, %g2, %g2; /* IC_addr bits of AFAR */ \
>> 1045 sllx %g2, 1, %g2; /* IC_addr[13:6]==VA[12:5] */ \
>> 1046 srlx %g5, (13 - 8), %g3; /* Make PTAG */ \
>> 1047 andn %g3, 0xff, %g3; /* Mask off undefined bits */ \
>> 1048 21: ldxa [%g2] ASI_IC_TAG, %g7; \
>> 1049 andn %g7, 0xff, %g7; \
>> 1050 cmp %g3, %g7; \
>> 1051 bne,pt %xcc, 23f; \
>> 1052 nop; \
>> 1053 /* Yep, what we want, capture state. */ \
>> 1054 stx %g2, [%g1 + 0x40]; \
>> 1055 stx %g7, [%g1 + 0x48]; \
>> 1056 add %g2, (1 << 3), %g2; \
>> 1057 ldxa [%g2] ASI_IC_TAG, %g7; \
>> 1058 add %g2, (1 << 3), %g2; \
>> 1059 stx %g7, [%g1 + 0x50]; \
>> 1060 ldxa [%g2] ASI_IC_TAG, %g7; \
>> 1061 add %g2, (1 << 3), %g2; \
>> 1062 stx %g7, [%g1 + 0x60]; \
>> 1063 ldxa [%g2] ASI_IC_TAG, %g7; \
>> 1064 stx %g7, [%g1 + 0x68]; \
>> 1065 sub %g2, (3 << 3), %g2; \
>> 1066 ldxa [%g2] ASI_IC_STAG, %g7; \
>> 1067 stx %g7, [%g1 + 0x58]; \
>> 1068 clr %g3; \
>> 1069 srlx %g2, 2, %g2; \
>> 1070 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7; \
>> 1071 stx %g7, [%g1]; \
>> 1072 add %g3, (1 << 3), %g3; \
>> 1073 cmp %g3, (8 << 3); \
>> 1074 bl,pt %xcc, 22b; \
>> 1075 add %g1, 0x8, %g1; \
>> 1076 ba,pt %xcc, 30f; \
>> 1077 add %g1, 0x30, %g1; \
>> 1078 23: sethi %hi(1 << 14), %g7; \
>> 1079 add %g2, %g7, %g2; \
>> 1080 srlx %g2, 14, %g7; \
>> 1081 cmp %g7, 4; \
>> 1082 bl,pt %xcc, 21b; \
>> 1083 nop; \
>> 1084 add %g1, 0x70, %g1; \
>> 1085 30: /* %g1 now points to E-cache logging area */ \
>> 1086 andn %g5, (32 - 1), %g2; /* E-cache subblock */ \
>> 1087 stx %g2, [%g1 + 0x20]; \
>> 1088 ldxa [%g2] ASI_EC_TAG_DATA, %g7; \
>> 1089 stx %g7, [%g1 + 0x28]; \
>> 1090 ldxa [%g2] ASI_EC_R, %g0; \
>> 1091 clr %g3; \
>> 1092 31: ldxa [%g3] ASI_EC_DATA, %g7; \
>> 1093 stx %g7, [%g1 + %g3]; \
>> 1094 add %g3, 0x8, %g3; \
>> 1095 cmp %g3, 0x20; \
>> 1096 bl,pt %xcc, 31b; \
>> 1097 nop; \
>> 1098 80: /* DONE */
>> 1099
>> 1100 /* These get patched into the trap table at boot time
>> 1101 * once we know we have a cheetah processor.
>> 1102 */
>> 1103 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
>> 1104 cheetah_fecc_trap_vector:
>> 1105 membar #Sync
>> 1106 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
>> 1107 andn %g1, DCU_DC | DCU_IC, %g1
>> 1108 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
>> 1109 membar #Sync
>> 1110 sethi %hi(cheetah_fast_ecc), %g2
>> 1111 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
>> 1112 mov 0, %g1
>> 1113 cheetah_fecc_trap_vector_tl1:
>> 1114 membar #Sync
>> 1115 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
>> 1116 andn %g1, DCU_DC | DCU_IC, %g1
>> 1117 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
>> 1118 membar #Sync
>> 1119 sethi %hi(cheetah_fast_ecc), %g2
>> 1120 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
>> 1121 mov 1, %g1
>> 1122 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
>> 1123 cheetah_cee_trap_vector:
>> 1124 membar #Sync
>> 1125 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
>> 1126 andn %g1, DCU_IC, %g1
>> 1127 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
>> 1128 membar #Sync
>> 1129 sethi %hi(cheetah_cee), %g2
>> 1130 jmpl %g2 + %lo(cheetah_cee), %g0
>> 1131 mov 0, %g1
>> 1132 cheetah_cee_trap_vector_tl1:
>> 1133 membar #Sync
>> 1134 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
>> 1135 andn %g1, DCU_IC, %g1
>> 1136 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
>> 1137 membar #Sync
>> 1138 sethi %hi(cheetah_cee), %g2
>> 1139 jmpl %g2 + %lo(cheetah_cee), %g0
>> 1140 mov 1, %g1
>> 1141 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
>> 1142 cheetah_deferred_trap_vector:
>> 1143 membar #Sync
>> 1144 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
>> 1145 andn %g1, DCU_DC | DCU_IC, %g1;
>> 1146 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
>> 1147 membar #Sync;
>> 1148 sethi %hi(cheetah_deferred_trap), %g2
>> 1149 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
>> 1150 mov 0, %g1
>> 1151 cheetah_deferred_trap_vector_tl1:
>> 1152 membar #Sync;
>> 1153 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
>> 1154 andn %g1, DCU_DC | DCU_IC, %g1;
>> 1155 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
>> 1156 membar #Sync;
>> 1157 sethi %hi(cheetah_deferred_trap), %g2
>> 1158 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
>> 1159 mov 1, %g1
>> 1160
>> 1161 /* Cheetah+ specific traps. These are for the new I/D cache parity
>> 1162 * error traps. The first argument to cheetah_plus_parity_handler
>> 1163 * is encoded as follows:
1103 * 1164 *
1104 * sr3 will contain the space id of t !! 1165 * Bit0: 0=dcache,1=icache
1105 * of the current running thread whil !! 1166 * Bit1: 0=recoverable,1=unrecoverable
1106 * running in the kernel. <<
1107 */ 1167 */
1108 !! 1168 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
1109 /* !! 1169 cheetah_plus_dcpe_trap_vector:
1110 * register number allocations. Note !! 1170 membar #Sync
1111 * in the shadowed registers !! 1171 sethi %hi(do_cheetah_plus_data_parity), %g7
1112 */ !! 1172 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
1113 !! 1173 nop
1114 t0 = r1 /* temporary register <<
1115 va = r8 /* virtual address fo <<
1116 t1 = r9 /* temporary register <<
1117 pte = r16 /* pte/phys page # */ <<
1118 prot = r17 /* prot bits */ <<
1119 spc = r24 /* space for which th <<
1120 ptp = r25 /* page directory/pag <<
1121 <<
1122 #ifdef CONFIG_64BIT <<
1123 <<
1124 dtlb_miss_20w: <<
1125 space_adjust spc,va,t0 <<
1126 get_pgd spc,ptp <<
1127 space_check spc,t0,dtlb_fault <<
1128 <<
1129 L3_ptep ptp,pte,t0,va,dtlb_ch <<
1130 <<
1131 ptl_lock spc,ptp,pte,t0,t1,dtl <<
1132 update_accessed ptp,pte,t0,t1 <<
1133 <<
1134 make_insert_tlb spc,pte,prot,t1 <<
1135 <<
1136 idtlbt pte,prot <<
1137 <<
1138 ptl_unlock spc,t0,t1 <<
1139 rfir <<
1140 nop <<
1141 <<
1142 dtlb_check_alias_20w: <<
1143 do_alias spc,t0,t1,va,pte,prot <<
1144 <<
1145 idtlbt pte,prot <<
1146 <<
1147 insert_nops NUM_PIPELINE_INSNS - <<
1148 rfir <<
1149 nop <<
1150 <<
1151 nadtlb_miss_20w: <<
1152 space_adjust spc,va,t0 <<
1153 get_pgd spc,ptp <<
1154 space_check spc,t0,nadtlb_fault <<
1155 <<
1156 L3_ptep ptp,pte,t0,va,nadtlb_ <<
1157 <<
1158 ptl_lock spc,ptp,pte,t0,t1,nad <<
1159 update_accessed ptp,pte,t0,t1 <<
1160 <<
1161 make_insert_tlb spc,pte,prot,t1 <<
1162 <<
1163 idtlbt pte,prot <<
1164 <<
1165 ptl_unlock spc,t0,t1 <<
1166 rfir <<
1167 nop 1174 nop
1168 <<
1169 nadtlb_check_alias_20w: <<
1170 do_alias spc,t0,t1,va,pte,prot <<
1171 <<
1172 idtlbt pte,prot <<
1173 <<
1174 insert_nops NUM_PIPELINE_INSNS - <<
1175 rfir <<
1176 nop 1175 nop
1177 <<
1178 #else <<
1179 <<
1180 dtlb_miss_11: <<
1181 get_pgd spc,ptp <<
1182 <<
1183 space_check spc,t0,dtlb_fault <<
1184 <<
1185 L2_ptep ptp,pte,t0,va,dtlb_ch <<
1186 <<
1187 ptl_lock spc,ptp,pte,t0,t1,dtl <<
1188 update_accessed ptp,pte,t0,t1 <<
1189 <<
1190 make_insert_tlb_11 spc,pte,prot <<
1191 <<
1192 mfsp %sr1,t1 /* Save sr1 <<
1193 mtsp spc,%sr1 <<
1194 <<
1195 idtlba pte,(%sr1,va) <<
1196 idtlbp prot,(%sr1,va) <<
1197 <<
1198 mtsp t1, %sr1 /* Re <<
1199 <<
1200 ptl_unlock spc,t0,t1 <<
1201 rfir <<
1202 nop 1176 nop
1203 <<
1204 dtlb_check_alias_11: <<
1205 do_alias spc,t0,t1,va,pte,prot <<
1206 <<
1207 idtlba pte,(va) <<
1208 idtlbp prot,(va) <<
1209 <<
1210 insert_nops NUM_PIPELINE_INSNS - <<
1211 rfir <<
1212 nop 1177 nop
1213 1178
1214 nadtlb_miss_11: !! 1179 do_cheetah_plus_data_parity:
1215 get_pgd spc,ptp !! 1180 ba,pt %xcc, etrap
1216 !! 1181 rd %pc, %g7
1217 space_check spc,t0,nadtlb_fault !! 1182 mov 0x0, %o0
1218 !! 1183 call cheetah_plus_parity_error
1219 L2_ptep ptp,pte,t0,va,nadtlb_ !! 1184 add %sp, PTREGS_OFF, %o1
1220 !! 1185 ba,pt %xcc, rtrap
1221 ptl_lock spc,ptp,pte,t0,t1,nad !! 1186 clr %l6
1222 update_accessed ptp,pte,t0,t1 !! 1187
1223 !! 1188 cheetah_plus_dcpe_trap_vector_tl1:
1224 make_insert_tlb_11 spc,pte,prot !! 1189 membar #Sync
1225 !! 1190 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1226 mfsp %sr1,t1 /* Save sr1 !! 1191 sethi %hi(do_dcpe_tl1), %g3
1227 mtsp spc,%sr1 !! 1192 jmpl %g3 + %lo(do_dcpe_tl1), %g0
1228 !! 1193 nop
1229 idtlba pte,(%sr1,va) !! 1194 nop
1230 idtlbp prot,(%sr1,va) !! 1195 nop
1231 !! 1196 nop
1232 mtsp t1, %sr1 /* Re !! 1197
1233 !! 1198 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
1234 ptl_unlock spc,t0,t1 !! 1199 cheetah_plus_icpe_trap_vector:
1235 rfir !! 1200 membar #Sync
>> 1201 sethi %hi(do_cheetah_plus_insn_parity), %g7
>> 1202 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
>> 1203 nop
1236 nop 1204 nop
1237 <<
1238 nadtlb_check_alias_11: <<
1239 do_alias spc,t0,t1,va,pte,prot <<
1240 <<
1241 idtlba pte,(va) <<
1242 idtlbp prot,(va) <<
1243 <<
1244 insert_nops NUM_PIPELINE_INSNS - <<
1245 rfir <<
1246 nop 1205 nop
1247 <<
1248 dtlb_miss_20: <<
1249 space_adjust spc,va,t0 <<
1250 get_pgd spc,ptp <<
1251 space_check spc,t0,dtlb_fault <<
1252 <<
1253 L2_ptep ptp,pte,t0,va,dtlb_ch <<
1254 <<
1255 ptl_lock spc,ptp,pte,t0,t1,dtl <<
1256 update_accessed ptp,pte,t0,t1 <<
1257 <<
1258 make_insert_tlb spc,pte,prot,t1 <<
1259 <<
1260 f_extend pte,t1 <<
1261 <<
1262 idtlbt pte,prot <<
1263 <<
1264 ptl_unlock spc,t0,t1 <<
1265 rfir <<
1266 nop 1206 nop
1267 <<
1268 dtlb_check_alias_20: <<
1269 do_alias spc,t0,t1,va,pte,prot <<
1270 <<
1271 idtlbt pte,prot <<
1272 <<
1273 insert_nops NUM_PIPELINE_INSNS - <<
1274 rfir <<
1275 nop 1207 nop
1276 1208
1277 nadtlb_miss_20: !! 1209 do_cheetah_plus_insn_parity:
1278 get_pgd spc,ptp !! 1210 ba,pt %xcc, etrap
1279 !! 1211 rd %pc, %g7
1280 space_check spc,t0,nadtlb_fault !! 1212 mov 0x1, %o0
1281 !! 1213 call cheetah_plus_parity_error
1282 L2_ptep ptp,pte,t0,va,nadtlb_ !! 1214 add %sp, PTREGS_OFF, %o1
1283 !! 1215 ba,pt %xcc, rtrap
1284 ptl_lock spc,ptp,pte,t0,t1,nad !! 1216 clr %l6
1285 update_accessed ptp,pte,t0,t1 !! 1217
1286 !! 1218 cheetah_plus_icpe_trap_vector_tl1:
1287 make_insert_tlb spc,pte,prot,t1 !! 1219 membar #Sync
1288 !! 1220 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1289 f_extend pte,t1 !! 1221 sethi %hi(do_icpe_tl1), %g3
1290 !! 1222 jmpl %g3 + %lo(do_icpe_tl1), %g0
1291 idtlbt pte,prot !! 1223 nop
1292 !! 1224 nop
1293 ptl_unlock spc,t0,t1 !! 1225 nop
1294 rfir !! 1226 nop
1295 nop !! 1227
1296 !! 1228 /* If we take one of these traps when tl >= 1, then we
1297 nadtlb_check_alias_20: !! 1229 * jump to interrupt globals. If some trap level above us
1298 do_alias spc,t0,t1,va,pte,prot !! 1230 * was also using interrupt globals, we cannot recover.
1299 !! 1231 * We may use all interrupt global registers except %g6.
1300 idtlbt pte,prot !! 1232 */
1301 !! 1233 .globl do_dcpe_tl1, do_icpe_tl1
1302 insert_nops NUM_PIPELINE_INSNS - !! 1234 do_dcpe_tl1:
1303 rfir !! 1235 rdpr %tl, %g1 ! Save original trap level
1304 nop !! 1236 mov 1, %g2 ! Setup TSTATE checking loop
1305 !! 1237 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1306 #endif !! 1238 1: wrpr %g2, %tl ! Set trap level to check
1307 !! 1239 rdpr %tstate, %g4 ! Read TSTATE for this level
1308 nadtlb_emulate: !! 1240 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1309 !! 1241 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
1310 /* !! 1242 wrpr %g1, %tl ! Restore original trap level
1311 * Non-access misses can be caused by !! 1243 add %g2, 1, %g2 ! Next trap level
1312 * probei instructions. The kernel no !! 1244 cmp %g2, %g1 ! Hit them all yet?
1313 * Use of lpa and probe instructions !! 1245 ble,pt %icc, 1b ! Not yet
1314 * with shadow registers, we defer ev !! 1246 nop
1315 */ !! 1247 wrpr %g1, %tl ! Restore original trap level
1316 b,n nadtlb_fault !! 1248 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1317 !! 1249 /* Reset D-cache parity */
1318 #ifdef CONFIG_64BIT !! 1250 sethi %hi(1 << 16), %g1 ! D-cache size
1319 itlb_miss_20w: !! 1251 mov (1 << 5), %g2 ! D-cache line size
1320 !! 1252 sub %g1, %g2, %g1 ! Move down 1 cacheline
1321 /* !! 1253 1: srl %g1, 14, %g3 ! Compute UTAG
1322 * I miss is a little different, sinc !! 1254 membar #Sync
1323 * on the gateway page which is in th !! 1255 stxa %g3, [%g1] ASI_DCACHE_UTAG
1324 */ !! 1256 membar #Sync
1325 !! 1257 sub %g2, 8, %g3 ! 64-bit data word within line
1326 space_adjust spc,va,t0 !! 1258 2: membar #Sync
1327 get_pgd spc,ptp !! 1259 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
1328 space_check spc,t0,itlb_fault !! 1260 membar #Sync
1329 !! 1261 subcc %g3, 8, %g3 ! Next 64-bit data word
1330 L3_ptep ptp,pte,t0,va,itlb_fa !! 1262 bge,pt %icc, 2b
1331 !! 1263 nop
1332 ptl_lock spc,ptp,pte,t0,t1,itl !! 1264 subcc %g1, %g2, %g1 ! Next cacheline
1333 update_accessed ptp,pte,t0,t1 !! 1265 bge,pt %icc, 1b
1334 !! 1266 nop
1335 make_insert_tlb spc,pte,prot,t1 !! 1267 ba,pt %xcc, dcpe_icpe_tl1_common
>> 1268 nop
>> 1269
>> 1270 do_dcpe_tl1_fatal:
>> 1271 sethi %hi(1f), %g7
>> 1272 ba,pt %xcc, etraptl1
>> 1273 1: or %g7, %lo(1b), %g7
>> 1274 mov 0x2, %o0
>> 1275 call cheetah_plus_parity_error
>> 1276 add %sp, PTREGS_OFF, %o1
>> 1277 ba,pt %xcc, rtrap
>> 1278 clr %l6
>> 1279
>> 1280 do_icpe_tl1:
>> 1281 rdpr %tl, %g1 ! Save original trap level
>> 1282 mov 1, %g2 ! Setup TSTATE checking loop
>> 1283 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
>> 1284 1: wrpr %g2, %tl ! Set trap level to check
>> 1285 rdpr %tstate, %g4 ! Read TSTATE for this level
>> 1286 andcc %g4, %g3, %g0 ! Interrupt globals in use?
>> 1287 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
>> 1288 wrpr %g1, %tl ! Restore original trap level
>> 1289 add %g2, 1, %g2 ! Next trap level
>> 1290 cmp %g2, %g1 ! Hit them all yet?
>> 1291 ble,pt %icc, 1b ! Not yet
>> 1292 nop
>> 1293 wrpr %g1, %tl ! Restore original trap level
>> 1294 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
>> 1295 /* Flush I-cache */
>> 1296 sethi %hi(1 << 15), %g1 ! I-cache size
>> 1297 mov (1 << 5), %g2 ! I-cache line size
>> 1298 sub %g1, %g2, %g1
>> 1299 1: or %g1, (2 << 3), %g3
>> 1300 stxa %g0, [%g3] ASI_IC_TAG
>> 1301 membar #Sync
>> 1302 subcc %g1, %g2, %g1
>> 1303 bge,pt %icc, 1b
>> 1304 nop
>> 1305 ba,pt %xcc, dcpe_icpe_tl1_common
>> 1306 nop
>> 1307
>> 1308 do_icpe_tl1_fatal:
>> 1309 sethi %hi(1f), %g7
>> 1310 ba,pt %xcc, etraptl1
>> 1311 1: or %g7, %lo(1b), %g7
>> 1312 mov 0x3, %o0
>> 1313 call cheetah_plus_parity_error
>> 1314 add %sp, PTREGS_OFF, %o1
>> 1315 ba,pt %xcc, rtrap
>> 1316 clr %l6
1336 1317
1337 iitlbt pte,prot !! 1318 dcpe_icpe_tl1_common:
1338 !! 1319 /* Flush D-cache, re-enable D/I caches in DCU and finally
1339 ptl_unlock spc,t0,t1 !! 1320 * retry the trapping instruction.
1340 rfir !! 1321 */
1341 nop !! 1322 sethi %hi(1 << 16), %g1 ! D-cache size
1342 !! 1323 mov (1 << 5), %g2 ! D-cache line size
1343 naitlb_miss_20w: !! 1324 sub %g1, %g2, %g1
1344 !! 1325 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1345 /* !! 1326 membar #Sync
1346 * I miss is a little different, sinc !! 1327 subcc %g1, %g2, %g1
1347 * on the gateway page which is in th !! 1328 bge,pt %icc, 1b
>> 1329 nop
>> 1330 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
>> 1331 or %g1, (DCU_DC | DCU_IC), %g1
>> 1332 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
>> 1333 membar #Sync
>> 1334 retry
>> 1335
>> 1336 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
>> 1337 * in the trap table. That code has done a memory barrier
>> 1338 * and has disabled both the I-cache and D-cache in the DCU
>> 1339 * control register. The I-cache is disabled so that we may
>> 1340 * capture the corrupted cache line, and the D-cache is disabled
>> 1341 * because corrupt data may have been placed there and we don't
>> 1342 * want to reference it.
>> 1343 *
>> 1344 * %g1 is one if this trap occured at %tl >= 1.
>> 1345 *
>> 1346 * Next, we turn off error reporting so that we don't recurse.
1348 */ 1347 */
>> 1348 .globl cheetah_fast_ecc
>> 1349 cheetah_fast_ecc:
>> 1350 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
>> 1351 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
>> 1352 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
>> 1353 membar #Sync
>> 1354
>> 1355 /* Fetch and clear AFSR/AFAR */
>> 1356 ldxa [%g0] ASI_AFSR, %g4
>> 1357 ldxa [%g0] ASI_AFAR, %g5
>> 1358 stxa %g4, [%g0] ASI_AFSR
>> 1359 membar #Sync
>> 1360
>> 1361 CHEETAH_LOG_ERROR
>> 1362
>> 1363 rdpr %pil, %g2
>> 1364 wrpr %g0, 15, %pil
>> 1365 ba,pt %xcc, etrap_irq
>> 1366 rd %pc, %g7
>> 1367 mov %l4, %o1
>> 1368 mov %l5, %o2
>> 1369 call cheetah_fecc_handler
>> 1370 add %sp, PTREGS_OFF, %o0
>> 1371 ba,a,pt %xcc, rtrap_clr_l6
>> 1372
>> 1373 /* Our caller has disabled I-cache and performed membar Sync. */
>> 1374 .globl cheetah_cee
>> 1375 cheetah_cee:
>> 1376 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
>> 1377 andn %g2, ESTATE_ERROR_CEEN, %g2
>> 1378 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
>> 1379 membar #Sync
>> 1380
>> 1381 /* Fetch and clear AFSR/AFAR */
>> 1382 ldxa [%g0] ASI_AFSR, %g4
>> 1383 ldxa [%g0] ASI_AFAR, %g5
>> 1384 stxa %g4, [%g0] ASI_AFSR
>> 1385 membar #Sync
>> 1386
>> 1387 CHEETAH_LOG_ERROR
>> 1388
>> 1389 rdpr %pil, %g2
>> 1390 wrpr %g0, 15, %pil
>> 1391 ba,pt %xcc, etrap_irq
>> 1392 rd %pc, %g7
>> 1393 mov %l4, %o1
>> 1394 mov %l5, %o2
>> 1395 call cheetah_cee_handler
>> 1396 add %sp, PTREGS_OFF, %o0
>> 1397 ba,a,pt %xcc, rtrap_clr_l6
>> 1398
>> 1399 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
>> 1400 .globl cheetah_deferred_trap
>> 1401 cheetah_deferred_trap:
>> 1402 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
>> 1403 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
>> 1404 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
>> 1405 membar #Sync
>> 1406
>> 1407 /* Fetch and clear AFSR/AFAR */
>> 1408 ldxa [%g0] ASI_AFSR, %g4
>> 1409 ldxa [%g0] ASI_AFAR, %g5
>> 1410 stxa %g4, [%g0] ASI_AFSR
>> 1411 membar #Sync
>> 1412
>> 1413 CHEETAH_LOG_ERROR
>> 1414
>> 1415 rdpr %pil, %g2
>> 1416 wrpr %g0, 15, %pil
>> 1417 ba,pt %xcc, etrap_irq
>> 1418 rd %pc, %g7
>> 1419 mov %l4, %o1
>> 1420 mov %l5, %o2
>> 1421 call cheetah_deferred_handler
>> 1422 add %sp, PTREGS_OFF, %o0
>> 1423 ba,a,pt %xcc, rtrap_clr_l6
>> 1424
>> 1425 .globl __do_privact
>> 1426 __do_privact:
>> 1427 mov TLB_SFSR, %g3
>> 1428 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
>> 1429 membar #Sync
>> 1430 sethi %hi(109f), %g7
>> 1431 ba,pt %xcc, etrap
>> 1432 109: or %g7, %lo(109b), %g7
>> 1433 call do_privact
>> 1434 add %sp, PTREGS_OFF, %o0
>> 1435 ba,pt %xcc, rtrap
>> 1436 clr %l6
>> 1437
>> 1438 .globl do_mna
>> 1439 do_mna:
>> 1440 rdpr %tl, %g3
>> 1441 cmp %g3, 1
>> 1442
>> 1443 /* Setup %g4/%g5 now as they are used in the
>> 1444 * winfixup code.
>> 1445 */
>> 1446 mov TLB_SFSR, %g3
>> 1447 mov DMMU_SFAR, %g4
>> 1448 ldxa [%g4] ASI_DMMU, %g4
>> 1449 ldxa [%g3] ASI_DMMU, %g5
>> 1450 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
>> 1451 membar #Sync
>> 1452 bgu,pn %icc, winfix_mna
>> 1453 rdpr %tpc, %g3
>> 1454
>> 1455 1: sethi %hi(109f), %g7
>> 1456 ba,pt %xcc, etrap
>> 1457 109: or %g7, %lo(109b), %g7
>> 1458 mov %l4, %o1
>> 1459 mov %l5, %o2
>> 1460 call mem_address_unaligned
>> 1461 add %sp, PTREGS_OFF, %o0
>> 1462 ba,pt %xcc, rtrap
>> 1463 clr %l6
>> 1464
>> 1465 .globl do_lddfmna
>> 1466 do_lddfmna:
>> 1467 sethi %hi(109f), %g7
>> 1468 mov TLB_SFSR, %g4
>> 1469 ldxa [%g4] ASI_DMMU, %g5
>> 1470 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
>> 1471 membar #Sync
>> 1472 mov DMMU_SFAR, %g4
>> 1473 ldxa [%g4] ASI_DMMU, %g4
>> 1474 ba,pt %xcc, etrap
>> 1475 109: or %g7, %lo(109b), %g7
>> 1476 mov %l4, %o1
>> 1477 mov %l5, %o2
>> 1478 call handle_lddfmna
>> 1479 add %sp, PTREGS_OFF, %o0
>> 1480 ba,pt %xcc, rtrap
>> 1481 clr %l6
>> 1482
>> 1483 .globl do_stdfmna
>> 1484 do_stdfmna:
>> 1485 sethi %hi(109f), %g7
>> 1486 mov TLB_SFSR, %g4
>> 1487 ldxa [%g4] ASI_DMMU, %g5
>> 1488 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
>> 1489 membar #Sync
>> 1490 mov DMMU_SFAR, %g4
>> 1491 ldxa [%g4] ASI_DMMU, %g4
>> 1492 ba,pt %xcc, etrap
>> 1493 109: or %g7, %lo(109b), %g7
>> 1494 mov %l4, %o1
>> 1495 mov %l5, %o2
>> 1496 call handle_stdfmna
>> 1497 add %sp, PTREGS_OFF, %o0
>> 1498 ba,pt %xcc, rtrap
>> 1499 clr %l6
>> 1500
>> 1501 .globl breakpoint_trap
>> 1502 breakpoint_trap:
>> 1503 call sparc_breakpoint
>> 1504 add %sp, PTREGS_OFF, %o0
>> 1505 ba,pt %xcc, rtrap
>> 1506 nop
>> 1507
>> 1508 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
>> 1509 defined(CONFIG_SOLARIS_EMUL_MODULE)
>> 1510 /* SunOS uses syscall zero as the 'indirect syscall' it looks
>> 1511 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
>> 1512 * This is complete brain damage.
>> 1513 */
>> 1514 .globl sunos_indir
>> 1515 sunos_indir:
>> 1516 srl %o0, 0, %o0
>> 1517 mov %o7, %l4
>> 1518 cmp %o0, NR_SYSCALLS
>> 1519 blu,a,pt %icc, 1f
>> 1520 sll %o0, 0x2, %o0
>> 1521 sethi %hi(sunos_nosys), %l6
>> 1522 b,pt %xcc, 2f
>> 1523 or %l6, %lo(sunos_nosys), %l6
>> 1524 1: sethi %hi(sunos_sys_table), %l7
>> 1525 or %l7, %lo(sunos_sys_table), %l7
>> 1526 lduw [%l7 + %o0], %l6
>> 1527 2: mov %o1, %o0
>> 1528 mov %o2, %o1
>> 1529 mov %o3, %o2
>> 1530 mov %o4, %o3
>> 1531 mov %o5, %o4
>> 1532 call %l6
>> 1533 mov %l4, %o7
>> 1534
>> 1535 .globl sunos_getpid
>> 1536 sunos_getpid:
>> 1537 call sys_getppid
>> 1538 nop
>> 1539 call sys_getpid
>> 1540 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
>> 1541 b,pt %xcc, ret_sys_call
>> 1542 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
>> 1543
>> 1544 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
>> 1545 .globl sunos_getuid
>> 1546 sunos_getuid:
>> 1547 call sys32_geteuid16
>> 1548 nop
>> 1549 call sys32_getuid16
>> 1550 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
>> 1551 b,pt %xcc, ret_sys_call
>> 1552 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
>> 1553
>> 1554 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
>> 1555 .globl sunos_getgid
>> 1556 sunos_getgid:
>> 1557 call sys32_getegid16
>> 1558 nop
>> 1559 call sys32_getgid16
>> 1560 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
>> 1561 b,pt %xcc, ret_sys_call
>> 1562 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
>> 1563 #endif
>> 1564
>> 1565 /* SunOS's execv() call only specifies the argv argument, the
>> 1566 * environment settings are the same as the calling processes.
>> 1567 */
>> 1568 .globl sunos_execv, sys_execve, sys32_execve
>> 1569 sys_execve:
>> 1570 sethi %hi(sparc_execve), %g1
>> 1571 ba,pt %xcc, execve_merge
>> 1572 or %g1, %lo(sparc_execve), %g1
>> 1573 sunos_execv:
>> 1574 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
>> 1575 sys32_execve:
>> 1576 sethi %hi(sparc32_execve), %g1
>> 1577 or %g1, %lo(sparc32_execve), %g1
>> 1578 execve_merge:
>> 1579 flushw
>> 1580 jmpl %g1, %g0
>> 1581 add %sp, PTREGS_OFF, %o0
>> 1582
>> 1583 .globl sys_pipe, sys_sigpause, sys_nis_syscall
>> 1584 .globl sys_sigsuspend, sys_rt_sigsuspend, sys32_rt_sigsuspend
>> 1585 .globl sys_rt_sigreturn
>> 1586 .globl sys32_sigreturn, sys32_rt_sigreturn
>> 1587 .globl sys32_execve, sys_ptrace
>> 1588 .globl sys_sigaltstack, sys32_sigaltstack
>> 1589 .globl sys32_sigstack
>> 1590 .align 32
>> 1591 sys_pipe: ba,pt %xcc, sparc_pipe
>> 1592 add %sp, PTREGS_OFF, %o0
>> 1593 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
>> 1594 add %sp, PTREGS_OFF, %o0
>> 1595 sys_memory_ordering:
>> 1596 ba,pt %xcc, sparc_memory_ordering
>> 1597 add %sp, PTREGS_OFF, %o1
>> 1598 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
>> 1599 add %i6, STACK_BIAS, %o2
>> 1600 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
>> 1601 mov %i6, %o2
>> 1602 sys32_sigaltstack:
>> 1603 ba,pt %xcc, do_sys32_sigaltstack
>> 1604 mov %i6, %o2
>> 1605
>> 1606 .align 32
>> 1607 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
>> 1608 call do_sigsuspend
>> 1609 add %o7, 1f-.-4, %o7
>> 1610 nop
>> 1611 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
>> 1612 add %sp, PTREGS_OFF, %o2
>> 1613 call do_rt_sigsuspend
>> 1614 add %o7, 1f-.-4, %o7
>> 1615 nop
>> 1616 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
>> 1617 srl %o0, 0, %o0
>> 1618 add %sp, PTREGS_OFF, %o2
>> 1619 call do_rt_sigsuspend32
>> 1620 add %o7, 1f-.-4, %o7
>> 1621 /* NOTE: %o0 has a correct value already */
>> 1622 sys_sigpause: add %sp, PTREGS_OFF, %o1
>> 1623 call do_sigpause
>> 1624 add %o7, 1f-.-4, %o7
>> 1625 nop
>> 1626 sys32_sigreturn:
>> 1627 add %sp, PTREGS_OFF, %o0
>> 1628 call do_sigreturn32
>> 1629 add %o7, 1f-.-4, %o7
>> 1630 nop
>> 1631 sys_rt_sigreturn:
>> 1632 add %sp, PTREGS_OFF, %o0
>> 1633 call do_rt_sigreturn
>> 1634 add %o7, 1f-.-4, %o7
>> 1635 nop
>> 1636 sys32_rt_sigreturn:
>> 1637 add %sp, PTREGS_OFF, %o0
>> 1638 call do_rt_sigreturn32
>> 1639 add %o7, 1f-.-4, %o7
>> 1640 nop
>> 1641 sys_ptrace: add %sp, PTREGS_OFF, %o0
>> 1642 call do_ptrace
>> 1643 add %o7, 1f-.-4, %o7
>> 1644 nop
>> 1645 .align 32
>> 1646 1: ldx [%curptr + AOFF_task_ptrace], %l5
>> 1647 andcc %l5, 0x02, %g0
>> 1648 be,pt %icc, rtrap
>> 1649 clr %l6
>> 1650 call syscall_trace
>> 1651 nop
1349 1652
1350 space_adjust spc,va,t0 !! 1653 ba,pt %xcc, rtrap
1351 get_pgd spc,ptp !! 1654 clr %l6
1352 space_check spc,t0,naitlb_fault <<
1353 <<
1354 L3_ptep ptp,pte,t0,va,naitlb_ <<
1355 <<
1356 ptl_lock spc,ptp,pte,t0,t1,nai <<
1357 update_accessed ptp,pte,t0,t1 <<
1358 <<
1359 make_insert_tlb spc,pte,prot,t1 <<
1360 <<
1361 iitlbt pte,prot <<
1362 <<
1363 ptl_unlock spc,t0,t1 <<
1364 rfir <<
1365 nop <<
1366 <<
1367 naitlb_check_alias_20w: <<
1368 do_alias spc,t0,t1,va,pte,prot <<
1369 <<
1370 iitlbt pte,prot <<
1371 <<
1372 insert_nops NUM_PIPELINE_INSNS - <<
1373 rfir <<
1374 nop <<
1375 <<
1376 #else <<
1377 <<
1378 itlb_miss_11: <<
1379 get_pgd spc,ptp <<
1380 <<
1381 space_check spc,t0,itlb_fault <<
1382 <<
1383 L2_ptep ptp,pte,t0,va,itlb_fa <<
1384 <<
1385 ptl_lock spc,ptp,pte,t0,t1,itl <<
1386 update_accessed ptp,pte,t0,t1 <<
1387 <<
1388 make_insert_tlb_11 spc,pte,prot <<
1389 <<
1390 mfsp %sr1,t1 /* Save sr1 <<
1391 mtsp spc,%sr1 <<
1392 <<
1393 iitlba pte,(%sr1,va) <<
1394 iitlbp prot,(%sr1,va) <<
1395 <<
1396 mtsp t1, %sr1 /* Re <<
1397 <<
1398 ptl_unlock spc,t0,t1 <<
1399 rfir <<
1400 nop <<
1401 <<
1402 naitlb_miss_11: <<
1403 get_pgd spc,ptp <<
1404 <<
1405 space_check spc,t0,naitlb_fault <<
1406 <<
1407 L2_ptep ptp,pte,t0,va,naitlb_ <<
1408 <<
1409 ptl_lock spc,ptp,pte,t0,t1,nai <<
1410 update_accessed ptp,pte,t0,t1 <<
1411 <<
1412 make_insert_tlb_11 spc,pte,prot <<
1413 <<
1414 mfsp %sr1,t1 /* Save sr1 <<
1415 mtsp spc,%sr1 <<
1416 <<
1417 iitlba pte,(%sr1,va) <<
1418 iitlbp prot,(%sr1,va) <<
1419 <<
1420 mtsp t1, %sr1 /* Re <<
1421 <<
1422 ptl_unlock spc,t0,t1 <<
1423 rfir <<
1424 nop <<
1425 <<
1426 naitlb_check_alias_11: <<
1427 do_alias spc,t0,t1,va,pte,prot <<
1428 <<
1429 iitlba pte,(%sr0, va) <<
1430 iitlbp prot,(%sr0, va) <<
1431 <<
1432 insert_nops NUM_PIPELINE_INSNS - <<
1433 rfir <<
1434 nop <<
1435 <<
1436 <<
1437 itlb_miss_20: <<
1438 get_pgd spc,ptp <<
1439 <<
1440 space_check spc,t0,itlb_fault <<
1441 <<
1442 L2_ptep ptp,pte,t0,va,itlb_fa <<
1443 <<
1444 ptl_lock spc,ptp,pte,t0,t1,itl <<
1445 update_accessed ptp,pte,t0,t1 <<
1446 <<
1447 make_insert_tlb spc,pte,prot,t1 <<
1448 <<
1449 f_extend pte,t1 <<
1450 <<
1451 iitlbt pte,prot <<
1452 <<
1453 ptl_unlock spc,t0,t1 <<
1454 rfir <<
1455 nop <<
1456 <<
1457 naitlb_miss_20: <<
1458 get_pgd spc,ptp <<
1459 <<
1460 space_check spc,t0,naitlb_fault <<
1461 <<
1462 L2_ptep ptp,pte,t0,va,naitlb_ <<
1463 <<
1464 ptl_lock spc,ptp,pte,t0,t1,nai <<
1465 update_accessed ptp,pte,t0,t1 <<
1466 <<
1467 make_insert_tlb spc,pte,prot,t1 <<
1468 <<
1469 f_extend pte,t1 <<
1470 <<
1471 iitlbt pte,prot <<
1472 <<
1473 ptl_unlock spc,t0,t1 <<
1474 rfir <<
1475 nop <<
1476 <<
1477 naitlb_check_alias_20: <<
1478 do_alias spc,t0,t1,va,pte,prot <<
1479 <<
1480 iitlbt pte,prot <<
1481 <<
1482 insert_nops NUM_PIPELINE_INSNS - <<
1483 rfir <<
1484 nop <<
1485 <<
1486 #endif <<
1487 <<
1488 #ifdef CONFIG_64BIT <<
1489 <<
1490 dbit_trap_20w: <<
1491 space_adjust spc,va,t0 <<
1492 get_pgd spc,ptp <<
1493 space_check spc,t0,dbit_fault <<
1494 <<
1495 L3_ptep ptp,pte,t0,va,dbit_fa <<
1496 <<
1497 ptl_lock spc,ptp,pte,t0,t1,dbi <<
1498 update_dirty ptp,pte,t1 <<
1499 <<
1500 make_insert_tlb spc,pte,prot,t1 <<
1501 <<
1502 idtlbt pte,prot <<
1503 <<
1504 ptl_unlock spc,t0,t1 <<
1505 rfir <<
1506 nop <<
1507 #else <<
1508 <<
1509 dbit_trap_11: <<
1510 <<
1511 get_pgd spc,ptp <<
1512 <<
1513 space_check spc,t0,dbit_fault <<
1514 <<
1515 L2_ptep ptp,pte,t0,va,dbit_fa <<
1516 <<
1517 ptl_lock spc,ptp,pte,t0,t1,dbi <<
1518 update_dirty ptp,pte,t1 <<
1519 <<
1520 make_insert_tlb_11 spc,pte,prot <<
1521 <<
1522 mfsp %sr1,t1 /* Save sr1 <<
1523 mtsp spc,%sr1 <<
1524 <<
1525 idtlba pte,(%sr1,va) <<
1526 idtlbp prot,(%sr1,va) <<
1527 <<
1528 mtsp t1, %sr1 /* Resto <<
1529 <<
1530 ptl_unlock spc,t0,t1 <<
1531 rfir <<
1532 nop <<
1533 <<
1534 dbit_trap_20: <<
1535 get_pgd spc,ptp <<
1536 <<
1537 space_check spc,t0,dbit_fault <<
1538 <<
1539 L2_ptep ptp,pte,t0,va,dbit_fa <<
1540 <<
1541 ptl_lock spc,ptp,pte,t0,t1,dbi <<
1542 update_dirty ptp,pte,t1 <<
1543 <<
1544 make_insert_tlb spc,pte,prot,t1 <<
1545 <<
1546 f_extend pte,t1 <<
1547 <<
1548 idtlbt pte,prot <<
1549 <<
1550 ptl_unlock spc,t0,t1 <<
1551 rfir <<
1552 nop <<
1553 #endif <<
1554 <<
1555 .import handle_interruption,code <<
1556 <<
1557 kernel_bad_space: <<
1558 b intr_save <<
1559 ldi 31,%r8 /* Use an unu <<
1560 <<
1561 dbit_fault: <<
1562 b intr_save <<
1563 ldi 20,%r8 <<
1564 <<
1565 itlb_fault: <<
1566 b intr_save <<
1567 ldi PARISC_ITLB_TRAP,%r8 <<
1568 <<
1569 nadtlb_fault: <<
1570 b intr_save <<
1571 ldi 17,%r8 <<
1572 <<
1573 naitlb_fault: <<
1574 b intr_save <<
1575 ldi 16,%r8 <<
1576 <<
1577 dtlb_fault: <<
1578 b intr_save <<
1579 ldi 15,%r8 <<
1580 <<
1581 /* Register saving semantics for syst <<
1582 <<
1583 %r1 clobbered by syste <<
1584 %r2 saved in PT_REGS b <<
1585 %r3 - %r18 preserved by C cod <<
1586 %r19 - %r20 saved in PT_REGS b <<
1587 %r21 - %r22 non-standard sysca <<
1588 stored in kernel s <<
1589 %r23 - %r26 arg3-arg0, saved i <<
1590 %r27 - %r30 saved in PT_REGS b <<
1591 %r31 syscall return poi <<
1592 */ <<
1593 <<
1594 /* Floating point registers (FIXME: w <<
1595 <<
1596 %fr0 - %fr3 status/exception, <<
1597 %fr4 - %fr7 arguments <<
1598 %fr8 - %fr11 not preserved by C <<
1599 %fr12 - %fr21 preserved by C cod <<
1600 %fr22 - %fr31 not preserved by C <<
1601 */ <<
1602 <<
1603 .macro reg_save regs <<
1604 STREG %r3, PT_GR3(\regs) <<
1605 STREG %r4, PT_GR4(\regs) <<
1606 STREG %r5, PT_GR5(\regs) <<
1607 STREG %r6, PT_GR6(\regs) <<
1608 STREG %r7, PT_GR7(\regs) <<
1609 STREG %r8, PT_GR8(\regs) <<
1610 STREG %r9, PT_GR9(\regs) <<
1611 STREG %r10,PT_GR10(\regs) <<
1612 STREG %r11,PT_GR11(\regs) <<
1613 STREG %r12,PT_GR12(\regs) <<
1614 STREG %r13,PT_GR13(\regs) <<
1615 STREG %r14,PT_GR14(\regs) <<
1616 STREG %r15,PT_GR15(\regs) <<
1617 STREG %r16,PT_GR16(\regs) <<
1618 STREG %r17,PT_GR17(\regs) <<
1619 STREG %r18,PT_GR18(\regs) <<
1620 .endm <<
1621 <<
1622 .macro reg_restore regs <<
1623 LDREG PT_GR3(\regs), %r3 <<
1624 LDREG PT_GR4(\regs), %r4 <<
1625 LDREG PT_GR5(\regs), %r5 <<
1626 LDREG PT_GR6(\regs), %r6 <<
1627 LDREG PT_GR7(\regs), %r7 <<
1628 LDREG PT_GR8(\regs), %r8 <<
1629 LDREG PT_GR9(\regs), %r9 <<
1630 LDREG PT_GR10(\regs),%r10 <<
1631 LDREG PT_GR11(\regs),%r11 <<
1632 LDREG PT_GR12(\regs),%r12 <<
1633 LDREG PT_GR13(\regs),%r13 <<
1634 LDREG PT_GR14(\regs),%r14 <<
1635 LDREG PT_GR15(\regs),%r15 <<
1636 LDREG PT_GR16(\regs),%r16 <<
1637 LDREG PT_GR17(\regs),%r17 <<
1638 LDREG PT_GR18(\regs),%r18 <<
1639 .endm <<
1640 <<
1641 .macro fork_like name <<
1642 ENTRY_CFI(sys_\name\()_wrapper) <<
1643 mfctl %cr30,%r1 <<
1644 ldo TASK_REGS(%r1),%r1 <<
1645 reg_save %r1 <<
1646 mfctl %cr27, %r28 <<
1647 ldil L%sys_\name, %r31 <<
1648 be R%sys_\name(%sr4,%r31) <<
1649 STREG %r28, PT_CR27(%r1) <<
1650 ENDPROC_CFI(sys_\name\()_wrapper) <<
1651 .endm <<
1652 <<
1653 fork_like clone <<
1654 fork_like clone3 <<
1655 fork_like fork <<
1656 fork_like vfork <<
1657 <<
1658 /* Set the return value for the child <<
1659 ENTRY(child_return) <<
1660 BL schedule_tail, %r2 <<
1661 nop <<
1662 finish_child_return: <<
1663 mfctl %cr30,%r1 <<
1664 ldo TASK_REGS(%r1),%r1 /* g <<
1665 <<
1666 LDREG PT_CR27(%r1), %r3 <<
1667 mtctl %r3, %cr27 <<
1668 reg_restore %r1 <<
1669 b syscall_exit <<
1670 copy %r0,%r28 <<
1671 END(child_return) <<
1672 <<
1673 ENTRY_CFI(sys_rt_sigreturn_wrapper) <<
1674 mfctl %cr30,%r26 <<
1675 ldo TASK_REGS(%r26),%r26 /* ge <<
1676 /* Don't save regs, we are going to r <<
1677 STREG %r2, -RP_OFFSET(%r30) <<
1678 #ifdef CONFIG_64BIT <<
1679 ldo FRAME_SIZE(%r30), %r30 <<
1680 BL sys_rt_sigreturn,%r2 <<
1681 ldo -16(%r30),%r29 /* Re <<
1682 #else <<
1683 BL sys_rt_sigreturn,%r2 <<
1684 ldo FRAME_SIZE(%r30), %r30 <<
1685 #endif <<
1686 <<
1687 ldo -FRAME_SIZE(%r30), %r30 <<
1688 LDREG -RP_OFFSET(%r30), %r2 <<
1689 <<
1690 /* FIXME: I think we need to restore <<
1691 mfctl %cr30,%r1 <<
1692 ldo TASK_REGS(%r1),%r1 /* ge <<
1693 reg_restore %r1 <<
1694 <<
1695 /* If the signal was received while t <<
1696 * syscall, then r2 will take us to s <<
1697 * take us to syscall_exit_rfi and on <<
1698 */ <<
1699 bv %r0(%r2) <<
1700 LDREG PT_GR28(%r1),%r28 /* reload <<
1701 ENDPROC_CFI(sys_rt_sigreturn_wrapper) <<
1702 <<
1703 ENTRY(syscall_exit) <<
1704 /* NOTE: Not all syscalls exit this w <<
1705 * via syscall_exit_rfi if the signal <<
1706 * was running. <<
1707 */ <<
1708 <<
1709 /* save return value now */ <<
1710 mfctl %cr30, %r1 <<
1711 STREG %r28,TASK_PT_GR28(%r1) <<
1712 <<
1713 /* Seems to me that dp could be wrong <<
1714 * calling a module, and nothing got <<
1715 */ <<
1716 loadgp <<
1717 <<
1718 syscall_check_resched: <<
1719 <<
1720 /* check for reschedule */ <<
1721 mfctl %cr30,%r19 <<
1722 LDREG TASK_TI_FLAGS(%r19),%r19 <<
1723 bb,<,n %r19, 31-TIF_NEED_RESCHED, sy <<
1724 <<
1725 .import do_signal,code <<
1726 syscall_check_sig: <<
1727 mfctl %cr30,%r19 <<
1728 LDREG TASK_TI_FLAGS(%r19),%r19 <<
1729 ldi (_TIF_USER_WORK_MASK & ~_TIF_ <<
1730 and,COND(<>) %r19, %r26, %r0 <<
1731 b,n syscall_restore /* skip past <<
1732 <<
1733 syscall_do_signal: <<
1734 /* Save callee-save registers (for si <<
1735 * FIXME: After this point the proces <<
1736 * consistent with all the relevant s <<
1737 * before the syscall. We need to ve <<
1738 */ <<
1739 mfctl %cr30,%r1 <<
1740 ldo TASK_REGS(%r1), %r26 <<
1741 reg_save %r26 <<
1742 <<
1743 #ifdef CONFIG_64BIT <<
1744 ldo -16(%r30),%r29 <<
1745 #endif <<
1746 <<
1747 BL do_notify_resume,%r2 <<
1748 ldi 1, %r25 <<
1749 <<
1750 mfctl %cr30,%r1 <<
1751 ldo TASK_REGS(%r1), %r20 <<
1752 reg_restore %r20 <<
1753 <<
1754 b,n syscall_check_sig <<
1755 <<
1756 syscall_restore: <<
1757 mfctl %cr30,%r1 <<
1758 <<
1759 /* Are we being ptraced? */ <<
1760 LDREG TASK_TI_FLAGS(%r1),%r19 <<
1761 ldi _TIF_SINGLESTEP|_TIF_BLOCKSTE <<
1762 and,COND(=) %r19,%r2,%r0 <<
1763 b,n syscall_restore_rfi <<
1764 <<
1765 ldo TASK_PT_FR31(%r1),%r19 <<
1766 rest_fp %r19 <<
1767 <<
1768 LDREG TASK_PT_SAR(%r1),%r19 <<
1769 mtsar %r19 <<
1770 <<
1771 LDREG TASK_PT_GR2(%r1),%r2 <<
1772 LDREG TASK_PT_GR19(%r1),%r19 <<
1773 LDREG TASK_PT_GR20(%r1),%r20 <<
1774 LDREG TASK_PT_GR21(%r1),%r21 <<
1775 LDREG TASK_PT_GR22(%r1),%r22 <<
1776 LDREG TASK_PT_GR23(%r1),%r23 <<
1777 LDREG TASK_PT_GR24(%r1),%r24 <<
1778 LDREG TASK_PT_GR25(%r1),%r25 <<
1779 LDREG TASK_PT_GR26(%r1),%r26 <<
1780 LDREG TASK_PT_GR27(%r1),%r27 /* <<
1781 LDREG TASK_PT_GR28(%r1),%r28 /* <<
1782 LDREG TASK_PT_GR29(%r1),%r29 <<
1783 LDREG TASK_PT_GR31(%r1),%r31 /* <<
1784 <<
1785 /* NOTE: We use rsm/ssm pair to make <<
1786 LDREG TASK_PT_GR30(%r1),%r1 <<
1787 rsm PSW_SM_I, %r0 <<
1788 copy %r1,%r30 <<
1789 mfsp %sr3,%r1 <<
1790 mtsp %r1,%sr7 <<
1791 ssm PSW_SM_I, %r0 <<
1792 <<
1793 /* Set sr2 to zero for userspace sysc <<
1794 mtsp %r0,%sr2 <<
1795 mtsp %r1,%sr4 <<
1796 mtsp %r1,%sr5 <<
1797 mtsp %r1,%sr6 <<
1798 <<
1799 depi PRIV_USER,31,2,%r31 /* en <<
1800 1655
1801 #ifdef CONFIG_64BIT !! 1656 /* This is how fork() was meant to be done, 8 instruction entry.
1802 /* decide whether to reset the wide m <<
1803 * 1657 *
1804 * For a syscall, the W bit is stored !! 1658 * I questioned the following code briefly, let me clear things
1805 * of sp. Extract it and reset W if !! 1659 * up so you must not reason on it like I did.
1806 extrd,u,*<> %r30,63,1,%r1 !! 1660 *
1807 rsm PSW_SM_W, %r0 !! 1661 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1808 /* now reset the lowest bit of sp if !! 1662 * need it here because the only piece of window state we copy to
1809 xor %r30,%r1,%r30 !! 1663 * the child is the CWP register. Even if the parent sleeps,
1810 #endif !! 1664 * we are safe because we stuck it into pt_regs of the parent
1811 be,n 0(%sr3,%r31) !! 1665 * so it will not change.
1812 !! 1666 *
1813 /* We have to return via an RFI, so t !! 1667 * XXX This raises the question, whether we can do the same on
1814 * appropriately. !! 1668 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1815 * This sets up pt_regs so we can ret !! 1669 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1816 * the most efficient way of doing th !! 1670 * XXX fork_kwim in UREG_G1 (global registers are considered
1817 */ !! 1671 * XXX volatile across a system call in the sparc ABI I think
1818 syscall_restore_rfi: !! 1672 * XXX if it isn't we can use regs->y instead, anyone who depends
1819 ldo -1(%r0),%r2 !! 1673 * XXX upon the Y register being preserved across a fork deserves
1820 mtctl %r2,%cr0 !! 1674 * XXX to lose).
1821 LDREG TASK_PT_PSW(%r1),%r2 !! 1675 *
1822 ldi 0x0b,%r20 !! 1676 * In fact we should take advantage of that fact for other things
1823 depi -1,13,1,%r20 !! 1677 * during system calls...
1824 !! 1678 */
1825 /* The values of SINGLESTEP_BIT and B !! 1679 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1826 * set in thread_info.h and converted !! 1680 .globl ret_from_syscall
1827 * numbers in asm-offsets.c */ !! 1681 .align 32
1828 !! 1682 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1829 /* if ((%r19.SINGLESTEP_BIT)) { %r20. !! 1683 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1830 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1, !! 1684 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1831 depi -1,27,1,%r20 !! 1685 ba,pt %xcc, sys_clone
1832 !! 1686 sys_fork: clr %o1
1833 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7 !! 1687 mov SIGCHLD, %o0
1834 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,% !! 1688 sys_clone: flushw
1835 depi -1,7,1,%r20 !! 1689 movrz %o1, %fp, %o1
1836 !! 1690 mov 0, %o3
1837 STREG %r20,TASK_PT_PSW(%r1) !! 1691 ba,pt %xcc, do_fork
1838 !! 1692 add %sp, PTREGS_OFF, %o2
1839 /* Always store space registers, sinc !! 1693 ret_from_syscall:
1840 !! 1694 /* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in
1841 mfsp %sr3,%r25 !! 1695 * %o7 for us. Check performance counter stuff too.
1842 STREG %r25,TASK_PT_SR3(%r1) !! 1696 */
1843 STREG %r25,TASK_PT_SR4(%r1) !! 1697 andn %o7, SPARC_FLAG_NEWCHILD, %l0
1844 STREG %r25,TASK_PT_SR5(%r1) !! 1698 mov %g5, %o0 /* 'prev' */
1845 STREG %r25,TASK_PT_SR6(%r1) !! 1699 call schedule_tail
1846 STREG %r25,TASK_PT_SR7(%r1) !! 1700 stb %l0, [%g6 + AOFF_task_thread + AOFF_thread_flags]
1847 STREG %r25,TASK_PT_IASQ0(%r1) !! 1701 andcc %l0, SPARC_FLAG_PERFCTR, %g0
1848 STREG %r25,TASK_PT_IASQ1(%r1) !! 1702 be,pt %icc, 1f
1849 !! 1703 nop
1850 /* XXX W bit??? */ !! 1704 ldx [%g6 + AOFF_task_thread + AOFF_thread_pcr_reg], %o7
1851 /* Now if old D bit is clear, it mean !! 1705 wr %g0, %o7, %pcr
1852 * on syscall entry, so do that now. !! 1706
1853 * calls, or if someone attached to u !! 1707 /* Blackbird errata workaround. See commentary in
1854 * We could make this more efficient !! 1708 * smp.c:smp_percpu_timer_interrupt() for more
1855 * then we wouldn't be able to use th !! 1709 * information.
1856 * It is only for traced processes an !! 1710 */
1857 * an issue. !! 1711 ba,pt %xcc, 99f
1858 */ !! 1712 nop
1859 bb,< %r2,30,pt_regs_ok !! 1713 .align 64
1860 ldo TASK_REGS(%r1),%r25 !! 1714 99: wr %g0, %g0, %pic
1861 reg_save %r25 !! 1715 rd %pic, %g0
1862 !! 1716
1863 /* Save the current sr */ !! 1717 1: b,pt %xcc, ret_sys_call
1864 mfsp %sr0,%r2 !! 1718 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1865 STREG %r2,TASK_PT_SR0(%r1) !! 1719 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1866 !! 1720 rdpr %otherwin, %g1
1867 /* Save the scratch sr */ !! 1721 rdpr %cansave, %g3
1868 mfsp %sr1,%r2 !! 1722 add %g3, %g1, %g3
1869 STREG %r2,TASK_PT_SR1(%r1) !! 1723 wrpr %g3, 0x0, %cansave
1870 !! 1724 wrpr %g0, 0x0, %otherwin
1871 /* sr2 should be set to zero for user !! 1725 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1872 STREG %r0,TASK_PT_SR2(%r1) !! 1726 ba,pt %xcc, sys_exit
1873 !! 1727 stb %g0, [%g6 + AOFF_task_thread + AOFF_thread_w_saved]
1874 LDREG TASK_PT_GR31(%r1),%r2 !! 1728
1875 depi PRIV_USER,31,2,%r2 /* en !! 1729 linux_sparc_ni_syscall:
1876 STREG %r2,TASK_PT_IAOQ0(%r1) !! 1730 sethi %hi(sys_ni_syscall), %l7
1877 ldo 4(%r2),%r2 !! 1731 b,pt %xcc, 4f
1878 STREG %r2,TASK_PT_IAOQ1(%r1) !! 1732 or %l7, %lo(sys_ni_syscall), %l7
1879 b intr_restore !! 1733
1880 copy %r25,%r16 !! 1734 linux_syscall_trace32:
1881 !! 1735 call syscall_trace
1882 pt_regs_ok: !! 1736 nop
1883 LDREG TASK_PT_IAOQ0(%r1),%r2 !! 1737 srl %i0, 0, %o0
1884 depi PRIV_USER,31,2,%r2 /* en !! 1738 mov %i4, %o4
1885 STREG %r2,TASK_PT_IAOQ0(%r1) !! 1739 srl %i1, 0, %o1
1886 LDREG TASK_PT_IAOQ1(%r1),%r2 !! 1740 srl %i2, 0, %o2
1887 depi PRIV_USER,31,2,%r2 !! 1741 b,pt %xcc, 2f
1888 STREG %r2,TASK_PT_IAOQ1(%r1) !! 1742 srl %i3, 0, %o3
1889 b intr_restore !! 1743
1890 copy %r25,%r16 !! 1744 linux_syscall_trace:
1891 !! 1745 call syscall_trace
1892 syscall_do_resched: !! 1746 nop
1893 load32 syscall_check_resched,%r2 /* !! 1747 mov %i0, %o0
1894 load32 schedule,%r19 !! 1748 mov %i1, %o1
1895 bv %r0(%r19) /* ju !! 1749 mov %i2, %o2
1896 #ifdef CONFIG_64BIT !! 1750 mov %i3, %o3
1897 ldo -16(%r30),%r29 /* Re !! 1751 b,pt %xcc, 2f
1898 #else !! 1752 mov %i4, %o4
1899 nop <<
1900 #endif <<
1901 END(syscall_exit) <<
1902 <<
1903 <<
1904 #ifdef CONFIG_FUNCTION_TRACER <<
1905 <<
1906 .import ftrace_function_trampoline,co <<
1907 .align L1_CACHE_BYTES <<
1908 ENTRY_CFI(mcount, caller) <<
1909 _mcount: <<
1910 .export _mcount,data <<
1911 /* <<
1912 * The 64bit mcount() function pointe <<
1913 * first two are free. We optimize i <<
1914 * calling mcount(), and 2 instructio <<
1915 * have all on one L1 cacheline. <<
1916 */ <<
1917 ldi 0, %arg3 <<
1918 b ftrace_function_trampoline <<
1919 copy %r3, %arg2 /* caller ori <<
1920 ftrace_stub: <<
1921 .globl ftrace_stub <<
1922 .type ftrace_stub, @function <<
1923 #ifdef CONFIG_64BIT <<
1924 bve (%rp) <<
1925 #else <<
1926 bv %r0(%rp) <<
1927 #endif <<
1928 nop <<
1929 #ifdef CONFIG_64BIT <<
1930 .dword mcount <<
1931 .dword 0 /* code in head.S puts value <<
1932 #endif <<
1933 ENDPROC_CFI(mcount) <<
1934 <<
1935 #ifdef CONFIG_DYNAMIC_FTRACE <<
1936 <<
1937 #ifdef CONFIG_64BIT <<
1938 #define FTRACE_FRAME_SIZE (2*FRAME_SIZE) <<
1939 #else <<
1940 #define FTRACE_FRAME_SIZE FRAME_SIZE <<
1941 #endif <<
1942 ENTRY_CFI(ftrace_caller, caller,frame=FTRACE_ <<
1943 ftrace_caller: <<
1944 .global ftrace_caller <<
1945 <<
1946 STREG %r3, -FTRACE_FRAME_SIZE+1*REG <<
1947 ldo -FTRACE_FRAME_SIZE(%sp), %r3 <<
1948 STREG %rp, -RP_OFFSET(%r3) <<
1949 <<
1950 /* Offset 0 is already allocated for <<
1951 STREG %r23, 2*REG_SZ(%r3) <<
1952 STREG %r24, 3*REG_SZ(%r3) <<
1953 STREG %r25, 4*REG_SZ(%r3) <<
1954 STREG %r26, 5*REG_SZ(%r3) <<
1955 STREG %r28, 6*REG_SZ(%r3) <<
1956 STREG %r29, 7*REG_SZ(%r3) <<
1957 #ifdef CONFIG_64BIT <<
1958 STREG %r19, 8*REG_SZ(%r3) <<
1959 STREG %r20, 9*REG_SZ(%r3) <<
1960 STREG %r21, 10*REG_SZ(%r3) <<
1961 STREG %r22, 11*REG_SZ(%r3) <<
1962 STREG %r27, 12*REG_SZ(%r3) <<
1963 STREG %r31, 13*REG_SZ(%r3) <<
1964 loadgp <<
1965 ldo -16(%sp),%r29 <<
1966 #endif <<
1967 LDREG 0(%r3), %r25 <<
1968 copy %rp, %r26 <<
1969 ldo -8(%r25), %r25 <<
1970 ldi 0, %r23 /* no pt_regs <<
1971 b,l ftrace_function_trampoline, % <<
1972 copy %r3, %r24 <<
1973 <<
1974 LDREG -RP_OFFSET(%r3), %rp <<
1975 LDREG 2*REG_SZ(%r3), %r23 <<
1976 LDREG 3*REG_SZ(%r3), %r24 <<
1977 LDREG 4*REG_SZ(%r3), %r25 <<
1978 LDREG 5*REG_SZ(%r3), %r26 <<
1979 LDREG 6*REG_SZ(%r3), %r28 <<
1980 LDREG 7*REG_SZ(%r3), %r29 <<
1981 #ifdef CONFIG_64BIT <<
1982 LDREG 8*REG_SZ(%r3), %r19 <<
1983 LDREG 9*REG_SZ(%r3), %r20 <<
1984 LDREG 10*REG_SZ(%r3), %r21 <<
1985 LDREG 11*REG_SZ(%r3), %r22 <<
1986 LDREG 12*REG_SZ(%r3), %r27 <<
1987 LDREG 13*REG_SZ(%r3), %r31 <<
1988 #endif <<
1989 LDREG 1*REG_SZ(%r3), %r3 <<
1990 <<
1991 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1 <<
1992 /* Adjust return point to jump back t <<
1993 ldo -4(%r1), %r1 <<
1994 bv,n (%r1) <<
1995 <<
1996 ENDPROC_CFI(ftrace_caller) <<
1997 <<
1998 #ifdef CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS <<
1999 ENTRY_CFI(ftrace_regs_caller,caller,frame=FTR <<
2000 CALLS,SAVE_RP,SAVE_SP) <<
2001 ftrace_regs_caller: <<
2002 .global ftrace_regs_caller <<
2003 <<
2004 ldo -FTRACE_FRAME_SIZE(%sp), %r1 <<
2005 STREG %rp, -RP_OFFSET(%r1) <<
2006 <<
2007 copy %sp, %r1 <<
2008 ldo PT_SZ_ALGN(%sp), %sp <<
2009 <<
2010 STREG %rp, PT_GR2(%r1) <<
2011 STREG %r3, PT_GR3(%r1) <<
2012 STREG %r4, PT_GR4(%r1) <<
2013 STREG %r5, PT_GR5(%r1) <<
2014 STREG %r6, PT_GR6(%r1) <<
2015 STREG %r7, PT_GR7(%r1) <<
2016 STREG %r8, PT_GR8(%r1) <<
2017 STREG %r9, PT_GR9(%r1) <<
2018 STREG %r10, PT_GR10(%r1) <<
2019 STREG %r11, PT_GR11(%r1) <<
2020 STREG %r12, PT_GR12(%r1) <<
2021 STREG %r13, PT_GR13(%r1) <<
2022 STREG %r14, PT_GR14(%r1) <<
2023 STREG %r15, PT_GR15(%r1) <<
2024 STREG %r16, PT_GR16(%r1) <<
2025 STREG %r17, PT_GR17(%r1) <<
2026 STREG %r18, PT_GR18(%r1) <<
2027 STREG %r19, PT_GR19(%r1) <<
2028 STREG %r20, PT_GR20(%r1) <<
2029 STREG %r21, PT_GR21(%r1) <<
2030 STREG %r22, PT_GR22(%r1) <<
2031 STREG %r23, PT_GR23(%r1) <<
2032 STREG %r24, PT_GR24(%r1) <<
2033 STREG %r25, PT_GR25(%r1) <<
2034 STREG %r26, PT_GR26(%r1) <<
2035 STREG %r27, PT_GR27(%r1) <<
2036 STREG %r28, PT_GR28(%r1) <<
2037 STREG %r29, PT_GR29(%r1) <<
2038 STREG %r30, PT_GR30(%r1) <<
2039 STREG %r31, PT_GR31(%r1) <<
2040 mfctl %cr11, %r26 <<
2041 STREG %r26, PT_SAR(%r1) <<
2042 <<
2043 copy %rp, %r26 <<
2044 LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN <<
2045 ldo -8(%r25), %r25 <<
2046 ldo -FTRACE_FRAME_SIZE(%r1), %arg <<
2047 b,l ftrace_function_trampoline, % <<
2048 copy %r1, %arg3 /* struct pt_regs <<
2049 <<
2050 ldo -PT_SZ_ALGN(%sp), %r1 <<
2051 <<
2052 LDREG PT_SAR(%r1), %rp <<
2053 mtctl %rp, %cr11 <<
2054 <<
2055 LDREG PT_GR2(%r1), %rp <<
2056 LDREG PT_GR3(%r1), %r3 <<
2057 LDREG PT_GR4(%r1), %r4 <<
2058 LDREG PT_GR5(%r1), %r5 <<
2059 LDREG PT_GR6(%r1), %r6 <<
2060 LDREG PT_GR7(%r1), %r7 <<
2061 LDREG PT_GR8(%r1), %r8 <<
2062 LDREG PT_GR9(%r1), %r9 <<
2063 LDREG PT_GR10(%r1),%r10 <<
2064 LDREG PT_GR11(%r1),%r11 <<
2065 LDREG PT_GR12(%r1),%r12 <<
2066 LDREG PT_GR13(%r1),%r13 <<
2067 LDREG PT_GR14(%r1),%r14 <<
2068 LDREG PT_GR15(%r1),%r15 <<
2069 LDREG PT_GR16(%r1),%r16 <<
2070 LDREG PT_GR17(%r1),%r17 <<
2071 LDREG PT_GR18(%r1),%r18 <<
2072 LDREG PT_GR19(%r1),%r19 <<
2073 LDREG PT_GR20(%r1),%r20 <<
2074 LDREG PT_GR21(%r1),%r21 <<
2075 LDREG PT_GR22(%r1),%r22 <<
2076 LDREG PT_GR23(%r1),%r23 <<
2077 LDREG PT_GR24(%r1),%r24 <<
2078 LDREG PT_GR25(%r1),%r25 <<
2079 LDREG PT_GR26(%r1),%r26 <<
2080 LDREG PT_GR27(%r1),%r27 <<
2081 LDREG PT_GR28(%r1),%r28 <<
2082 LDREG PT_GR29(%r1),%r29 <<
2083 LDREG PT_GR30(%r1),%r30 <<
2084 LDREG PT_GR31(%r1),%r31 <<
2085 <<
2086 ldo -PT_SZ_ALGN(%sp), %sp <<
2087 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1 <<
2088 /* Adjust return point to jump back t <<
2089 ldo -4(%r1), %r1 <<
2090 bv,n (%r1) <<
2091 <<
2092 ENDPROC_CFI(ftrace_regs_caller) <<
2093 <<
2094 #endif <<
2095 #endif <<
2096 <<
2097 #ifdef CONFIG_FUNCTION_GRAPH_TRACER <<
2098 .align 8 <<
2099 ENTRY_CFI(return_to_handler, caller,frame=FRA <<
2100 .export parisc_return_to_handler,data <<
2101 parisc_return_to_handler: <<
2102 copy %r3,%r1 <<
2103 STREG %r0,-RP_OFFSET(%sp) /* st <<
2104 copy %sp,%r3 <<
2105 STREGM %r1,FRAME_SIZE(%sp) <<
2106 STREG %ret0,8(%r3) <<
2107 STREG %ret1,16(%r3) <<
2108 <<
2109 #ifdef CONFIG_64BIT <<
2110 loadgp <<
2111 #endif <<
2112 1753
2113 /* call ftrace_return_to_handler(0) * <<
2114 .import ftrace_return_to_handler,code <<
2115 load32 ftrace_return_to_handler,%ret0 <<
2116 load32 .Lftrace_ret,%r2 <<
2117 #ifdef CONFIG_64BIT <<
2118 ldo -16(%sp),%ret1 /* Re <<
2119 bve (%ret0) <<
2120 #else <<
2121 bv %r0(%ret0) <<
2122 #endif <<
2123 ldi 0,%r26 <<
2124 .Lftrace_ret: <<
2125 copy %ret0,%rp <<
2126 <<
2127 /* restore original return values */ <<
2128 LDREG 8(%r3),%ret0 <<
2129 LDREG 16(%r3),%ret1 <<
2130 <<
2131 /* return from function */ <<
2132 #ifdef CONFIG_64BIT <<
2133 bve (%rp) <<
2134 #else <<
2135 bv %r0(%rp) <<
2136 #endif <<
2137 LDREGM -FRAME_SIZE(%sp),%r3 <<
2138 ENDPROC_CFI(return_to_handler) <<
2139 1754
2140 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ !! 1755 /* Linux 32-bit and SunOS system calls enter here... */
>> 1756 .align 32
>> 1757 .globl linux_sparc_syscall32
>> 1758 linux_sparc_syscall32:
>> 1759 /* Direct access to user regs, much faster. */
>> 1760 cmp %g1, NR_SYSCALLS ! IEU1 Group
>> 1761 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
>> 1762 srl %i0, 0, %o0 ! IEU0
>> 1763 sll %g1, 2, %l4 ! IEU0 Group
>> 1764 #ifdef SYSCALL_TRACING
>> 1765 call syscall_trace_entry
>> 1766 add %sp, PTREGS_OFF, %o0
>> 1767 srl %i0, 0, %o0
>> 1768 #endif
>> 1769 mov %i4, %o4 ! IEU1
>> 1770 lduw [%l7 + %l4], %l7 ! Load
>> 1771 srl %i1, 0, %o1 ! IEU0 Group
>> 1772 ldx [%curptr + AOFF_task_ptrace], %l0 ! Load
>> 1773
>> 1774 mov %i5, %o5 ! IEU1
>> 1775 srl %i2, 0, %o2 ! IEU0 Group
>> 1776 andcc %l0, 0x02, %g0 ! IEU0 Group
>> 1777 bne,pn %icc, linux_syscall_trace32 ! CTI
>> 1778 mov %i0, %l5 ! IEU1
>> 1779 call %l7 ! CTI Group brk forced
>> 1780 srl %i3, 0, %o3 ! IEU0
>> 1781 ba,a,pt %xcc, 3f
2141 1782
2142 #endif /* CONFIG_FUNCTION_TRACER */ !! 1783 /* Linux native and SunOS system calls enter here... */
>> 1784 .align 32
>> 1785 .globl linux_sparc_syscall, ret_sys_call
>> 1786 linux_sparc_syscall:
>> 1787 /* Direct access to user regs, much faster. */
>> 1788 cmp %g1, NR_SYSCALLS ! IEU1 Group
>> 1789 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
>> 1790 mov %i0, %o0 ! IEU0
>> 1791 sll %g1, 2, %l4 ! IEU0 Group
>> 1792 #ifdef SYSCALL_TRACING
>> 1793 call syscall_trace_entry
>> 1794 add %sp, PTREGS_OFF, %o0
>> 1795 mov %i0, %o0
>> 1796 #endif
>> 1797 mov %i1, %o1 ! IEU1
>> 1798 lduw [%l7 + %l4], %l7 ! Load
>> 1799 4: mov %i2, %o2 ! IEU0 Group
>> 1800 ldx [%curptr + AOFF_task_ptrace], %l0 ! Load
>> 1801
>> 1802 mov %i3, %o3 ! IEU1
>> 1803 mov %i4, %o4 ! IEU0 Group
>> 1804 andcc %l0, 0x02, %g0 ! IEU1 Group+1 bubble
>> 1805 bne,pn %icc, linux_syscall_trace ! CTI Group
>> 1806 mov %i0, %l5 ! IEU0
>> 1807 2: call %l7 ! CTI Group brk forced
>> 1808 mov %i5, %o5 ! IEU0
>> 1809 nop
>> 1810
>> 1811 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
>> 1812 ret_sys_call:
>> 1813 #ifdef SYSCALL_TRACING
>> 1814 mov %o0, %o1
>> 1815 call syscall_trace_exit
>> 1816 add %sp, PTREGS_OFF, %o0
>> 1817 mov %o1, %o0
>> 1818 #endif
>> 1819 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
>> 1820 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
>> 1821 sra %o0, 0, %o0
>> 1822 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
>> 1823 cmp %o0, -ENOIOCTLCMD
>> 1824 sllx %g2, 32, %g2
>> 1825 bgeu,pn %xcc, 1f
>> 1826 andcc %l0, 0x02, %l6
>> 1827 80:
>> 1828 andn %g3, %g2, %g3 /* System call success, clear Carry condition code. */
>> 1829 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
>> 1830 bne,pn %icc, linux_syscall_trace2
>> 1831 add %l1, 0x4, %l2 ! npc = npc+4
>> 1832 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
>> 1833 ba,pt %xcc, rtrap_clr_l6
>> 1834 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
2143 1835
2144 #ifdef CONFIG_IRQSTACKS <<
2145 /* void call_on_stack(unsigned long param1, v <<
2146 unsigned long new_stack <<
2147 ENTRY_CFI(call_on_stack, FRAME=2*FRAME_SIZE,C <<
2148 ENTRY(_call_on_stack) <<
2149 copy %sp, %r1 <<
2150 <<
2151 /* Regarding the HPPA calling convent <<
2152 we assume the PIC register is not <<
2153 CONFIG_64BIT, the argument pointer <<
2154 argument region allocated for the <<
2155 <<
2156 /* Switch to new stack. We allocate <<
2157 ldo 2*FRAME_SIZE(%arg2), %sp <<
2158 # ifdef CONFIG_64BIT <<
2159 /* Save previous stack pointer and re <<
2160 STREG %rp, -FRAME_SIZE-RP_OFFSET(%s <<
2161 /* Calls always use function descript <<
2162 LDREG 16(%arg1), %arg1 <<
2163 bve,l (%arg1), %rp <<
2164 STREG %r1, -FRAME_SIZE-REG_SZ(%sp) <<
2165 LDREG -FRAME_SIZE-RP_OFFSET(%sp), % <<
2166 bve (%rp) <<
2167 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp <<
2168 # else <<
2169 /* Save previous stack pointer and re <<
2170 STREG %r1, -FRAME_SIZE-REG_SZ(%sp) <<
2171 STREG %rp, -FRAME_SIZE-RP_OFFSET(%s <<
2172 /* Calls use function descriptor if P <<
2173 bb,>=,n %arg1, 30, 1f <<
2174 depwi 0,31,2, %arg1 <<
2175 LDREG 0(%arg1), %arg1 <<
2176 1: 1836 1:
2177 be,l 0(%sr4,%arg1), %sr0, %r31 !! 1837 /* Really a failure? Check if force_successful_syscall_return()
2178 copy %r31, %rp !! 1838 * was invoked.
2179 LDREG -FRAME_SIZE-RP_OFFSET(%sp), % <<
2180 bv (%rp) <<
2181 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp <<
2182 # endif /* CONFIG_64BIT */ <<
2183 ENDPROC_CFI(call_on_stack) <<
2184 #endif /* CONFIG_IRQSTACKS */ <<
2185 <<
2186 ENTRY_CFI(get_register) <<
2187 /* <<
2188 * get_register is used by the non ac <<
2189 * copy the value of the general regi <<
2190 * r1. This routine can't be used for <<
2191 * the rfir will restore the original <<
2192 * registers we put a -1 into r1 to i <<
2193 * should not be used (the register b <<
2194 * a -1 in it, but that is OK, it jus <<
2195 * to use the slow path instead). <<
2196 */ 1839 */
2197 blr %r8,%r0 !! 1840 ldx [%curptr + AOFF_task_thread + AOFF_thread_flags], %l0
2198 nop !! 1841 andcc %l0, SPARC_FLAG_SYS_SUCCESS, %g0
2199 bv %r0(%r25) /* r0 */ !! 1842 be,pt %icc, 1f
2200 copy %r0,%r1 !! 1843 andcc %l6, 0x02, %g0
2201 bv %r0(%r25) /* r1 - shadowed !! 1844 andn %l0, SPARC_FLAG_SYS_SUCCESS, %l0
2202 ldi -1,%r1 !! 1845 ba,pt %xcc, 80b
2203 bv %r0(%r25) /* r2 */ !! 1846 stx %l0, [%curptr + AOFF_task_thread + AOFF_thread_flags]
2204 copy %r2,%r1 !! 1847
2205 bv %r0(%r25) /* r3 */ !! 1848 /* System call failure, set Carry condition code.
2206 copy %r3,%r1 !! 1849 * Also, get abs(errno) to return to the process.
2207 bv %r0(%r25) /* r4 */ <<
2208 copy %r4,%r1 <<
2209 bv %r0(%r25) /* r5 */ <<
2210 copy %r5,%r1 <<
2211 bv %r0(%r25) /* r6 */ <<
2212 copy %r6,%r1 <<
2213 bv %r0(%r25) /* r7 */ <<
2214 copy %r7,%r1 <<
2215 bv %r0(%r25) /* r8 - shadowed <<
2216 ldi -1,%r1 <<
2217 bv %r0(%r25) /* r9 - shadowed <<
2218 ldi -1,%r1 <<
2219 bv %r0(%r25) /* r10 */ <<
2220 copy %r10,%r1 <<
2221 bv %r0(%r25) /* r11 */ <<
2222 copy %r11,%r1 <<
2223 bv %r0(%r25) /* r12 */ <<
2224 copy %r12,%r1 <<
2225 bv %r0(%r25) /* r13 */ <<
2226 copy %r13,%r1 <<
2227 bv %r0(%r25) /* r14 */ <<
2228 copy %r14,%r1 <<
2229 bv %r0(%r25) /* r15 */ <<
2230 copy %r15,%r1 <<
2231 bv %r0(%r25) /* r16 - shadowe <<
2232 ldi -1,%r1 <<
2233 bv %r0(%r25) /* r17 - shadowe <<
2234 ldi -1,%r1 <<
2235 bv %r0(%r25) /* r18 */ <<
2236 copy %r18,%r1 <<
2237 bv %r0(%r25) /* r19 */ <<
2238 copy %r19,%r1 <<
2239 bv %r0(%r25) /* r20 */ <<
2240 copy %r20,%r1 <<
2241 bv %r0(%r25) /* r21 */ <<
2242 copy %r21,%r1 <<
2243 bv %r0(%r25) /* r22 */ <<
2244 copy %r22,%r1 <<
2245 bv %r0(%r25) /* r23 */ <<
2246 copy %r23,%r1 <<
2247 bv %r0(%r25) /* r24 - shadowe <<
2248 ldi -1,%r1 <<
2249 bv %r0(%r25) /* r25 - shadowe <<
2250 ldi -1,%r1 <<
2251 bv %r0(%r25) /* r26 */ <<
2252 copy %r26,%r1 <<
2253 bv %r0(%r25) /* r27 */ <<
2254 copy %r27,%r1 <<
2255 bv %r0(%r25) /* r28 */ <<
2256 copy %r28,%r1 <<
2257 bv %r0(%r25) /* r29 */ <<
2258 copy %r29,%r1 <<
2259 bv %r0(%r25) /* r30 */ <<
2260 copy %r30,%r1 <<
2261 bv %r0(%r25) /* r31 */ <<
2262 copy %r31,%r1 <<
2263 ENDPROC_CFI(get_register) <<
2264 <<
2265 <<
2266 ENTRY_CFI(set_register) <<
2267 /* <<
2268 * set_register is used by the non ac <<
2269 * copy the value of r1 into the gene <<
2270 * r8. <<
2271 */ 1850 */
2272 blr %r8,%r0 !! 1851 1:
2273 nop !! 1852 sub %g0, %o0, %o0
2274 bv %r0(%r25) /* r0 (silly, bu !! 1853 or %g3, %g2, %g3
2275 copy %r1,%r0 !! 1854 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
2276 bv %r0(%r25) /* r1 */ !! 1855 mov 1, %l6
2277 copy %r1,%r1 !! 1856 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
2278 bv %r0(%r25) /* r2 */ !! 1857 bne,pn %icc, linux_syscall_trace2
2279 copy %r1,%r2 !! 1858 add %l1, 0x4, %l2 !npc = npc+4
2280 bv %r0(%r25) /* r3 */ !! 1859 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
2281 copy %r1,%r3 !! 1860
2282 bv %r0(%r25) /* r4 */ !! 1861 b,pt %xcc, rtrap
2283 copy %r1,%r4 !! 1862 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
2284 bv %r0(%r25) /* r5 */ !! 1863 linux_syscall_trace2:
2285 copy %r1,%r5 !! 1864 call syscall_trace
2286 bv %r0(%r25) /* r6 */ !! 1865 nop
2287 copy %r1,%r6 !! 1866 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
2288 bv %r0(%r25) /* r7 */ !! 1867 ba,pt %xcc, rtrap
2289 copy %r1,%r7 !! 1868 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
2290 bv %r0(%r25) /* r8 */ <<
2291 copy %r1,%r8 <<
2292 bv %r0(%r25) /* r9 */ <<
2293 copy %r1,%r9 <<
2294 bv %r0(%r25) /* r10 */ <<
2295 copy %r1,%r10 <<
2296 bv %r0(%r25) /* r11 */ <<
2297 copy %r1,%r11 <<
2298 bv %r0(%r25) /* r12 */ <<
2299 copy %r1,%r12 <<
2300 bv %r0(%r25) /* r13 */ <<
2301 copy %r1,%r13 <<
2302 bv %r0(%r25) /* r14 */ <<
2303 copy %r1,%r14 <<
2304 bv %r0(%r25) /* r15 */ <<
2305 copy %r1,%r15 <<
2306 bv %r0(%r25) /* r16 */ <<
2307 copy %r1,%r16 <<
2308 bv %r0(%r25) /* r17 */ <<
2309 copy %r1,%r17 <<
2310 bv %r0(%r25) /* r18 */ <<
2311 copy %r1,%r18 <<
2312 bv %r0(%r25) /* r19 */ <<
2313 copy %r1,%r19 <<
2314 bv %r0(%r25) /* r20 */ <<
2315 copy %r1,%r20 <<
2316 bv %r0(%r25) /* r21 */ <<
2317 copy %r1,%r21 <<
2318 bv %r0(%r25) /* r22 */ <<
2319 copy %r1,%r22 <<
2320 bv %r0(%r25) /* r23 */ <<
2321 copy %r1,%r23 <<
2322 bv %r0(%r25) /* r24 */ <<
2323 copy %r1,%r24 <<
2324 bv %r0(%r25) /* r25 */ <<
2325 copy %r1,%r25 <<
2326 bv %r0(%r25) /* r26 */ <<
2327 copy %r1,%r26 <<
2328 bv %r0(%r25) /* r27 */ <<
2329 copy %r1,%r27 <<
2330 bv %r0(%r25) /* r28 */ <<
2331 copy %r1,%r28 <<
2332 bv %r0(%r25) /* r29 */ <<
2333 copy %r1,%r29 <<
2334 bv %r0(%r25) /* r30 */ <<
2335 copy %r1,%r30 <<
2336 bv %r0(%r25) /* r31 */ <<
2337 copy %r1,%r31 <<
2338 ENDPROC_CFI(set_register) <<
2339 1869
>> 1870 .align 32
>> 1871 .globl __flushw_user
>> 1872 __flushw_user:
>> 1873 rdpr %otherwin, %g1
>> 1874 brz,pn %g1, 2f
>> 1875 clr %g2
>> 1876 1: save %sp, -128, %sp
>> 1877 rdpr %otherwin, %g1
>> 1878 brnz,pt %g1, 1b
>> 1879 add %g2, 1, %g2
>> 1880 1: sub %g2, 1, %g2
>> 1881 brnz,pt %g2, 1b
>> 1882 restore %g0, %g0, %g0
>> 1883 2: retl
>> 1884 nop
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