1 /* This file is subject to the terms and condi !! 1 /*
>> 2 * This file is subject to the terms and conditions of the GNU General Public
2 * License. See the file "COPYING" in the mai 3 * License. See the file "COPYING" in the main directory of this archive
3 * for more details. 4 * for more details.
4 * 5 *
5 * Copyright (C) 1999-2007 by Helge Deller <del !! 6 * Copyright (C) 1994, 1995 Waldorf Electronics
6 * Copyright 1999 SuSE GmbH (Philipp Rumpf) !! 7 * Written by Ralf Baechle and Andreas Busse
7 * Copyright 1999 Philipp Rumpf (prumpf@tux.or !! 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
8 * Copyright 2000 Hewlett Packard (Paul Bame, !! 9 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 2001 Grant Grundler (Hewlett !! 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
10 * Copyright (C) 2004 Kyle McMartin <kyle@debia !! 11 * Further modifications by David S. Miller and Harald Koerfgen
11 * !! 12 * Copyright (C) 1999 Silicon Graphics, Inc.
12 * Initial Version 04-23-1999 by Helge Deller < !! 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
>> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
13 */ 15 */
14 <<
15 #include <asm/asm-offsets.h> <<
16 #include <asm/psw.h> <<
17 #include <asm/pdc.h> <<
18 <<
19 #include <asm/assembly.h> <<
20 <<
21 #include <linux/linkage.h> <<
22 #include <linux/init.h> 16 #include <linux/init.h>
23 #include <linux/pgtable.h> !! 17 #include <linux/threads.h>
24 18
25 .level 1.1 !! 19 #include <asm/addrspace.h>
>> 20 #include <asm/asm.h>
>> 21 #include <asm/asmmacro.h>
>> 22 #include <asm/irqflags.h>
>> 23 #include <asm/regdef.h>
>> 24 #include <asm/page.h>
>> 25 #include <asm/pgtable-bits.h>
>> 26 #include <asm/mipsregs.h>
>> 27 #include <asm/stackframe.h>
26 28
27 __INITDATA !! 29 #include <kernel-entry-init.h>
28 ENTRY(boot_args) <<
29 .word 0 /* arg0 */ <<
30 .word 0 /* arg1 */ <<
31 .word 0 /* arg2 */ <<
32 .word 0 /* arg3 */ <<
33 END(boot_args) <<
34 <<
35 __HEAD <<
36 <<
37 .align 4 <<
38 .import init_task,data <<
39 .import init_stack,data <<
40 .import fault_vector_20,code /* IVA <<
41 #ifndef CONFIG_64BIT <<
42 .import fault_vector_11,code /* IVA <<
43 .import $global$ /* for <<
44 #endif /*!CONFIG_64BIT*/ <<
45 ENTRY(parisc_kernel_start) <<
46 .proc <<
47 .callinfo <<
48 <<
49 /* Make sure sr4-sr7 are set to zero f <<
50 mtsp %r0,%sr4 <<
51 mtsp %r0,%sr5 <<
52 mtsp %r0,%sr6 <<
53 mtsp %r0,%sr7 <<
54 <<
55 /* Clear BSS (shouldn't the boot loade <<
56 <<
57 .import __bss_start,data <<
58 .import __bss_stop,data <<
59 <<
60 load32 PA(__bss_start),%r3 <<
61 load32 PA(__bss_stop),%r4 <<
62 $bss_loop: <<
63 cmpb,<<,n %r3,%r4,$bss_loop <<
64 stw,ma %r0,4(%r3) <<
65 <<
66 /* Save away the arguments the boot lo <<
67 load32 PA(boot_args),%r1 <<
68 stw,ma %arg0,4(%r1) <<
69 stw,ma %arg1,4(%r1) <<
70 stw,ma %arg2,4(%r1) <<
71 stw,ma %arg3,4(%r1) <<
72 <<
73 #if defined(CONFIG_PA20) <<
74 /* check for 64-bit capable CPU as req <<
75 ldi 32,%r10 <<
76 mtctl %r10,%cr11 <<
77 .level 2.0 <<
78 mfctl,w %cr11,%r10 <<
79 .level 1.1 <<
80 comib,<>,n 0,%r10,$cpu_ok <<
81 <<
82 load32 PA(msg1),%arg0 <<
83 ldi msg1_end-msg1,%arg1 <<
84 $iodc_panic: <<
85 copy %arg0, %r10 <<
86 copy %arg1, %r11 <<
87 load32 PA(init_stack),%sp <<
88 #define MEM_CONS 0x3A0 <<
89 ldw MEM_CONS+32(%r0),%arg0 <<
90 ldi ENTRY_IO_COUT,%arg1 <<
91 ldw MEM_CONS+36(%r0),%arg2 <<
92 ldw MEM_CONS+8(%r0),%arg3 <<
93 load32 PA(__bss_start),%r1 <<
94 stw %r1,-52(%sp) <<
95 stw %r0,-56(%sp) <<
96 stw %r10,-60(%sp) <<
97 stw %r11,-64(%sp) <<
98 stw %r0,-68(%sp) <<
99 load32 PA(.iodc_panic_ret), % <<
100 ldw MEM_CONS+40(%r0),%r1 <<
101 bv,n (%r1) <<
102 .iodc_panic_ret: <<
103 b . /* wai <<
104 or %r10,%r10,%r10 /* qem <<
105 msg1: .ascii "Can't boot kernel which was bu <<
106 msg1_end: <<
107 30
108 $cpu_ok: !! 31 /*
109 #endif !! 32 * inputs are the text nasid in t1, data nasid in t2.
110 !! 33 */
111 .level PA_ASM_LEVEL !! 34 .macro MAPPED_KERNEL_SETUP_TLB
112 !! 35 #ifdef CONFIG_MAPPED_KERNEL
113 /* Initialize startup VM. Just map fir !! 36 /*
114 load32 PA(swapper_pg_dir),%r4 !! 37 * This needs to read the nasid - assume 0 for now.
115 mtctl %r4,%cr24 /* Ini !! 38 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
116 mtctl %r4,%cr25 /* Ini !! 39 * 0+DVG in tlblo_1.
117 !! 40 */
118 #if CONFIG_PGTABLE_LEVELS == 3 !! 41 dli t0, 0xffffffffc0000000
119 /* Set pmd in pgd */ !! 42 dmtc0 t0, CP0_ENTRYHI
120 load32 PA(pmd0),%r5 !! 43 li t0, 0x1c000 # Offset of text into node memory
121 shrd %r5,PxD_VALUE_SHIFT,%r !! 44 dsll t1, NASID_SHFT # Shift text nasid into place
122 ldo (PxD_FLAG_PRESENT+PxD_ !! 45 dsll t2, NASID_SHFT # Same for data nasid
123 stw %r3,ASM_PGD_ENTRY*ASM_ !! 46 or t1, t1, t0 # Physical load address of kernel text
124 ldo ASM_PMD_ENTRY*ASM_PMD_ !! 47 or t2, t2, t0 # Physical load address of kernel data
>> 48 dsrl t1, 12 # 4K pfn
>> 49 dsrl t2, 12 # 4K pfn
>> 50 dsll t1, 6 # Get pfn into place
>> 51 dsll t2, 6 # Get pfn into place
>> 52 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
>> 53 or t0, t0, t1
>> 54 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
>> 55 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
>> 56 or t0, t0, t2
>> 57 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
>> 58 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
>> 59 mtc0 t0, CP0_PAGEMASK
>> 60 li t0, 0 # KMAP_INX
>> 61 mtc0 t0, CP0_INDEX
>> 62 li t0, 1
>> 63 mtc0 t0, CP0_WIRED
>> 64 tlbwi
125 #else 65 #else
126 /* 2-level page table, so pmd == pgd * !! 66 mtc0 zero, CP0_WIRED
127 ldo ASM_PGD_ENTRY*ASM_PGD_ <<
128 #endif 67 #endif
>> 68 .endm
129 69
130 /* Fill in pmd with enough pte directo !! 70 /*
131 load32 PA(pg0),%r1 !! 71 * For the moment disable interrupts, mark the kernel mode and
132 SHRREG %r1,PxD_VALUE_SHIFT,%r !! 72 * set ST0_KX so that the CPU does not spit fire when using
133 ldo (PxD_FLAG_PRESENT+PxD_ !! 73 * 64-bit addresses. A full initialization of the CPU's status
134 !! 74 * register is done later in per_cpu_trap_init().
135 ldi ASM_PT_INITIAL,%r1 !! 75 */
136 !! 76 .macro setup_c0_status set clr
137 1: !! 77 .set push
138 stw %r3,0(%r4) !! 78 #ifdef CONFIG_MIPS_MT_SMTC
139 ldo (PAGE_SIZE >> PxD_VALU !! 79 /*
140 addib,> -1,%r1,1b !! 80 * For SMTC, we need to set privilege and disable interrupts only for
141 #if CONFIG_PGTABLE_LEVELS == 3 !! 81 * the current TC, using the TCStatus register.
142 ldo ASM_PMD_ENTRY_SIZE(%r4 !! 82 */
>> 83 mfc0 t0, CP0_TCSTATUS
>> 84 /* Fortunately CU 0 is in the same place in both registers */
>> 85 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
>> 86 li t1, ST0_CU0 | 0x08001c00
>> 87 or t0, t1
>> 88 /* Clear TKSU, leave IXMT */
>> 89 xori t0, 0x00001800
>> 90 mtc0 t0, CP0_TCSTATUS
>> 91 _ehb
>> 92 /* We need to leave the global IE bit set, but clear EXL...*/
>> 93 mfc0 t0, CP0_STATUS
>> 94 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
>> 95 xor t0, ST0_EXL | ST0_ERL | \clr
>> 96 mtc0 t0, CP0_STATUS
143 #else 97 #else
144 ldo ASM_PGD_ENTRY_SIZE(%r4 !! 98 mfc0 t0, CP0_STATUS
>> 99 or t0, ST0_CU0|\set|0x1f|\clr
>> 100 xor t0, 0x1f|\clr
>> 101 mtc0 t0, CP0_STATUS
>> 102 .set noreorder
>> 103 sll zero,3 # ehb
145 #endif 104 #endif
>> 105 .set pop
>> 106 .endm
146 107
147 !! 108 .macro setup_c0_status_pri
148 /* Now initialize the PTEs themselves. !! 109 #ifdef CONFIG_64BIT
149 * everything ... it will get remapped !! 110 setup_c0_status ST0_KX 0
150 ldo 0+_PAGE_KERNEL_RWX(%r0 !! 111 #else
151 load32 (1<<(KERNEL_INITIAL_OR !! 112 setup_c0_status 0 0
152 load32 PA(pg0),%r1 <<
153 <<
154 $pgt_fill_loop: <<
155 STREGM %r3,ASM_PTE_ENTRY_SIZE <<
156 ldo (1<<PFN_PTE_SHIFT)(%r3 <<
157 addib,> -1,%r11,$pgt_fill_loop <<
158 nop <<
159 <<
160 /* Load the return address...er...cras <<
161 copy %r0,%r2 <<
162 <<
163 /* And the RFI Target address too */ <<
164 load32 start_parisc,%r11 <<
165 <<
166 /* And the initial task pointer */ <<
167 load32 init_task,%r6 <<
168 mtctl %r6,%cr30 <<
169 <<
170 /* And the stack pointer too */ <<
171 load32 init_stack,%sp <<
172 tophys_r1 %sp <<
173 #if defined(CONFIG_64BIT) && defined(CONFIG_FU <<
174 .import _mcount,data <<
175 /* initialize mcount FPTR */ <<
176 /* Get the global data pointer */ <<
177 loadgp <<
178 load32 PA(_mcount), %r10 <<
179 std %dp,0x18(%r10) <<
180 #endif 113 #endif
>> 114 .endm
181 115
182 #define MEM_PDC_LO 0x388 !! 116 .macro setup_c0_status_sec
183 #define MEM_PDC_HI 0x35C <<
184 #ifdef CONFIG_64BIT 117 #ifdef CONFIG_64BIT
185 /* Get PDCE_PROC for monarch CPU. */ !! 118 setup_c0_status ST0_KX ST0_BEV
186 ldw MEM_PDC_LO(%r0),%r3 !! 119 #else
187 ldw MEM_PDC_HI(%r0),%r10 !! 120 setup_c0_status 0 ST0_BEV
188 depd %r10, 31, 32, %r3 <<
189 #endif 121 #endif
>> 122 .endm
190 123
191 !! 124 #ifndef CONFIG_NO_EXCEPT_FILL
192 #ifdef CONFIG_SMP !! 125 /*
193 /* Set the smp rendezvous address into !! 126 * Reserved space for exception handlers.
194 ** It would be safer to do this in ini !! 127 * Necessary for machines which link their kernels at KSEG0.
195 ** it's just way easier to deal with h !! 128 */
196 ** of 64-bit function ptrs and the add !! 129 .fill 0x400
197 */ <<
198 load32 PA(smp_slave_stext),%r <<
199 stw %r10,0x10(%r0) /* MEM <<
200 stw %r0,0x28(%r0) /* MEM <<
201 <<
202 /* FALLTHROUGH */ <<
203 .procend <<
204 <<
205 #ifdef CONFIG_HOTPLUG_CPU <<
206 /* common_stext is far away in another <<
207 load32 PA(common_stext), %rp <<
208 bv,n (%rp) <<
209 <<
210 /* common_stext and smp_slave_stext ne <<
211 .text <<
212 #endif 130 #endif
213 131
214 /* !! 132 EXPORT(_stext)
215 ** Code Common to both Monarch and Sla <<
216 ** Entry: <<
217 ** <<
218 ** 1.1: <<
219 ** %r11 must contain RFI target add <<
220 ** %r25/%r26 args to pass to target <<
221 ** %r2 in case rfi target decides <<
222 ** <<
223 ** 2.0w: <<
224 ** %r3 PDCE_PROC address <<
225 ** %r11 RFI target address <<
226 ** <<
227 ** Caller must init: SR4-7, %sp, %r10, <<
228 */ <<
229 common_stext: <<
230 .proc <<
231 .callinfo <<
232 #else <<
233 /* Clear PDC entry point - we won't us <<
234 stw %r0,0x10(%r0) /* MEM <<
235 stw %r0,0x28(%r0) /* MEM <<
236 #endif /*CONFIG_SMP*/ <<
237 133
238 #ifdef CONFIG_64BIT !! 134 #ifdef CONFIG_BOOT_RAW
239 mfctl %cr30,%r6 !! 135 /*
240 tophys_r1 %r6 !! 136 * Give us a fighting chance of running if execution beings at the
>> 137 * kernel load address. This is needed because this platform does
>> 138 * not have a ELF loader yet.
>> 139 */
>> 140 FEXPORT(__kernel_entry)
>> 141 j kernel_entry
>> 142 #endif
241 143
242 /* Save the rfi target address */ !! 144 __REF
243 STREG %r11, TASK_PT_GR11(%r <<
244 /* Switch to wide mode Superdome doesn <<
245 ** calls. <<
246 */ <<
247 1: mfia %rp /* cle <<
248 ldo 2f-1b(%rp),%rp <<
249 depdi 0,31,32,%rp <<
250 bv (%rp) <<
251 ssm PSW_SM_W,%r0 <<
252 <<
253 /* Set Wide mode as the "Default" (eg <<
254 ** First trap occurs *right* after (or <<
255 ** Someday, palo might not do this for <<
256 */ <<
257 2: <<
258 145
259 ldo PDC_PSW(%r0),%arg0 !! 146 NESTED(kernel_entry, 16, sp) # kernel entry point
260 ldo PDC_PSW_SET_DEFAULTS(% <<
261 ldo PDC_PSW_WIDE_BIT(%r0), <<
262 load32 PA(stext_pdc_ret), %rp <<
263 bv (%r3) <<
264 copy %r0,%arg3 <<
265 <<
266 stext_pdc_ret: <<
267 LDREG TASK_PT_GR11(%r6), %r1 <<
268 tovirt_r1 %r6 <<
269 mtctl %r6,%cr30 <<
270 #endif <<
271 147
272 #ifndef CONFIG_64BIT !! 148 kernel_entry_setup # cpu specific setup
273 /* clear all BTLBs */ <<
274 ldi PDC_BLOCK_TLB,%arg0 <<
275 load32 PA(stext_pdc_btlb_ret) <<
276 ldw MEM_PDC_LO(%r0),%r3 <<
277 bv (%r3) <<
278 ldi PDC_BTLB_PURGE_ALL,%ar <<
279 stext_pdc_btlb_ret: <<
280 #endif <<
281 149
282 /* PARANOID: clear user scratch/user s !! 150 setup_c0_status_pri
283 mtsp %r0,%sr0 <<
284 mtsp %r0,%sr1 <<
285 mtsp %r0,%sr2 <<
286 mtsp %r0,%sr3 <<
287 <<
288 /* Initialize Protection Registers */ <<
289 mtctl %r0,%cr8 <<
290 mtctl %r0,%cr9 <<
291 mtctl %r0,%cr12 <<
292 mtctl %r0,%cr13 <<
293 151
294 /* Initialize the global data pointer !! 152 /* We might not get launched at the address the kernel is linked to,
295 loadgp !! 153 so we jump there. */
>> 154 PTR_LA t0, 0f
>> 155 jr t0
>> 156 0:
296 157
297 /* Set up our interrupt table. HPMCs !! 158 #ifdef CONFIG_MIPS_MT_SMTC
>> 159 /*
>> 160 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
>> 161 * We still need to enable interrupts globally in Status,
>> 162 * and clear EXL/ERL.
298 * 163 *
299 * We need to install the correct iva !! 164 * TCContext is used to track interrupt levels under
300 * following short sequence of instruc !! 165 * service in SMTC kernel. Clear for boot TC before
301 * (without being illegal on a PA1.1 m !! 166 * allowing any interrupts.
302 */ 167 */
303 #ifndef CONFIG_64BIT !! 168 mtc0 zero, CP0_TCCONTEXT
304 ldi 32,%r10 <<
305 mtctl %r10,%cr11 <<
306 .level 2.0 <<
307 mfctl,w %cr11,%r10 <<
308 .level 1.1 <<
309 comib,<>,n 0,%r10,$is_pa20 <<
310 ldil L%PA(fault_vector_11), <<
311 b $install_iva <<
312 ldo R%PA(fault_vector_11)( <<
313 <<
314 $is_pa20: <<
315 .level PA_ASM_LEVEL /* restor <<
316 #endif /*!CONFIG_64BIT*/ <<
317 load32 PA(fault_vector_20),%r <<
318 <<
319 $install_iva: <<
320 mtctl %r10,%cr14 <<
321 <<
322 b aligned_rfi /* Prepar <<
323 nop <<
324 <<
325 .align 128 <<
326 aligned_rfi: <<
327 pcxt_ssm_bug <<
328 <<
329 copy %r3, %arg0 /* PDC <<
330 <<
331 rsm PSW_SM_QUIET,%r0 <<
332 /* Don't need NOPs, have 8 compliant i <<
333 <<
334 mtctl %r0,%cr17 /* Cle <<
335 mtctl %r0,%cr17 /* Cle <<
336 <<
337 /* Load RFI target into PC queue */ <<
338 mtctl %r11,%cr18 /* IIA <<
339 ldo 4(%r11),%r11 <<
340 mtctl %r11,%cr18 /* IIA <<
341 <<
342 load32 KERNEL_PSW,%r10 <<
343 mtctl %r10,%ipsw <<
344 <<
345 tovirt_r1 %sp <<
346 <<
347 /* Jump through hyperspace to Virt Mod <<
348 rfi <<
349 nop <<
350 <<
351 .procend <<
352 169
353 #ifdef CONFIG_SMP !! 170 mfc0 t0, CP0_STATUS
354 !! 171 ori t0, t0, 0xff1f
355 .import smp_init_current_idle_task,dat !! 172 xori t0, t0, 0x001e
356 .import smp_callin,code !! 173 mtc0 t0, CP0_STATUS
>> 174 #endif /* CONFIG_MIPS_MT_SMTC */
>> 175
>> 176 PTR_LA t0, __bss_start # clear .bss
>> 177 LONG_S zero, (t0)
>> 178 PTR_LA t1, __bss_stop - LONGSIZE
>> 179 1:
>> 180 PTR_ADDIU t0, LONGSIZE
>> 181 LONG_S zero, (t0)
>> 182 bne t0, t1, 1b
>> 183
>> 184 LONG_S a0, fw_arg0 # firmware arguments
>> 185 LONG_S a1, fw_arg1
>> 186 LONG_S a2, fw_arg2
>> 187 LONG_S a3, fw_arg3
>> 188
>> 189 MTC0 zero, CP0_CONTEXT # clear context register
>> 190 PTR_LA $28, init_thread_union
>> 191 /* Set the SP after an empty pt_regs. */
>> 192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
>> 193 PTR_ADDU sp, $28
>> 194 back_to_back_c0_hazard
>> 195 set_saved_sp sp, t0, t1
>> 196 PTR_SUBU sp, 4 * SZREG # init stack pointer
357 197
358 #ifndef CONFIG_64BIT !! 198 j start_kernel
359 smp_callin_rtn: !! 199 END(kernel_entry)
360 .proc <<
361 .callinfo <<
362 break 1,1 /* Break if r <<
363 nop <<
364 nop <<
365 .procend <<
366 #endif /*!CONFIG_64BIT*/ <<
367 <<
368 /********************************************* <<
369 * smp_slave_stext is executed by all non-monar <<
370 * pokes the slave CPUs in smp.c:smp_boot_cpus( <<
371 * <<
372 * Once here, registers values are initialized <<
373 * mode. Once all available/eligible CPUs are i <<
374 * released and start out by executing their ow <<
375 ********************************************** <<
376 smp_slave_stext: <<
377 .proc <<
378 .callinfo <<
379 200
380 /* !! 201 __CPUINIT
381 ** Initialize Space registers <<
382 */ <<
383 mtsp %r0,%sr4 <<
384 mtsp %r0,%sr5 <<
385 mtsp %r0,%sr6 <<
386 mtsp %r0,%sr7 <<
387 202
388 #ifdef CONFIG_64BIT !! 203 #ifdef CONFIG_SMP
>> 204 /*
>> 205 * SMP slave cpus entry point. Board specific code for bootstrap calls this
>> 206 * function after setting up the stack and gp registers.
>> 207 */
>> 208 NESTED(smp_bootstrap, 16, sp)
>> 209 #ifdef CONFIG_MIPS_MT_SMTC
389 /* 210 /*
390 * Enable Wide mode early, in case th !! 211 * Read-modify-writes of Status must be atomic, and this
391 * task in smp_init_current_idle_task !! 212 * is one case where CLI is invoked without EXL being
>> 213 * necessarily set. The CLI and setup_c0_status will
>> 214 * in fact be redundant for all but the first TC of
>> 215 * each VPE being booted.
392 */ 216 */
393 1: mfia %rp /* cle !! 217 DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
394 ldo 2f-1b(%rp),%rp !! 218 jal mips_ihb
395 depdi 0,31,32,%rp !! 219 #endif /* CONFIG_MIPS_MT_SMTC */
396 bv (%rp) !! 220 setup_c0_status_sec
397 ssm PSW_SM_W,%r0 !! 221 smp_slave_setup
>> 222 #ifdef CONFIG_MIPS_MT_SMTC
>> 223 andi t2, t2, VPECONTROL_TE
>> 224 beqz t2, 2f
>> 225 EMT # emt
398 2: 226 2:
399 #endif !! 227 #endif /* CONFIG_MIPS_MT_SMTC */
400 !! 228 j start_secondary
401 /* Initialize the SP - monarch sets u !! 229 END(smp_bootstrap)
402 load32 PA(smp_init_current_id <<
403 LDREG 0(%r6),%r6 <<
404 mtctl %r6,%cr30 <<
405 tophys_r1 %r6 <<
406 LDREG TASK_STACK(%r6),%sp <<
407 tophys_r1 %sp <<
408 ldo FRAME_SIZE(%sp),%sp <<
409 <<
410 /* point CPU to kernel page tables */ <<
411 load32 PA(swapper_pg_dir),%r4 <<
412 mtctl %r4,%cr24 /* Ini <<
413 mtctl %r4,%cr25 /* Ini <<
414 <<
415 #ifdef CONFIG_64BIT <<
416 /* Setup PDCE_PROC entry */ <<
417 copy %arg0,%r3 <<
418 #else <<
419 /* Load RFI *return* address in case s <<
420 load32 smp_callin_rtn,%r2 <<
421 #endif <<
422 <<
423 /* Load RFI target address. */ <<
424 load32 smp_callin,%r11 <<
425 <<
426 /* ok...common code can handle the res <<
427 b common_stext <<
428 nop <<
429 <<
430 .procend <<
431 #endif /* CONFIG_SMP */ 230 #endif /* CONFIG_SMP */
432 231
433 #ifndef CONFIG_64BIT !! 232 __FINIT
434 .section .data..ro_after_init <<
435 <<
436 .align 4 <<
437 .export $global$,data <<
438 <<
439 .type $global$,@object <<
440 .size $global$,4 <<
441 $global$: <<
442 .word 0 <<
443 #endif /*!CONFIG_64BIT*/ <<
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