1 /* This file is subject to the terms and condi !! 1 /*
2 * License. See the file "COPYING" in the mai !! 2 * PowerPC version
3 * for more details. !! 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * !! 4 *
5 * Copyright (C) 1999-2007 by Helge Deller <del !! 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright 1999 SuSE GmbH (Philipp Rumpf) !! 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright 1999 Philipp Rumpf (prumpf@tux.or !! 7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Copyright 2000 Hewlett Packard (Paul Bame, !! 8 * Low-level exception handlers and MMU support
9 * Copyright (C) 2001 Grant Grundler (Hewlett !! 9 * rewritten by Paul Mackerras.
10 * Copyright (C) 2004 Kyle McMartin <kyle@debia !! 10 * Copyright (C) 1996 Paul Mackerras.
11 * !! 11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * Initial Version 04-23-1999 by Helge Deller < !! 12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 */ !! 13 *
14 !! 14 * This file contains the low-level support and setup for the
15 #include <asm/asm-offsets.h> !! 15 * PowerPC platform, including trap and interrupt dispatch.
16 #include <asm/psw.h> !! 16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 #include <asm/pdc.h> !! 17 *
18 !! 18 * This program is free software; you can redistribute it and/or
19 #include <asm/assembly.h> !! 19 * modify it under the terms of the GNU General Public License
20 !! 20 * as published by the Free Software Foundation; either version
21 #include <linux/linkage.h> !! 21 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h> !! 22 *
23 #include <linux/pgtable.h> !! 23 */
24 <<
25 .level 1.1 <<
26 <<
27 __INITDATA <<
28 ENTRY(boot_args) <<
29 .word 0 /* arg0 */ <<
30 .word 0 /* arg1 */ <<
31 .word 0 /* arg2 */ <<
32 .word 0 /* arg3 */ <<
33 END(boot_args) <<
34 <<
35 __HEAD <<
36 <<
37 .align 4 <<
38 .import init_task,data <<
39 .import init_stack,data <<
40 .import fault_vector_20,code /* IVA <<
41 #ifndef CONFIG_64BIT <<
42 .import fault_vector_11,code /* IVA <<
43 .import $global$ /* for <<
44 #endif /*!CONFIG_64BIT*/ <<
45 ENTRY(parisc_kernel_start) <<
46 .proc <<
47 .callinfo <<
48 <<
49 /* Make sure sr4-sr7 are set to zero f <<
50 mtsp %r0,%sr4 <<
51 mtsp %r0,%sr5 <<
52 mtsp %r0,%sr6 <<
53 mtsp %r0,%sr7 <<
54 <<
55 /* Clear BSS (shouldn't the boot loade <<
56 <<
57 .import __bss_start,data <<
58 .import __bss_stop,data <<
59 <<
60 load32 PA(__bss_start),%r3 <<
61 load32 PA(__bss_stop),%r4 <<
62 $bss_loop: <<
63 cmpb,<<,n %r3,%r4,$bss_loop <<
64 stw,ma %r0,4(%r3) <<
65 <<
66 /* Save away the arguments the boot lo <<
67 load32 PA(boot_args),%r1 <<
68 stw,ma %arg0,4(%r1) <<
69 stw,ma %arg1,4(%r1) <<
70 stw,ma %arg2,4(%r1) <<
71 stw,ma %arg3,4(%r1) <<
72 <<
73 #if defined(CONFIG_PA20) <<
74 /* check for 64-bit capable CPU as req <<
75 ldi 32,%r10 <<
76 mtctl %r10,%cr11 <<
77 .level 2.0 <<
78 mfctl,w %cr11,%r10 <<
79 .level 1.1 <<
80 comib,<>,n 0,%r10,$cpu_ok <<
81 <<
82 load32 PA(msg1),%arg0 <<
83 ldi msg1_end-msg1,%arg1 <<
84 $iodc_panic: <<
85 copy %arg0, %r10 <<
86 copy %arg1, %r11 <<
87 load32 PA(init_stack),%sp <<
88 #define MEM_CONS 0x3A0 <<
89 ldw MEM_CONS+32(%r0),%arg0 <<
90 ldi ENTRY_IO_COUT,%arg1 <<
91 ldw MEM_CONS+36(%r0),%arg2 <<
92 ldw MEM_CONS+8(%r0),%arg3 <<
93 load32 PA(__bss_start),%r1 <<
94 stw %r1,-52(%sp) <<
95 stw %r0,-56(%sp) <<
96 stw %r10,-60(%sp) <<
97 stw %r11,-64(%sp) <<
98 stw %r0,-68(%sp) <<
99 load32 PA(.iodc_panic_ret), % <<
100 ldw MEM_CONS+40(%r0),%r1 <<
101 bv,n (%r1) <<
102 .iodc_panic_ret: <<
103 b . /* wai <<
104 or %r10,%r10,%r10 /* qem <<
105 msg1: .ascii "Can't boot kernel which was bu <<
106 msg1_end: <<
107 <<
108 $cpu_ok: <<
109 #endif <<
110 <<
111 .level PA_ASM_LEVEL <<
112 <<
113 /* Initialize startup VM. Just map fir <<
114 load32 PA(swapper_pg_dir),%r4 <<
115 mtctl %r4,%cr24 /* Ini <<
116 mtctl %r4,%cr25 /* Ini <<
117 <<
118 #if CONFIG_PGTABLE_LEVELS == 3 <<
119 /* Set pmd in pgd */ <<
120 load32 PA(pmd0),%r5 <<
121 shrd %r5,PxD_VALUE_SHIFT,%r <<
122 ldo (PxD_FLAG_PRESENT+PxD_ <<
123 stw %r3,ASM_PGD_ENTRY*ASM_ <<
124 ldo ASM_PMD_ENTRY*ASM_PMD_ <<
125 #else <<
126 /* 2-level page table, so pmd == pgd * <<
127 ldo ASM_PGD_ENTRY*ASM_PGD_ <<
128 #endif <<
129 <<
130 /* Fill in pmd with enough pte directo <<
131 load32 PA(pg0),%r1 <<
132 SHRREG %r1,PxD_VALUE_SHIFT,%r <<
133 ldo (PxD_FLAG_PRESENT+PxD_ <<
134 24
135 ldi ASM_PT_INITIAL,%r1 !! 25 #include <linux/config.h>
>> 26 #include <asm/processor.h>
>> 27 #include <asm/page.h>
>> 28 #include <asm/mmu.h>
>> 29 #include <asm/pgtable.h>
>> 30 #include <asm/cputable.h>
>> 31 #include <asm/cache.h>
>> 32 #include <asm/thread_info.h>
>> 33 #include <asm/ppc_asm.h>
>> 34 #include <asm/offsets.h>
136 35
137 1: !! 36 #ifdef CONFIG_APUS
138 stw %r3,0(%r4) !! 37 #include <asm/amigappc.h>
139 ldo (PAGE_SIZE >> PxD_VALU <<
140 addib,> -1,%r1,1b <<
141 #if CONFIG_PGTABLE_LEVELS == 3 <<
142 ldo ASM_PMD_ENTRY_SIZE(%r4 <<
143 #else <<
144 ldo ASM_PGD_ENTRY_SIZE(%r4 <<
145 #endif 38 #endif
146 39
>> 40 #ifdef CONFIG_PPC64BRIDGE
>> 41 #define LOAD_BAT(n, reg, RA, RB) \
>> 42 ld RA,(n*32)+0(reg); \
>> 43 ld RB,(n*32)+8(reg); \
>> 44 mtspr IBAT##n##U,RA; \
>> 45 mtspr IBAT##n##L,RB; \
>> 46 ld RA,(n*32)+16(reg); \
>> 47 ld RB,(n*32)+24(reg); \
>> 48 mtspr DBAT##n##U,RA; \
>> 49 mtspr DBAT##n##L,RB; \
>> 50
>> 51 #else /* CONFIG_PPC64BRIDGE */
>> 52
>> 53 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
>> 54 #define LOAD_BAT(n, reg, RA, RB) \
>> 55 /* see the comment for clear_bats() -- Cort */ \
>> 56 li RA,0; \
>> 57 mtspr IBAT##n##U,RA; \
>> 58 mtspr DBAT##n##U,RA; \
>> 59 lwz RA,(n*16)+0(reg); \
>> 60 lwz RB,(n*16)+4(reg); \
>> 61 mtspr IBAT##n##U,RA; \
>> 62 mtspr IBAT##n##L,RB; \
>> 63 beq 1f; \
>> 64 lwz RA,(n*16)+8(reg); \
>> 65 lwz RB,(n*16)+12(reg); \
>> 66 mtspr DBAT##n##U,RA; \
>> 67 mtspr DBAT##n##L,RB; \
>> 68 1:
>> 69 #endif /* CONFIG_PPC64BRIDGE */
147 70
148 /* Now initialize the PTEs themselves. !! 71 .text
149 * everything ... it will get remapped !! 72 .stabs "arch/ppc/kernel/",N_SO,0,0,0f
150 ldo 0+_PAGE_KERNEL_RWX(%r0 !! 73 .stabs "head.S",N_SO,0,0,0f
151 load32 (1<<(KERNEL_INITIAL_OR !! 74 0:
152 load32 PA(pg0),%r1 !! 75 .globl _stext
153 !! 76 _stext:
154 $pgt_fill_loop: !! 77
155 STREGM %r3,ASM_PTE_ENTRY_SIZE !! 78 /*
156 ldo (1<<PFN_PTE_SHIFT)(%r3 !! 79 * _start is defined this way because the XCOFF loader in the OpenFirmware
157 addib,> -1,%r11,$pgt_fill_loop !! 80 * on the powermac expects the entry point to be a procedure descriptor.
>> 81 */
>> 82 .text
>> 83 .globl _start
>> 84 _start:
>> 85 /*
>> 86 * These are here for legacy reasons, the kernel used to
>> 87 * need to look like a coff function entry for the pmac
>> 88 * but we're always started by some kind of bootloader now.
>> 89 * -- Cort
>> 90 */
>> 91 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
>> 92 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
158 nop 93 nop
159 94
160 /* Load the return address...er...cras !! 95 /* PMAC
161 copy %r0,%r2 !! 96 * Enter here with the kernel text, data and bss loaded starting at
>> 97 * 0, running with virtual == physical mapping.
>> 98 * r5 points to the prom entry point (the client interface handler
>> 99 * address). Address translation is turned on, with the prom
>> 100 * managing the hash table. Interrupts are disabled. The stack
>> 101 * pointer (r1) points to just below the end of the half-meg region
>> 102 * from 0x380000 - 0x400000, which is mapped in already.
>> 103 *
>> 104 * If we are booted from MacOS via BootX, we enter with the kernel
>> 105 * image loaded somewhere, and the following values in registers:
>> 106 * r3: 'BooX' (0x426f6f58)
>> 107 * r4: virtual address of boot_infos_t
>> 108 * r5: 0
>> 109 *
>> 110 * APUS
>> 111 * r3: 'APUS'
>> 112 * r4: physical address of memory base
>> 113 * Linux/m68k style BootInfo structure at &_end.
>> 114 *
>> 115 * PREP
>> 116 * This is jumped to on prep systems right after the kernel is relocated
>> 117 * to its proper place in memory by the boot loader. The expected layout
>> 118 * of the regs is:
>> 119 * r3: ptr to residual data
>> 120 * r4: initrd_start or if no initrd then 0
>> 121 * r5: initrd_end - unused if r4 is 0
>> 122 * r6: Start of command line string
>> 123 * r7: End of command line string
>> 124 *
>> 125 * This just gets a minimal mmu environment setup so we can call
>> 126 * start_here() to do the real work.
>> 127 * -- Cort
>> 128 */
162 129
163 /* And the RFI Target address too */ !! 130 .globl __start
164 load32 start_parisc,%r11 !! 131 __start:
>> 132 /*
>> 133 * We have to do any OF calls before we map ourselves to KERNELBASE,
>> 134 * because OF may have I/O devices mapped into that area
>> 135 * (particularly on CHRP).
>> 136 */
>> 137 mr r31,r3 /* save parameters */
>> 138 mr r30,r4
>> 139 mr r29,r5
>> 140 mr r28,r6
>> 141 mr r27,r7
>> 142 li r24,0 /* cpu # */
>> 143
>> 144 #ifdef CONFIG_POWER4
>> 145 /*
>> 146 * On the PPC970, we have to turn off real-mode cache inhibit
>> 147 * early, before we first turn the MMU off.
>> 148 */
>> 149 mfspr r0,SPRN_PVR
>> 150 srwi r0,r0,16
>> 151 cmpwi r0,0x39
>> 152 beql ppc970_setup_hid
>> 153 #endif /* CONFIG_POWER4 */
>> 154
>> 155 /*
>> 156 * early_init() does the early machine identification and does
>> 157 * the necessary low-level setup and clears the BSS
>> 158 * -- Cort <cort@fsmlabs.com>
>> 159 */
>> 160 bl early_init
165 161
166 /* And the initial task pointer */ !! 162 #ifdef CONFIG_APUS
167 load32 init_task,%r6 !! 163 /* On APUS the __va/__pa constants need to be set to the correct
168 mtctl %r6,%cr30 !! 164 * values before continuing.
169 !! 165 */
170 /* And the stack pointer too */ !! 166 mr r4,r30
171 load32 init_stack,%sp !! 167 bl fix_mem_constants
172 tophys_r1 %sp !! 168 #endif /* CONFIG_APUS */
173 #if defined(CONFIG_64BIT) && defined(CONFIG_FU <<
174 .import _mcount,data <<
175 /* initialize mcount FPTR */ <<
176 /* Get the global data pointer */ <<
177 loadgp <<
178 load32 PA(_mcount), %r10 <<
179 std %dp,0x18(%r10) <<
180 #endif <<
181 <<
182 #define MEM_PDC_LO 0x388 <<
183 #define MEM_PDC_HI 0x35C <<
184 #ifdef CONFIG_64BIT <<
185 /* Get PDCE_PROC for monarch CPU. */ <<
186 ldw MEM_PDC_LO(%r0),%r3 <<
187 ldw MEM_PDC_HI(%r0),%r10 <<
188 depd %r10, 31, 32, %r3 <<
189 #endif <<
190 169
>> 170 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
>> 171 * the physical address we are running at, returned by early_init()
>> 172 */
>> 173 bl mmu_off
>> 174 __after_mmu_off:
>> 175 #ifndef CONFIG_POWER4
>> 176 bl clear_bats
>> 177 bl flush_tlbs
>> 178
>> 179 bl initial_bats
>> 180 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
>> 181 bl setup_disp_bat
>> 182 #endif
>> 183 #else /* CONFIG_POWER4 */
>> 184 bl reloc_offset
>> 185 bl initial_mm_power4
>> 186 #endif /* CONFIG_POWER4 */
191 187
>> 188 /*
>> 189 * Call setup_cpu for CPU 0 and initialize 6xx Idle
>> 190 */
>> 191 bl reloc_offset
>> 192 li r24,0 /* cpu# */
>> 193 bl call_setup_cpu /* Call setup_cpu for this CPU */
>> 194 #ifdef CONFIG_6xx
>> 195 bl reloc_offset
>> 196 bl init_idle_6xx
>> 197 #endif /* CONFIG_6xx */
>> 198 #ifdef CONFIG_POWER4
>> 199 bl reloc_offset
>> 200 bl init_idle_power4
>> 201 #endif /* CONFIG_POWER4 */
>> 202
>> 203
>> 204 #ifndef CONFIG_APUS
>> 205 /*
>> 206 * We need to run with _start at physical address 0.
>> 207 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
>> 208 * the exception vectors at 0 (and therefore this copy
>> 209 * overwrites OF's exception vectors with our own).
>> 210 * If the MMU is already turned on, we copy stuff to KERNELBASE,
>> 211 * otherwise we copy it to 0.
>> 212 */
>> 213 bl reloc_offset
>> 214 mr r26,r3
>> 215 addis r4,r3,KERNELBASE@h /* current address of _start */
>> 216 cmpwi 0,r4,0 /* are we already running at 0? */
>> 217 bne relocate_kernel
>> 218 #endif /* CONFIG_APUS */
>> 219 /*
>> 220 * we now have the 1st 16M of ram mapped with the bats.
>> 221 * prep needs the mmu to be turned on here, but pmac already has it on.
>> 222 * this shouldn't bother the pmac since it just gets turned on again
>> 223 * as we jump to our code at KERNELBASE. -- Cort
>> 224 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
>> 225 * off, and in other cases, we now turn it off before changing BATs above.
>> 226 */
>> 227 turn_on_mmu:
>> 228 mfmsr r0
>> 229 ori r0,r0,MSR_DR|MSR_IR
>> 230 mtspr SRR1,r0
>> 231 lis r0,start_here@h
>> 232 ori r0,r0,start_here@l
>> 233 mtspr SRR0,r0
>> 234 SYNC
>> 235 RFI /* enables MMU */
>> 236
>> 237 /*
>> 238 * We need __secondary_hold as a place to hold the other cpus on
>> 239 * an SMP machine, even when we are running a UP kernel.
>> 240 */
>> 241 . = 0xc0 /* for prep bootloader */
>> 242 li r3,1 /* MTX only has 1 cpu */
>> 243 .globl __secondary_hold
>> 244 __secondary_hold:
>> 245 /* tell the master we're here */
>> 246 stw r3,4(0)
192 #ifdef CONFIG_SMP 247 #ifdef CONFIG_SMP
193 /* Set the smp rendezvous address into !! 248 100: lwz r4,0(0)
194 ** It would be safer to do this in ini !! 249 /* wait until we're told to start */
195 ** it's just way easier to deal with h !! 250 cmpw 0,r4,r3
196 ** of 64-bit function ptrs and the add !! 251 bne 100b
197 */ !! 252 /* our cpu # was at addr 0 - go */
198 load32 PA(smp_slave_stext),%r !! 253 mr r24,r3 /* cpu # */
199 stw %r10,0x10(%r0) /* MEM !! 254 b __secondary_start
200 stw %r0,0x28(%r0) /* MEM !! 255 #else
201 !! 256 b .
202 /* FALLTHROUGH */ !! 257 #endif /* CONFIG_SMP */
203 .procend <<
204 <<
205 #ifdef CONFIG_HOTPLUG_CPU <<
206 /* common_stext is far away in another <<
207 load32 PA(common_stext), %rp <<
208 bv,n (%rp) <<
209 258
210 /* common_stext and smp_slave_stext ne !! 259 /*
211 .text !! 260 * Exception entry code. This code runs with address translation
>> 261 * turned off, i.e. using physical addresses.
>> 262 * We assume sprg3 has the physical address of the current
>> 263 * task's thread_struct.
>> 264 */
>> 265 #define EXCEPTION_PROLOG \
>> 266 mtspr SPRG0,r10; \
>> 267 mtspr SPRG1,r11; \
>> 268 mfcr r10; \
>> 269 EXCEPTION_PROLOG_1; \
>> 270 EXCEPTION_PROLOG_2
>> 271
>> 272 #define EXCEPTION_PROLOG_1 \
>> 273 mfspr r11,SRR1; /* check whether user or kernel */ \
>> 274 andi. r11,r11,MSR_PR; \
>> 275 tophys(r11,r1); /* use tophys(r1) if kernel */ \
>> 276 beq 1f; \
>> 277 mfspr r11,SPRG3; \
>> 278 lwz r11,THREAD_INFO-THREAD(r11); \
>> 279 addi r11,r11,THREAD_SIZE; \
>> 280 tophys(r11,r11); \
>> 281 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
>> 282
>> 283
>> 284 #define EXCEPTION_PROLOG_2 \
>> 285 CLR_TOP32(r11); \
>> 286 stw r10,_CCR(r11); /* save registers */ \
>> 287 stw r12,GPR12(r11); \
>> 288 stw r9,GPR9(r11); \
>> 289 mfspr r10,SPRG0; \
>> 290 stw r10,GPR10(r11); \
>> 291 mfspr r12,SPRG1; \
>> 292 stw r12,GPR11(r11); \
>> 293 mflr r10; \
>> 294 stw r10,_LINK(r11); \
>> 295 mfspr r12,SRR0; \
>> 296 mfspr r9,SRR1; \
>> 297 stw r1,GPR1(r11); \
>> 298 stw r1,0(r11); \
>> 299 tovirt(r1,r11); /* set new kernel sp */ \
>> 300 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
>> 301 MTMSRD(r10); /* (except for mach check in rtas) */ \
>> 302 stw r0,GPR0(r11); \
>> 303 SAVE_4GPRS(3, r11); \
>> 304 SAVE_2GPRS(7, r11)
>> 305
>> 306 /*
>> 307 * Note: code which follows this uses cr0.eq (set if from kernel),
>> 308 * r11, r12 (SRR0), and r9 (SRR1).
>> 309 *
>> 310 * Note2: once we have set r1 we are in a position to take exceptions
>> 311 * again, and we could thus set MSR:RI at that point.
>> 312 */
>> 313
>> 314 /*
>> 315 * Exception vectors.
>> 316 */
>> 317 #define EXCEPTION(n, label, hdlr, xfer) \
>> 318 . = n; \
>> 319 label: \
>> 320 EXCEPTION_PROLOG; \
>> 321 addi r3,r1,STACK_FRAME_OVERHEAD; \
>> 322 xfer(n, hdlr)
>> 323
>> 324 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
>> 325 li r10,trap; \
>> 326 stw r10,TRAP(r11); \
>> 327 li r10,MSR_KERNEL; \
>> 328 copyee(r10, r9); \
>> 329 bl tfer; \
>> 330 i##n: \
>> 331 .long hdlr; \
>> 332 .long ret
>> 333
>> 334 #define COPY_EE(d, s) rlwimi d,s,0,16,16
>> 335 #define NOCOPY(d, s)
>> 336
>> 337 #define EXC_XFER_STD(n, hdlr) \
>> 338 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
>> 339 ret_from_except_full)
>> 340
>> 341 #define EXC_XFER_LITE(n, hdlr) \
>> 342 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
>> 343 ret_from_except)
>> 344
>> 345 #define EXC_XFER_EE(n, hdlr) \
>> 346 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
>> 347 ret_from_except_full)
>> 348
>> 349 #define EXC_XFER_EE_LITE(n, hdlr) \
>> 350 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
>> 351 ret_from_except)
>> 352
>> 353 /* System reset */
>> 354 /* core99 pmac starts the seconary here by changing the vector, and
>> 355 putting it back to what it was (UnknownException) when done. */
>> 356 #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
>> 357 . = 0x100
>> 358 b __secondary_start_gemini
>> 359 #else
>> 360 EXCEPTION(0x100, Reset, UnknownException, EXC_XFER_STD)
212 #endif 361 #endif
213 362
214 /* !! 363 /* Machine check */
215 ** Code Common to both Monarch and Sla !! 364 /*
216 ** Entry: !! 365 * On CHRP, this is complicated by the fact that we could get a
217 ** !! 366 * machine check inside RTAS, and we have no guarantee that certain
218 ** 1.1: !! 367 * critical registers will have the values we expect. The set of
219 ** %r11 must contain RFI target add !! 368 * registers that might have bad values includes all the GPRs
220 ** %r25/%r26 args to pass to target !! 369 * and all the BATs. We indicate that we are in RTAS by putting
221 ** %r2 in case rfi target decides !! 370 * a non-zero value, the address of the exception frame to use,
222 ** !! 371 * in SPRG2. The machine check handler checks SPRG2 and uses its
223 ** 2.0w: !! 372 * value if it is non-zero. If we ever needed to free up SPRG2,
224 ** %r3 PDCE_PROC address !! 373 * we could use a field in the thread_info or thread_struct instead.
225 ** %r11 RFI target address !! 374 * (Other exception handlers assume that r1 is a valid kernel stack
226 ** !! 375 * pointer when we take an exception from supervisor mode.)
227 ** Caller must init: SR4-7, %sp, %r10, !! 376 * -- paulus.
228 */ !! 377 */
229 common_stext: !! 378 . = 0x200
230 .proc !! 379 mtspr SPRG0,r10
231 .callinfo !! 380 mtspr SPRG1,r11
>> 381 mfcr r10
>> 382 #ifdef CONFIG_PPC_CHRP
>> 383 mfspr r11,SPRG2
>> 384 cmpwi 0,r11,0
>> 385 bne 7f
>> 386 #endif /* CONFIG_PPC_CHRP */
>> 387 EXCEPTION_PROLOG_1
>> 388 7: EXCEPTION_PROLOG_2
>> 389 addi r3,r1,STACK_FRAME_OVERHEAD
>> 390 #ifdef CONFIG_PPC_CHRP
>> 391 mfspr r4,SPRG2
>> 392 cmpwi cr1,r4,0
>> 393 bne cr1,1f
>> 394 #endif
>> 395 EXC_XFER_STD(0x200, MachineCheckException)
>> 396 #ifdef CONFIG_PPC_CHRP
>> 397 1: b machine_check_in_rtas
>> 398 #endif
>> 399
>> 400 /* Data access exception. */
>> 401 . = 0x300
>> 402 #ifdef CONFIG_PPC64BRIDGE
>> 403 b DataAccess
>> 404 DataAccessCont:
232 #else 405 #else
233 /* Clear PDC entry point - we won't us !! 406 DataAccess:
234 stw %r0,0x10(%r0) /* MEM !! 407 EXCEPTION_PROLOG
235 stw %r0,0x28(%r0) /* MEM !! 408 #endif /* CONFIG_PPC64BRIDGE */
236 #endif /*CONFIG_SMP*/ !! 409 mfspr r10,DSISR
237 !! 410 andis. r0,r10,0xa470 /* weird error? */
238 #ifdef CONFIG_64BIT !! 411 bne 1f /* if not, try to put a PTE */
239 mfctl %cr30,%r6 !! 412 mfspr r4,DAR /* into the hash table */
240 tophys_r1 %r6 !! 413 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
241 !! 414 bl hash_page
242 /* Save the rfi target address */ !! 415 1: stw r10,_DSISR(r11)
243 STREG %r11, TASK_PT_GR11(%r !! 416 mr r5,r10
244 /* Switch to wide mode Superdome doesn !! 417 mfspr r4,DAR
245 ** calls. !! 418 stw r4,_DAR(r11)
246 */ !! 419 addi r3,r1,STACK_FRAME_OVERHEAD
247 1: mfia %rp /* cle !! 420 EXC_XFER_EE_LITE(0x300, do_page_fault)
248 ldo 2f-1b(%rp),%rp !! 421
249 depdi 0,31,32,%rp !! 422 #ifdef CONFIG_PPC64BRIDGE
250 bv (%rp) !! 423 /* SLB fault on data access. */
251 ssm PSW_SM_W,%r0 !! 424 . = 0x380
252 !! 425 b DataSegment
253 /* Set Wide mode as the "Default" (eg !! 426 #endif /* CONFIG_PPC64BRIDGE */
254 ** First trap occurs *right* after (or !! 427
255 ** Someday, palo might not do this for !! 428 /* Instruction access exception. */
256 */ !! 429 . = 0x400
257 2: !! 430 #ifdef CONFIG_PPC64BRIDGE
>> 431 b InstructionAccess
>> 432 InstructionAccessCont:
>> 433 #else
>> 434 InstructionAccess:
>> 435 EXCEPTION_PROLOG
>> 436 #endif /* CONFIG_PPC64BRIDGE */
>> 437 andis. r0,r9,0x4000 /* no pte found? */
>> 438 beq 1f /* if so, try to put a PTE */
>> 439 li r3,0 /* into the hash table */
>> 440 mr r4,r12 /* SRR0 is fault address */
>> 441 bl hash_page
>> 442 1: addi r3,r1,STACK_FRAME_OVERHEAD
>> 443 mr r4,r12
>> 444 mr r5,r9
>> 445 EXC_XFER_EE_LITE(0x400, do_page_fault)
>> 446
>> 447 #ifdef CONFIG_PPC64BRIDGE
>> 448 /* SLB fault on instruction access. */
>> 449 . = 0x480
>> 450 b InstructionSegment
>> 451 #endif /* CONFIG_PPC64BRIDGE */
>> 452
>> 453 /* External interrupt */
>> 454 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
>> 455
>> 456 /* Alignment exception */
>> 457 . = 0x600
>> 458 Alignment:
>> 459 EXCEPTION_PROLOG
>> 460 mfspr r4,DAR
>> 461 stw r4,_DAR(r11)
>> 462 mfspr r5,DSISR
>> 463 stw r5,_DSISR(r11)
>> 464 addi r3,r1,STACK_FRAME_OVERHEAD
>> 465 EXC_XFER_EE(0x600, AlignmentException)
>> 466
>> 467 /* Program check exception */
>> 468 EXCEPTION(0x700, ProgramCheck, ProgramCheckException, EXC_XFER_EE)
>> 469
>> 470 /* Floating-point unavailable */
>> 471 . = 0x800
>> 472 FPUnavailable:
>> 473 EXCEPTION_PROLOG
>> 474 bne load_up_fpu /* if from user, just load it up */
>> 475 addi r3,r1,STACK_FRAME_OVERHEAD
>> 476 EXC_XFER_EE_LITE(0x800, KernelFP)
>> 477
>> 478 /* Decrementer */
>> 479 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
>> 480
>> 481 EXCEPTION(0xa00, Trap_0a, UnknownException, EXC_XFER_EE)
>> 482 EXCEPTION(0xb00, Trap_0b, UnknownException, EXC_XFER_EE)
>> 483
>> 484 /* System call */
>> 485 . = 0xc00
>> 486 SystemCall:
>> 487 EXCEPTION_PROLOG
>> 488 EXC_XFER_EE_LITE(0xc00, DoSyscall)
>> 489
>> 490 /* Single step - not used on 601 */
>> 491 EXCEPTION(0xd00, SingleStep, SingleStepException, EXC_XFER_EE)
>> 492 EXCEPTION(0xe00, Trap_0e, UnknownException, EXC_XFER_EE)
>> 493
>> 494 /*
>> 495 * The Altivec unavailable trap is at 0x0f20. Foo.
>> 496 * We effectively remap it to 0x3000.
>> 497 */
>> 498 . = 0xf00
258 499
259 ldo PDC_PSW(%r0),%arg0 !! 500 #ifdef CONFIG_ALTIVEC
260 ldo PDC_PSW_SET_DEFAULTS(% !! 501 b Trap_0f
261 ldo PDC_PSW_WIDE_BIT(%r0), !! 502 . = 0xf20
262 load32 PA(stext_pdc_ret), %rp !! 503 b AltiVecUnavailable
263 bv (%r3) !! 504 Trap_0f:
264 copy %r0,%arg3 !! 505 #endif
265 !! 506 EXCEPTION_PROLOG
266 stext_pdc_ret: !! 507 addi r3,r1,STACK_FRAME_OVERHEAD
267 LDREG TASK_PT_GR11(%r6), %r1 !! 508 EXC_XFER_EE(0xf00, UnknownException)
268 tovirt_r1 %r6 !! 509
269 mtctl %r6,%cr30 !! 510 /*
270 #endif !! 511 * Handle TLB miss for instruction on 603/603e.
271 !! 512 * Note: we get an alternate set of r0 - r3 to use automatically.
272 #ifndef CONFIG_64BIT !! 513 */
273 /* clear all BTLBs */ !! 514 . = 0x1000
274 ldi PDC_BLOCK_TLB,%arg0 !! 515 InstructionTLBMiss:
275 load32 PA(stext_pdc_btlb_ret) !! 516 /*
276 ldw MEM_PDC_LO(%r0),%r3 !! 517 * r0: stored ctr
277 bv (%r3) !! 518 * r1: linux style pte ( later becomes ppc hardware pte )
278 ldi PDC_BTLB_PURGE_ALL,%ar !! 519 * r2: ptr to linux-style pte
279 stext_pdc_btlb_ret: !! 520 * r3: scratch
280 #endif !! 521 */
281 !! 522 mfctr r0
282 /* PARANOID: clear user scratch/user s !! 523 /* Get PTE (linux-style) and check access */
283 mtsp %r0,%sr0 !! 524 mfspr r3,IMISS
284 mtsp %r0,%sr1 !! 525 lis r1,KERNELBASE@h /* check if kernel address */
285 mtsp %r0,%sr2 !! 526 cmplw 0,r3,r1
286 mtsp %r0,%sr3 !! 527 mfspr r2,SPRG3
287 !! 528 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
288 /* Initialize Protection Registers */ !! 529 lwz r2,PGDIR(r2)
289 mtctl %r0,%cr8 !! 530 blt+ 112f
290 mtctl %r0,%cr9 !! 531 lis r2,swapper_pg_dir@ha /* if kernel address, use */
291 mtctl %r0,%cr12 !! 532 addi r2,r2,swapper_pg_dir@l /* kernel page table */
292 mtctl %r0,%cr13 !! 533 mfspr r1,SRR1 /* and MSR_PR bit from SRR1 */
293 !! 534 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
294 /* Initialize the global data pointer !! 535 112: tophys(r2,r2)
295 loadgp !! 536 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
296 !! 537 lwz r2,0(r2) /* get pmd entry */
297 /* Set up our interrupt table. HPMCs !! 538 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
298 * !! 539 beq- InstructionAddressInvalid /* return if no mapping */
299 * We need to install the correct iva !! 540 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
300 * following short sequence of instruc !! 541 lwz r3,0(r2) /* get linux-style pte */
301 * (without being illegal on a PA1.1 m !! 542 andc. r1,r1,r3 /* check access & ~permission */
>> 543 bne- InstructionAddressInvalid /* return if access not permitted */
>> 544 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
>> 545 /*
>> 546 * NOTE! We are assuming this is not an SMP system, otherwise
>> 547 * we would need to update the pte atomically with lwarx/stwcx.
302 */ 548 */
303 #ifndef CONFIG_64BIT !! 549 stw r3,0(r2) /* update PTE (accessed bit) */
304 ldi 32,%r10 !! 550 /* Convert linux-style PTE to low word of PPC-style PTE */
305 mtctl %r10,%cr11 !! 551 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
306 .level 2.0 !! 552 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
307 mfctl,w %cr11,%r10 !! 553 and r1,r1,r2 /* writable if _RW and _DIRTY */
308 .level 1.1 !! 554 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
309 comib,<>,n 0,%r10,$is_pa20 !! 555 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
310 ldil L%PA(fault_vector_11), !! 556 ori r1,r1,0xe14 /* clear out reserved bits and M */
311 b $install_iva !! 557 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
312 ldo R%PA(fault_vector_11)( !! 558 mtspr RPA,r1
313 !! 559 mfspr r3,IMISS
314 $is_pa20: !! 560 tlbli r3
315 .level PA_ASM_LEVEL /* restor !! 561 mfspr r3,SRR1 /* Need to restore CR0 */
316 #endif /*!CONFIG_64BIT*/ !! 562 mtcrf 0x80,r3
317 load32 PA(fault_vector_20),%r !! 563 rfi
318 !! 564 InstructionAddressInvalid:
319 $install_iva: !! 565 mfspr r3,SRR1
320 mtctl %r10,%cr14 !! 566 rlwinm r1,r3,9,6,6 /* Get load/store bit */
>> 567
>> 568 addis r1,r1,0x2000
>> 569 mtspr DSISR,r1 /* (shouldn't be needed) */
>> 570 mtctr r0 /* Restore CTR */
>> 571 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
>> 572 or r2,r2,r1
>> 573 mtspr SRR1,r2
>> 574 mfspr r1,IMISS /* Get failing address */
>> 575 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
>> 576 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
>> 577 xor r1,r1,r2
>> 578 mtspr DAR,r1 /* Set fault address */
>> 579 mfmsr r0 /* Restore "normal" registers */
>> 580 xoris r0,r0,MSR_TGPR>>16
>> 581 mtcrf 0x80,r3 /* Restore CR0 */
>> 582 mtmsr r0
>> 583 b InstructionAccess
321 584
322 b aligned_rfi /* Prepar !! 585 /*
323 nop !! 586 * Handle TLB miss for DATA Load operation on 603/603e
>> 587 */
>> 588 . = 0x1100
>> 589 DataLoadTLBMiss:
>> 590 /*
>> 591 * r0: stored ctr
>> 592 * r1: linux style pte ( later becomes ppc hardware pte )
>> 593 * r2: ptr to linux-style pte
>> 594 * r3: scratch
>> 595 */
>> 596 mfctr r0
>> 597 /* Get PTE (linux-style) and check access */
>> 598 mfspr r3,DMISS
>> 599 lis r1,KERNELBASE@h /* check if kernel address */
>> 600 cmplw 0,r3,r1
>> 601 mfspr r2,SPRG3
>> 602 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
>> 603 lwz r2,PGDIR(r2)
>> 604 blt+ 112f
>> 605 lis r2,swapper_pg_dir@ha /* if kernel address, use */
>> 606 addi r2,r2,swapper_pg_dir@l /* kernel page table */
>> 607 mfspr r1,SRR1 /* and MSR_PR bit from SRR1 */
>> 608 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
>> 609 112: tophys(r2,r2)
>> 610 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
>> 611 lwz r2,0(r2) /* get pmd entry */
>> 612 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
>> 613 beq- DataAddressInvalid /* return if no mapping */
>> 614 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
>> 615 lwz r3,0(r2) /* get linux-style pte */
>> 616 andc. r1,r1,r3 /* check access & ~permission */
>> 617 bne- DataAddressInvalid /* return if access not permitted */
>> 618 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
>> 619 /*
>> 620 * NOTE! We are assuming this is not an SMP system, otherwise
>> 621 * we would need to update the pte atomically with lwarx/stwcx.
>> 622 */
>> 623 stw r3,0(r2) /* update PTE (accessed bit) */
>> 624 /* Convert linux-style PTE to low word of PPC-style PTE */
>> 625 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
>> 626 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
>> 627 and r1,r1,r2 /* writable if _RW and _DIRTY */
>> 628 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
>> 629 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
>> 630 ori r1,r1,0xe14 /* clear out reserved bits and M */
>> 631 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
>> 632 mtspr RPA,r1
>> 633 mfspr r3,DMISS
>> 634 tlbld r3
>> 635 mfspr r3,SRR1 /* Need to restore CR0 */
>> 636 mtcrf 0x80,r3
>> 637 rfi
>> 638 DataAddressInvalid:
>> 639 mfspr r3,SRR1
>> 640 rlwinm r1,r3,9,6,6 /* Get load/store bit */
>> 641 addis r1,r1,0x2000
>> 642 mtspr DSISR,r1
>> 643 mtctr r0 /* Restore CTR */
>> 644 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
>> 645 mtspr SRR1,r2
>> 646 mfspr r1,DMISS /* Get failing address */
>> 647 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
>> 648 beq 20f /* Jump if big endian */
>> 649 xori r1,r1,3
>> 650 20: mtspr DAR,r1 /* Set fault address */
>> 651 mfmsr r0 /* Restore "normal" registers */
>> 652 xoris r0,r0,MSR_TGPR>>16
>> 653 mtcrf 0x80,r3 /* Restore CR0 */
>> 654 mtmsr r0
>> 655 b DataAccess
324 656
325 .align 128 !! 657 /*
326 aligned_rfi: !! 658 * Handle TLB miss for DATA Store on 603/603e
327 pcxt_ssm_bug !! 659 */
>> 660 . = 0x1200
>> 661 DataStoreTLBMiss:
>> 662 /*
>> 663 * r0: stored ctr
>> 664 * r1: linux style pte ( later becomes ppc hardware pte )
>> 665 * r2: ptr to linux-style pte
>> 666 * r3: scratch
>> 667 */
>> 668 mfctr r0
>> 669 /* Get PTE (linux-style) and check access */
>> 670 mfspr r3,DMISS
>> 671 lis r1,KERNELBASE@h /* check if kernel address */
>> 672 cmplw 0,r3,r1
>> 673 mfspr r2,SPRG3
>> 674 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
>> 675 lwz r2,PGDIR(r2)
>> 676 blt+ 112f
>> 677 lis r2,swapper_pg_dir@ha /* if kernel address, use */
>> 678 addi r2,r2,swapper_pg_dir@l /* kernel page table */
>> 679 mfspr r1,SRR1 /* and MSR_PR bit from SRR1 */
>> 680 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
>> 681 112: tophys(r2,r2)
>> 682 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
>> 683 lwz r2,0(r2) /* get pmd entry */
>> 684 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
>> 685 beq- DataAddressInvalid /* return if no mapping */
>> 686 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
>> 687 lwz r3,0(r2) /* get linux-style pte */
>> 688 andc. r1,r1,r3 /* check access & ~permission */
>> 689 bne- DataAddressInvalid /* return if access not permitted */
>> 690 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
>> 691 /*
>> 692 * NOTE! We are assuming this is not an SMP system, otherwise
>> 693 * we would need to update the pte atomically with lwarx/stwcx.
>> 694 */
>> 695 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
>> 696 /* Convert linux-style PTE to low word of PPC-style PTE */
>> 697 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
>> 698 li r1,0xe15 /* clear out reserved bits and M */
>> 699 andc r1,r3,r1 /* PP = user? 2: 0 */
>> 700 mtspr RPA,r1
>> 701 mfspr r3,DMISS
>> 702 tlbld r3
>> 703 mfspr r3,SRR1 /* Need to restore CR0 */
>> 704 mtcrf 0x80,r3
>> 705 rfi
328 706
329 copy %r3, %arg0 /* PDC !! 707 #ifndef CONFIG_ALTIVEC
>> 708 #define AltivecAssistException UnknownException
>> 709 #endif
>> 710 EXCEPTION(0x1300, Trap_13, InstructionBreakpoint, EXC_XFER_EE)
>> 711 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
>> 712 EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
>> 713 #ifdef CONFIG_POWER4
>> 714 EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
>> 715 EXCEPTION(0x1700, Trap_17, AltivecAssistException, EXC_XFER_EE)
>> 716 EXCEPTION(0x1800, Trap_18, TAUException, EXC_XFER_STD)
>> 717 #else /* !CONFIG_POWER4 */
>> 718 EXCEPTION(0x1600, Trap_16, AltivecAssistException, EXC_XFER_EE)
>> 719 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
>> 720 EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
>> 721 #endif /* CONFIG_POWER4 */
>> 722 EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
>> 723 EXCEPTION(0x1a00, Trap_1a, UnknownException, EXC_XFER_EE)
>> 724 EXCEPTION(0x1b00, Trap_1b, UnknownException, EXC_XFER_EE)
>> 725 EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE)
>> 726 EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE)
>> 727 EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE)
>> 728 EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE)
>> 729 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
>> 730 EXCEPTION(0x2100, Trap_21, UnknownException, EXC_XFER_EE)
>> 731 EXCEPTION(0x2200, Trap_22, UnknownException, EXC_XFER_EE)
>> 732 EXCEPTION(0x2300, Trap_23, UnknownException, EXC_XFER_EE)
>> 733 EXCEPTION(0x2400, Trap_24, UnknownException, EXC_XFER_EE)
>> 734 EXCEPTION(0x2500, Trap_25, UnknownException, EXC_XFER_EE)
>> 735 EXCEPTION(0x2600, Trap_26, UnknownException, EXC_XFER_EE)
>> 736 EXCEPTION(0x2700, Trap_27, UnknownException, EXC_XFER_EE)
>> 737 EXCEPTION(0x2800, Trap_28, UnknownException, EXC_XFER_EE)
>> 738 EXCEPTION(0x2900, Trap_29, UnknownException, EXC_XFER_EE)
>> 739 EXCEPTION(0x2a00, Trap_2a, UnknownException, EXC_XFER_EE)
>> 740 EXCEPTION(0x2b00, Trap_2b, UnknownException, EXC_XFER_EE)
>> 741 EXCEPTION(0x2c00, Trap_2c, UnknownException, EXC_XFER_EE)
>> 742 EXCEPTION(0x2d00, Trap_2d, UnknownException, EXC_XFER_EE)
>> 743 EXCEPTION(0x2e00, Trap_2e, UnknownException, EXC_XFER_EE)
>> 744 EXCEPTION(0x2f00, MOLTrampoline, UnknownException, EXC_XFER_EE_LITE)
>> 745
>> 746 .globl mol_trampoline
>> 747 .set mol_trampoline, i0x2f00
>> 748
>> 749 . = 0x3000
>> 750
>> 751 #ifdef CONFIG_ALTIVEC
>> 752 AltiVecUnavailable:
>> 753 EXCEPTION_PROLOG
>> 754 bne load_up_altivec /* if from user, just load it up */
>> 755 EXC_XFER_EE_LITE(0xf20, KernelAltiVec)
>> 756 #endif /* CONFIG_ALTIVEC */
>> 757
>> 758 #ifdef CONFIG_PPC64BRIDGE
>> 759 DataAccess:
>> 760 EXCEPTION_PROLOG
>> 761 b DataAccessCont
>> 762
>> 763 InstructionAccess:
>> 764 EXCEPTION_PROLOG
>> 765 b InstructionAccessCont
>> 766
>> 767 DataSegment:
>> 768 EXCEPTION_PROLOG
>> 769 addi r3,r1,STACK_FRAME_OVERHEAD
>> 770 mfspr r4,DAR
>> 771 stw r4,_DAR(r11)
>> 772 EXC_XFER_STD(0x380, UnknownException)
>> 773
>> 774 InstructionSegment:
>> 775 EXCEPTION_PROLOG
>> 776 addi r3,r1,STACK_FRAME_OVERHEAD
>> 777 EXC_XFER_STD(0x480, UnknownException)
>> 778 #endif /* CONFIG_PPC64BRIDGE */
>> 779
>> 780 /*
>> 781 * This task wants to use the FPU now.
>> 782 * On UP, disable FP for the task which had the FPU previously,
>> 783 * and save its floating-point registers in its thread_struct.
>> 784 * Load up this task's FP registers from its thread_struct,
>> 785 * enable the FPU for the current task and return to the task.
>> 786 */
>> 787 load_up_fpu:
>> 788 mfmsr r5
>> 789 ori r5,r5,MSR_FP
>> 790 #ifdef CONFIG_PPC64BRIDGE
>> 791 clrldi r5,r5,1 /* turn off 64-bit mode */
>> 792 #endif /* CONFIG_PPC64BRIDGE */
>> 793 SYNC
>> 794 MTMSRD(r5) /* enable use of fpu now */
>> 795 isync
>> 796 /*
>> 797 * For SMP, we don't do lazy FPU switching because it just gets too
>> 798 * horrendously complex, especially when a task switches from one CPU
>> 799 * to another. Instead we call giveup_fpu in switch_to.
>> 800 */
>> 801 #ifndef CONFIG_SMP
>> 802 tophys(r6,0) /* get __pa constant */
>> 803 addis r3,r6,last_task_used_math@ha
>> 804 lwz r4,last_task_used_math@l(r3)
>> 805 cmpi 0,r4,0
>> 806 beq 1f
>> 807 add r4,r4,r6
>> 808 addi r4,r4,THREAD /* want last_task_used_math->thread */
>> 809 SAVE_32FPRS(0, r4)
>> 810 mffs fr0
>> 811 stfd fr0,THREAD_FPSCR-4(r4)
>> 812 lwz r5,PT_REGS(r4)
>> 813 add r5,r5,r6
>> 814 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 815 li r10,MSR_FP|MSR_FE0|MSR_FE1
>> 816 andc r4,r4,r10 /* disable FP for previous task */
>> 817 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 818 1:
>> 819 #endif /* CONFIG_SMP */
>> 820 /* enable use of FP after return */
>> 821 mfspr r5,SPRG3 /* current task's THREAD (phys) */
>> 822 lwz r4,THREAD_FPEXC_MODE(r5)
>> 823 ori r9,r9,MSR_FP /* enable FP for current */
>> 824 or r9,r9,r4
>> 825 lfd fr0,THREAD_FPSCR-4(r5)
>> 826 mtfsf 0xff,fr0
>> 827 REST_32FPRS(0, r5)
>> 828 #ifndef CONFIG_SMP
>> 829 subi r4,r5,THREAD
>> 830 sub r4,r4,r6
>> 831 stw r4,last_task_used_math@l(r3)
>> 832 #endif /* CONFIG_SMP */
>> 833 /* restore registers and return */
>> 834 /* we haven't used ctr or xer or lr */
>> 835 /* fall through to fast_exception_return */
>> 836
>> 837 .globl fast_exception_return
>> 838 fast_exception_return:
>> 839 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
>> 840 beq 1f /* if not, we've got problems */
>> 841 2: REST_4GPRS(3, r11)
>> 842 lwz r10,_CCR(r11)
>> 843 REST_GPR(1, r11)
>> 844 mtcr r10
>> 845 lwz r10,_LINK(r11)
>> 846 mtlr r10
>> 847 REST_GPR(10, r11)
>> 848 mtspr SRR1,r9
>> 849 mtspr SRR0,r12
>> 850 REST_GPR(9, r11)
>> 851 REST_GPR(12, r11)
>> 852 lwz r11,GPR11(r11)
>> 853 SYNC
>> 854 RFI
>> 855
>> 856 /* check if the exception happened in a restartable section */
>> 857 1: lis r3,exc_exit_restart_end@ha
>> 858 addi r3,r3,exc_exit_restart_end@l
>> 859 cmplw r12,r3
>> 860 bge 3f
>> 861 lis r4,exc_exit_restart@ha
>> 862 addi r4,r4,exc_exit_restart@l
>> 863 cmplw r12,r4
>> 864 blt 3f
>> 865 lis r3,fee_restarts@ha
>> 866 tophys(r3,r3)
>> 867 lwz r5,fee_restarts@l(r3)
>> 868 addi r5,r5,1
>> 869 stw r5,fee_restarts@l(r3)
>> 870 mr r12,r4 /* restart at exc_exit_restart */
>> 871 b 2b
>> 872
>> 873 .comm fee_restarts,4
>> 874
>> 875 /* aargh, a nonrecoverable interrupt, panic */
>> 876 /* aargh, we don't know which trap this is */
>> 877 /* but the 601 doesn't implement the RI bit, so assume it's OK */
>> 878 3:
>> 879 BEGIN_FTR_SECTION
>> 880 b 2b
>> 881 END_FTR_SECTION_IFSET(CPU_FTR_601)
>> 882 li r10,-1
>> 883 stw r10,TRAP(r11)
>> 884 addi r3,r1,STACK_FRAME_OVERHEAD
>> 885 li r10,MSR_KERNEL
>> 886 bl transfer_to_handler_full
>> 887 .long nonrecoverable_exception
>> 888 .long ret_from_except
>> 889
>> 890 /*
>> 891 * FP unavailable trap from kernel - print a message, but let
>> 892 * the task use FP in the kernel until it returns to user mode.
>> 893 */
>> 894 KernelFP:
>> 895 lwz r3,_MSR(r1)
>> 896 ori r3,r3,MSR_FP
>> 897 stw r3,_MSR(r1) /* enable use of FP after return */
>> 898 lis r3,86f@h
>> 899 ori r3,r3,86f@l
>> 900 mr r4,r2 /* current */
>> 901 lwz r5,_NIP(r1)
>> 902 bl printk
>> 903 b ret_from_except
>> 904 86: .string "floating point used in kernel (task=%p, pc=%x)\n"
>> 905 .align 4,0
>> 906
>> 907 #ifdef CONFIG_ALTIVEC
>> 908 /* Note that the AltiVec support is closely modeled after the FP
>> 909 * support. Changes to one are likely to be applicable to the
>> 910 * other! */
>> 911 load_up_altivec:
>> 912 /*
>> 913 * Disable AltiVec for the task which had AltiVec previously,
>> 914 * and save its AltiVec registers in its thread_struct.
>> 915 * Enables AltiVec for use in the kernel on return.
>> 916 * On SMP we know the AltiVec units are free, since we give it up every
>> 917 * switch. -- Kumar
>> 918 */
>> 919 mfmsr r5
>> 920 oris r5,r5,MSR_VEC@h
>> 921 MTMSRD(r5) /* enable use of AltiVec now */
>> 922 isync
>> 923 /*
>> 924 * For SMP, we don't do lazy AltiVec switching because it just gets too
>> 925 * horrendously complex, especially when a task switches from one CPU
>> 926 * to another. Instead we call giveup_altivec in switch_to.
>> 927 */
>> 928 #ifndef CONFIG_SMP
>> 929 tophys(r6,0)
>> 930 addis r3,r6,last_task_used_altivec@ha
>> 931 lwz r4,last_task_used_altivec@l(r3)
>> 932 cmpi 0,r4,0
>> 933 beq 1f
>> 934 add r4,r4,r6
>> 935 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
>> 936 SAVE_32VR(0,r10,r4)
>> 937 mfvscr vr0
>> 938 li r10,THREAD_VSCR
>> 939 stvx vr0,r10,r4
>> 940 lwz r5,PT_REGS(r4)
>> 941 add r5,r5,r6
>> 942 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 943 lis r10,MSR_VEC@h
>> 944 andc r4,r4,r10 /* disable altivec for previous task */
>> 945 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 946 1:
>> 947 #endif /* CONFIG_SMP */
>> 948 /* enable use of AltiVec after return */
>> 949 oris r9,r9,MSR_VEC@h
>> 950 mfspr r5,SPRG3 /* current task's THREAD (phys) */
>> 951 li r4,1
>> 952 li r10,THREAD_VSCR
>> 953 stw r4,THREAD_USED_VR(r5)
>> 954 lvx vr0,r10,r5
>> 955 mtvscr vr0
>> 956 REST_32VR(0,r10,r5)
>> 957 #ifndef CONFIG_SMP
>> 958 subi r4,r5,THREAD
>> 959 sub r4,r4,r6
>> 960 stw r4,last_task_used_altivec@l(r3)
>> 961 #endif /* CONFIG_SMP */
>> 962 /* restore registers and return */
>> 963 /* we haven't used ctr or xer or lr */
>> 964 b fast_exception_return
>> 965
>> 966 /*
>> 967 * AltiVec unavailable trap from kernel - print a message, but let
>> 968 * the task use AltiVec in the kernel until it returns to user mode.
>> 969 */
>> 970 KernelAltiVec:
>> 971 lwz r3,_MSR(r1)
>> 972 oris r3,r3,MSR_VEC@h
>> 973 stw r3,_MSR(r1) /* enable use of AltiVec after return */
>> 974 lis r3,87f@h
>> 975 ori r3,r3,87f@l
>> 976 mr r4,r2 /* current */
>> 977 lwz r5,_NIP(r1)
>> 978 bl printk
>> 979 b ret_from_except
>> 980 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
>> 981 .align 4,0
>> 982
>> 983 /*
>> 984 * giveup_altivec(tsk)
>> 985 * Disable AltiVec for the task given as the argument,
>> 986 * and save the AltiVec registers in its thread_struct.
>> 987 * Enables AltiVec for use in the kernel on return.
>> 988 */
330 989
331 rsm PSW_SM_QUIET,%r0 !! 990 .globl giveup_altivec
332 /* Don't need NOPs, have 8 compliant i !! 991 giveup_altivec:
>> 992 mfmsr r5
>> 993 oris r5,r5,MSR_VEC@h
>> 994 SYNC
>> 995 MTMSRD(r5) /* enable use of AltiVec now */
>> 996 isync
>> 997 cmpi 0,r3,0
>> 998 beqlr- /* if no previous owner, done */
>> 999 addi r3,r3,THREAD /* want THREAD of task */
>> 1000 lwz r5,PT_REGS(r3)
>> 1001 cmpi 0,r5,0
>> 1002 SAVE_32VR(0, r4, r3)
>> 1003 mfvscr vr0
>> 1004 li r4,THREAD_VSCR
>> 1005 stvx vr0,r4,r3
>> 1006 beq 1f
>> 1007 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 1008 lis r3,MSR_VEC@h
>> 1009 andc r4,r4,r3 /* disable AltiVec for previous task */
>> 1010 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 1011 1:
>> 1012 #ifndef CONFIG_SMP
>> 1013 li r5,0
>> 1014 lis r4,last_task_used_altivec@ha
>> 1015 stw r5,last_task_used_altivec@l(r4)
>> 1016 #endif /* CONFIG_SMP */
>> 1017 blr
>> 1018 #endif /* CONFIG_ALTIVEC */
333 1019
334 mtctl %r0,%cr17 /* Cle !! 1020 /*
335 mtctl %r0,%cr17 /* Cle !! 1021 * giveup_fpu(tsk)
>> 1022 * Disable FP for the task given as the argument,
>> 1023 * and save the floating-point registers in its thread_struct.
>> 1024 * Enables the FPU for use in the kernel on return.
>> 1025 */
>> 1026 .globl giveup_fpu
>> 1027 giveup_fpu:
>> 1028 mfmsr r5
>> 1029 ori r5,r5,MSR_FP
>> 1030 SYNC_601
>> 1031 ISYNC_601
>> 1032 MTMSRD(r5) /* enable use of fpu now */
>> 1033 SYNC_601
>> 1034 isync
>> 1035 cmpi 0,r3,0
>> 1036 beqlr- /* if no previous owner, done */
>> 1037 addi r3,r3,THREAD /* want THREAD of task */
>> 1038 lwz r5,PT_REGS(r3)
>> 1039 cmpi 0,r5,0
>> 1040 SAVE_32FPRS(0, r3)
>> 1041 mffs fr0
>> 1042 stfd fr0,THREAD_FPSCR-4(r3)
>> 1043 beq 1f
>> 1044 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 1045 li r3,MSR_FP|MSR_FE0|MSR_FE1
>> 1046 andc r4,r4,r3 /* disable FP for previous task */
>> 1047 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
>> 1048 1:
>> 1049 #ifndef CONFIG_SMP
>> 1050 li r5,0
>> 1051 lis r4,last_task_used_math@ha
>> 1052 stw r5,last_task_used_math@l(r4)
>> 1053 #endif /* CONFIG_SMP */
>> 1054 blr
336 1055
337 /* Load RFI target into PC queue */ !! 1056 /*
338 mtctl %r11,%cr18 /* IIA !! 1057 * This code is jumped to from the startup code to copy
339 ldo 4(%r11),%r11 !! 1058 * the kernel image to physical address 0.
340 mtctl %r11,%cr18 /* IIA !! 1059 */
>> 1060 relocate_kernel:
>> 1061 addis r9,r26,klimit@ha /* fetch klimit */
>> 1062 lwz r25,klimit@l(r9)
>> 1063 addis r25,r25,-KERNELBASE@h
>> 1064 li r3,0 /* Destination base address */
>> 1065 li r6,0 /* Destination offset */
>> 1066 li r5,0x4000 /* # bytes of memory to copy */
>> 1067 bl copy_and_flush /* copy the first 0x4000 bytes */
>> 1068 addi r0,r3,4f@l /* jump to the address of 4f */
>> 1069 mtctr r0 /* in copy and do the rest. */
>> 1070 bctr /* jump to the copy */
>> 1071 4: mr r5,r25
>> 1072 bl copy_and_flush /* copy the rest */
>> 1073 b turn_on_mmu
>> 1074
>> 1075 /*
>> 1076 * Copy routine used to copy the kernel to start at physical address 0
>> 1077 * and flush and invalidate the caches as needed.
>> 1078 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
>> 1079 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
>> 1080 */
>> 1081 copy_and_flush:
>> 1082 addi r5,r5,-4
>> 1083 addi r6,r6,-4
>> 1084 4: li r0,L1_CACHE_LINE_SIZE/4
>> 1085 mtctr r0
>> 1086 3: addi r6,r6,4 /* copy a cache line */
>> 1087 lwzx r0,r6,r4
>> 1088 stwx r0,r6,r3
>> 1089 bdnz 3b
>> 1090 dcbst r6,r3 /* write it to memory */
>> 1091 sync
>> 1092 icbi r6,r3 /* flush the icache line */
>> 1093 cmplw 0,r6,r5
>> 1094 blt 4b
>> 1095 sync /* additional sync needed on g4 */
>> 1096 isync
>> 1097 addi r5,r5,4
>> 1098 addi r6,r6,4
>> 1099 blr
>> 1100
>> 1101 #ifdef CONFIG_APUS
>> 1102 /*
>> 1103 * On APUS the physical base address of the kernel is not known at compile
>> 1104 * time, which means the __pa/__va constants used are incorrect. In the
>> 1105 * __init section is recorded the virtual addresses of instructions using
>> 1106 * these constants, so all that has to be done is fix these before
>> 1107 * continuing the kernel boot.
>> 1108 *
>> 1109 * r4 = The physical address of the kernel base.
>> 1110 */
>> 1111 fix_mem_constants:
>> 1112 mr r10,r4
>> 1113 addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
>> 1114 neg r11,r10 /* phys_to_virt constant */
>> 1115
>> 1116 lis r12,__vtop_table_begin@h
>> 1117 ori r12,r12,__vtop_table_begin@l
>> 1118 add r12,r12,r10 /* table begin phys address */
>> 1119 lis r13,__vtop_table_end@h
>> 1120 ori r13,r13,__vtop_table_end@l
>> 1121 add r13,r13,r10 /* table end phys address */
>> 1122 subi r12,r12,4
>> 1123 subi r13,r13,4
>> 1124 1: lwzu r14,4(r12) /* virt address of instruction */
>> 1125 add r14,r14,r10 /* phys address of instruction */
>> 1126 lwz r15,0(r14) /* instruction, now insert top */
>> 1127 rlwimi r15,r10,16,16,31 /* half of vp const in low half */
>> 1128 stw r15,0(r14) /* of instruction and restore. */
>> 1129 dcbst r0,r14 /* write it to memory */
>> 1130 sync
>> 1131 icbi r0,r14 /* flush the icache line */
>> 1132 cmpw r12,r13
>> 1133 bne 1b
>> 1134 sync /* additional sync needed on g4 */
>> 1135 isync
>> 1136
>> 1137 /*
>> 1138 * Map the memory where the exception handlers will
>> 1139 * be copied to when hash constants have been patched.
>> 1140 */
>> 1141 #ifdef CONFIG_APUS_FAST_EXCEPT
>> 1142 lis r8,0xfff0
>> 1143 #else
>> 1144 lis r8,0
>> 1145 #endif
>> 1146 ori r8,r8,0x2 /* 128KB, supervisor */
>> 1147 mtspr DBAT3U,r8
>> 1148 mtspr DBAT3L,r8
>> 1149
>> 1150 lis r12,__ptov_table_begin@h
>> 1151 ori r12,r12,__ptov_table_begin@l
>> 1152 add r12,r12,r10 /* table begin phys address */
>> 1153 lis r13,__ptov_table_end@h
>> 1154 ori r13,r13,__ptov_table_end@l
>> 1155 add r13,r13,r10 /* table end phys address */
>> 1156 subi r12,r12,4
>> 1157 subi r13,r13,4
>> 1158 1: lwzu r14,4(r12) /* virt address of instruction */
>> 1159 add r14,r14,r10 /* phys address of instruction */
>> 1160 lwz r15,0(r14) /* instruction, now insert top */
>> 1161 rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
>> 1162 stw r15,0(r14) /* of instruction and restore. */
>> 1163 dcbst r0,r14 /* write it to memory */
>> 1164 sync
>> 1165 icbi r0,r14 /* flush the icache line */
>> 1166 cmpw r12,r13
>> 1167 bne 1b
>> 1168
>> 1169 sync /* additional sync needed on g4 */
>> 1170 isync /* No speculative loading until now */
>> 1171 blr
>> 1172
>> 1173 /***********************************************************************
>> 1174 * Please note that on APUS the exception handlers are located at the
>> 1175 * physical address 0xfff0000. For this reason, the exception handlers
>> 1176 * cannot use relative branches to access the code below.
>> 1177 ***********************************************************************/
>> 1178 #endif /* CONFIG_APUS */
341 1179
342 load32 KERNEL_PSW,%r10 !! 1180 #ifdef CONFIG_SMP
343 mtctl %r10,%ipsw !! 1181 #ifdef CONFIG_GEMINI
>> 1182 .globl __secondary_start_gemini
>> 1183 __secondary_start_gemini:
>> 1184 mfspr r4,HID0
>> 1185 ori r4,r4,HID0_ICFI
>> 1186 li r3,0
>> 1187 ori r3,r3,HID0_ICE
>> 1188 andc r4,r4,r3
>> 1189 mtspr HID0,r4
>> 1190 sync
>> 1191 bl gemini_prom_init
>> 1192 b __secondary_start
>> 1193 #endif /* CONFIG_GEMINI */
>> 1194 .globl __secondary_start_psurge
>> 1195 __secondary_start_psurge:
>> 1196 li r24,1 /* cpu # */
>> 1197 b __secondary_start_psurge99
>> 1198 .globl __secondary_start_psurge2
>> 1199 __secondary_start_psurge2:
>> 1200 li r24,2 /* cpu # */
>> 1201 b __secondary_start_psurge99
>> 1202 .globl __secondary_start_psurge3
>> 1203 __secondary_start_psurge3:
>> 1204 li r24,3 /* cpu # */
>> 1205 b __secondary_start_psurge99
>> 1206 __secondary_start_psurge99:
>> 1207 /* we come in here with IR=0 and DR=1, and DBAT 0
>> 1208 set to map the 0xf0000000 - 0xffffffff region */
>> 1209 mfmsr r0
>> 1210 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
>> 1211 SYNC
>> 1212 mtmsr r0
>> 1213 isync
>> 1214
>> 1215 .globl __secondary_start
>> 1216 __secondary_start:
>> 1217 #ifdef CONFIG_PPC64BRIDGE
>> 1218 mfmsr r0
>> 1219 clrldi r0,r0,1 /* make sure it's in 32-bit mode */
>> 1220 SYNC
>> 1221 MTMSRD(r0)
>> 1222 isync
>> 1223 #endif
>> 1224 /* Copy some CPU settings from CPU 0 */
>> 1225 bl __restore_cpu_setup
344 1226
345 tovirt_r1 %sp !! 1227 lis r3,-KERNELBASE@h
>> 1228 mr r4,r24
>> 1229 bl identify_cpu
>> 1230 bl call_setup_cpu /* Call setup_cpu for this CPU */
>> 1231 #ifdef CONFIG_6xx
>> 1232 lis r3,-KERNELBASE@h
>> 1233 bl init_idle_6xx
>> 1234 #endif /* CONFIG_6xx */
>> 1235 #ifdef CONFIG_POWER4
>> 1236 lis r3,-KERNELBASE@h
>> 1237 bl init_idle_power4
>> 1238 #endif /* CONFIG_POWER4 */
>> 1239
>> 1240 /* get current_thread_info and current */
>> 1241 lis r1,secondary_ti@ha
>> 1242 tophys(r1,r1)
>> 1243 lwz r1,secondary_ti@l(r1)
>> 1244 tophys(r2,r1)
>> 1245 lwz r2,TI_TASK(r2)
>> 1246
>> 1247 /* stack */
>> 1248 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
>> 1249 li r0,0
>> 1250 tophys(r3,r1)
>> 1251 stw r0,0(r3)
>> 1252
>> 1253 /* load up the MMU */
>> 1254 bl load_up_mmu
>> 1255
>> 1256 /* ptr to phys current thread */
>> 1257 tophys(r4,r2)
>> 1258 addi r4,r4,THREAD /* phys address of our thread_struct */
>> 1259 CLR_TOP32(r4)
>> 1260 mtspr SPRG3,r4
>> 1261 li r3,0
>> 1262 mtspr SPRG2,r3 /* 0 => not in RTAS */
>> 1263
>> 1264 /* enable MMU and jump to start_secondary */
>> 1265 li r4,MSR_KERNEL
>> 1266 FIX_SRR1(r4,r5)
>> 1267 lis r3,start_secondary@h
>> 1268 ori r3,r3,start_secondary@l
>> 1269 mtspr SRR0,r3
>> 1270 mtspr SRR1,r4
>> 1271 SYNC
>> 1272 RFI
>> 1273 #endif /* CONFIG_SMP */
346 1274
347 /* Jump through hyperspace to Virt Mod !! 1275 /*
348 rfi !! 1276 * Those generic dummy functions are kept for CPUs not
349 nop !! 1277 * included in CONFIG_6xx
>> 1278 */
>> 1279 _GLOBAL(__setup_cpu_power3)
>> 1280 blr
>> 1281 _GLOBAL(__setup_cpu_power4)
>> 1282 blr
>> 1283 _GLOBAL(__setup_cpu_ppc970)
>> 1284 blr
>> 1285 _GLOBAL(__setup_cpu_generic)
>> 1286 blr
>> 1287
>> 1288 #ifndef CONFIG_6xx
>> 1289 _GLOBAL(__save_cpu_setup)
>> 1290 blr
>> 1291 _GLOBAL(__restore_cpu_setup)
>> 1292 #ifdef CONFIG_POWER4
>> 1293 /* turn off real-mode cache inhibit on the PPC970 */
>> 1294 mfspr r0,SPRN_PVR
>> 1295 srwi r0,r0,16
>> 1296 cmpwi r0,0x39
>> 1297 beq ppc970_setup_hid
>> 1298 #endif
>> 1299 blr
>> 1300 #endif /* CONFIG_6xx */
350 1301
351 .procend <<
352 1302
353 #ifdef CONFIG_SMP !! 1303 /*
>> 1304 * Load stuff into the MMU. Intended to be called with
>> 1305 * IR=0 and DR=0.
>> 1306 */
>> 1307 load_up_mmu:
>> 1308 sync /* Force all PTE updates to finish */
>> 1309 isync
>> 1310 tlbia /* Clear all TLB entries */
>> 1311 sync /* wait for tlbia/tlbie to finish */
>> 1312 TLBSYNC /* ... on all CPUs */
>> 1313 /* Load the SDR1 register (hash table base & size) */
>> 1314 lis r6,_SDR1@ha
>> 1315 tophys(r6,r6)
>> 1316 lwz r6,_SDR1@l(r6)
>> 1317 mtspr SDR1,r6
>> 1318 #ifdef CONFIG_PPC64BRIDGE
>> 1319 /* clear the ASR so we only use the pseudo-segment registers. */
>> 1320 li r6,0
>> 1321 mtasr r6
>> 1322 #endif /* CONFIG_PPC64BRIDGE */
>> 1323 li r0,16 /* load up segment register values */
>> 1324 mtctr r0 /* for context 0 */
>> 1325 lis r3,0x2000 /* Ku = 1, VSID = 0 */
>> 1326 li r4,0
>> 1327 3: mtsrin r3,r4
>> 1328 addi r3,r3,0x111 /* increment VSID */
>> 1329 addis r4,r4,0x1000 /* address of next segment */
>> 1330 bdnz 3b
>> 1331 #ifndef CONFIG_POWER4
>> 1332 /* Load the BAT registers with the values set up by MMU_init.
>> 1333 MMU_init takes care of whether we're on a 601 or not. */
>> 1334 mfpvr r3
>> 1335 srwi r3,r3,16
>> 1336 cmpwi r3,1
>> 1337 lis r3,BATS@ha
>> 1338 addi r3,r3,BATS@l
>> 1339 tophys(r3,r3)
>> 1340 LOAD_BAT(0,r3,r4,r5)
>> 1341 LOAD_BAT(1,r3,r4,r5)
>> 1342 LOAD_BAT(2,r3,r4,r5)
>> 1343 LOAD_BAT(3,r3,r4,r5)
>> 1344 #endif /* CONFIG_POWER4 */
>> 1345 blr
354 1346
355 .import smp_init_current_idle_task,dat !! 1347 /*
356 .import smp_callin,code !! 1348 * This is where the main kernel code starts.
>> 1349 */
>> 1350 start_here:
>> 1351 /* ptr to current */
>> 1352 lis r2,init_task@h
>> 1353 ori r2,r2,init_task@l
>> 1354 /* Set up for using our exception vectors */
>> 1355 /* ptr to phys current thread */
>> 1356 tophys(r4,r2)
>> 1357 addi r4,r4,THREAD /* init task's THREAD */
>> 1358 CLR_TOP32(r4)
>> 1359 mtspr SPRG3,r4
>> 1360 li r3,0
>> 1361 mtspr SPRG2,r3 /* 0 => not in RTAS */
>> 1362
>> 1363 /* stack */
>> 1364 lis r1,init_thread_union@ha
>> 1365 addi r1,r1,init_thread_union@l
>> 1366 li r0,0
>> 1367 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
>> 1368 /*
>> 1369 * Do early bootinfo parsing, platform-specific initialization,
>> 1370 * and set up the MMU.
>> 1371 */
>> 1372 mr r3,r31
>> 1373 mr r4,r30
>> 1374 mr r5,r29
>> 1375 mr r6,r28
>> 1376 mr r7,r27
>> 1377 bl machine_init
>> 1378 bl MMU_init
>> 1379
>> 1380 #ifdef CONFIG_APUS
>> 1381 /* Copy exception code to exception vector base on APUS. */
>> 1382 lis r4,KERNELBASE@h
>> 1383 #ifdef CONFIG_APUS_FAST_EXCEPT
>> 1384 lis r3,0xfff0 /* Copy to 0xfff00000 */
>> 1385 #else
>> 1386 lis r3,0 /* Copy to 0x00000000 */
>> 1387 #endif
>> 1388 li r5,0x4000 /* # bytes of memory to copy */
>> 1389 li r6,0
>> 1390 bl copy_and_flush /* copy the first 0x4000 bytes */
>> 1391 #endif /* CONFIG_APUS */
>> 1392
>> 1393 /*
>> 1394 * Go back to running unmapped so we can load up new values
>> 1395 * for SDR1 (hash table pointer) and the segment registers
>> 1396 * and change to using our exception vectors.
>> 1397 */
>> 1398 lis r4,2f@h
>> 1399 ori r4,r4,2f@l
>> 1400 tophys(r4,r4)
>> 1401 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
>> 1402 FIX_SRR1(r3,r5)
>> 1403 mtspr SRR0,r4
>> 1404 mtspr SRR1,r3
>> 1405 SYNC
>> 1406 RFI
>> 1407 /* Load up the kernel context */
>> 1408 2: bl load_up_mmu
>> 1409
>> 1410 #ifdef CONFIG_BDI_SWITCH
>> 1411 /* Add helper information for the Abatron bdiGDB debugger.
>> 1412 * We do this here because we know the mmu is disabled, and
>> 1413 * will be enabled for real in just a few instructions.
>> 1414 */
>> 1415 lis r5, abatron_pteptrs@h
>> 1416 ori r5, r5, abatron_pteptrs@l
>> 1417 stw r5, 0xf0(r0) /* This much match your Abatron config */
>> 1418 lis r6, swapper_pg_dir@h
>> 1419 ori r6, r6, swapper_pg_dir@l
>> 1420 tophys(r5, r5)
>> 1421 stw r6, 0(r5)
>> 1422 #endif /* CONFIG_BDI_SWITCH */
>> 1423
>> 1424 /* Now turn on the MMU for real! */
>> 1425 li r4,MSR_KERNEL
>> 1426 FIX_SRR1(r4,r5)
>> 1427 lis r3,start_kernel@h
>> 1428 ori r3,r3,start_kernel@l
>> 1429 mtspr SRR0,r3
>> 1430 mtspr SRR1,r4
>> 1431 SYNC
>> 1432 RFI
357 1433
358 #ifndef CONFIG_64BIT !! 1434 /*
359 smp_callin_rtn: !! 1435 * Set up the segment registers for a new context.
360 .proc !! 1436 */
361 .callinfo !! 1437 _GLOBAL(set_context)
362 break 1,1 /* Break if r !! 1438 mulli r3,r3,897 /* multiply context by skew factor */
363 nop !! 1439 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
364 nop !! 1440 addis r3,r3,0x6000 /* Set Ks, Ku bits */
365 .procend !! 1441 li r0,NUM_USER_SEGMENTS
366 #endif /*!CONFIG_64BIT*/ !! 1442 mtctr r0
>> 1443
>> 1444 #ifdef CONFIG_BDI_SWITCH
>> 1445 /* Context switch the PTE pointer for the Abatron BDI2000.
>> 1446 * The PGDIR is passed as second argument.
>> 1447 */
>> 1448 lis r5, KERNELBASE@h
>> 1449 lwz r5, 0xf0(r5)
>> 1450 stw r4, 0x4(r5)
>> 1451 #endif
>> 1452 li r4,0
>> 1453 BEGIN_FTR_SECTION
>> 1454 dssall
>> 1455 sync
>> 1456 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
>> 1457 3: isync
>> 1458 #ifdef CONFIG_PPC64BRIDGE
>> 1459 slbie r4
>> 1460 #endif /* CONFIG_PPC64BRIDGE */
>> 1461 mtsrin r3,r4
>> 1462 addi r3,r3,0x111 /* next VSID */
>> 1463 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
>> 1464 addis r4,r4,0x1000 /* address of next segment */
>> 1465 bdnz 3b
>> 1466 sync
>> 1467 isync
>> 1468 blr
>> 1469
>> 1470 /*
>> 1471 * An undocumented "feature" of 604e requires that the v bit
>> 1472 * be cleared before changing BAT values.
>> 1473 *
>> 1474 * Also, newer IBM firmware does not clear bat3 and 4 so
>> 1475 * this makes sure it's done.
>> 1476 * -- Cort
>> 1477 */
>> 1478 clear_bats:
>> 1479 li r10,0
>> 1480 mfspr r9,PVR
>> 1481 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
>> 1482 cmpwi r9, 1
>> 1483 beq 1f
>> 1484
>> 1485 mtspr DBAT0U,r10
>> 1486 mtspr DBAT0L,r10
>> 1487 mtspr DBAT1U,r10
>> 1488 mtspr DBAT1L,r10
>> 1489 mtspr DBAT2U,r10
>> 1490 mtspr DBAT2L,r10
>> 1491 mtspr DBAT3U,r10
>> 1492 mtspr DBAT3L,r10
>> 1493 1:
>> 1494 mtspr IBAT0U,r10
>> 1495 mtspr IBAT0L,r10
>> 1496 mtspr IBAT1U,r10
>> 1497 mtspr IBAT1L,r10
>> 1498 mtspr IBAT2U,r10
>> 1499 mtspr IBAT2L,r10
>> 1500 mtspr IBAT3U,r10
>> 1501 mtspr IBAT3L,r10
>> 1502 BEGIN_FTR_SECTION
>> 1503 /* Here's a tweak: at this point, CPU setup have
>> 1504 * not been called yet, so HIGH_BAT_EN may not be
>> 1505 * set in HID0 for the 745x processors. However, it
>> 1506 * seems that doesn't affect our ability to actually
>> 1507 * write to these SPRs.
>> 1508 */
>> 1509 mtspr SPRN_DBAT4U,r20
>> 1510 mtspr SPRN_DBAT4L,r20
>> 1511 mtspr SPRN_DBAT5U,r20
>> 1512 mtspr SPRN_DBAT5L,r20
>> 1513 mtspr SPRN_DBAT6U,r20
>> 1514 mtspr SPRN_DBAT6L,r20
>> 1515 mtspr SPRN_DBAT7U,r20
>> 1516 mtspr SPRN_DBAT7L,r20
>> 1517 mtspr SPRN_IBAT4U,r20
>> 1518 mtspr SPRN_IBAT4L,r20
>> 1519 mtspr SPRN_IBAT5U,r20
>> 1520 mtspr SPRN_IBAT5L,r20
>> 1521 mtspr SPRN_IBAT6U,r20
>> 1522 mtspr SPRN_IBAT6L,r20
>> 1523 mtspr SPRN_IBAT7U,r20
>> 1524 mtspr SPRN_IBAT7L,r20
>> 1525 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
>> 1526 blr
>> 1527
>> 1528 flush_tlbs:
>> 1529 lis r10, 0x40
>> 1530 1: addic. r10, r10, -0x1000
>> 1531 tlbie r10
>> 1532 blt 1b
>> 1533 sync
>> 1534 blr
>> 1535
>> 1536 mmu_off:
>> 1537 addi r4, r3, __after_mmu_off - _start
>> 1538 mfmsr r3
>> 1539 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
>> 1540 beqlr
>> 1541 andc r3,r3,r0
>> 1542 mtspr SRR0,r4
>> 1543 mtspr SRR1,r3
>> 1544 sync
>> 1545 RFI
>> 1546
>> 1547 #ifndef CONFIG_POWER4
>> 1548 /*
>> 1549 * Use the first pair of BAT registers to map the 1st 16MB
>> 1550 * of RAM to KERNELBASE. From this point on we can't safely
>> 1551 * call OF any more.
>> 1552 */
>> 1553 initial_bats:
>> 1554 lis r11,KERNELBASE@h
>> 1555 #ifndef CONFIG_PPC64BRIDGE
>> 1556 mfspr r9,PVR
>> 1557 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
>> 1558 cmpi 0,r9,1
>> 1559 bne 4f
>> 1560 ori r11,r11,4 /* set up BAT registers for 601 */
>> 1561 li r8,0x7f /* valid, block length = 8MB */
>> 1562 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
>> 1563 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
>> 1564 mtspr IBAT0U,r11 /* N.B. 601 has valid bit in */
>> 1565 mtspr IBAT0L,r8 /* lower BAT register */
>> 1566 mtspr IBAT1U,r9
>> 1567 mtspr IBAT1L,r10
>> 1568 isync
>> 1569 blr
>> 1570 #endif /* CONFIG_PPC64BRIDGE */
367 1571
368 /********************************************* !! 1572 4: tophys(r8,r11)
369 * smp_slave_stext is executed by all non-monar !! 1573 #ifdef CONFIG_SMP
370 * pokes the slave CPUs in smp.c:smp_boot_cpus( !! 1574 ori r8,r8,0x12 /* R/W access, M=1 */
371 * !! 1575 #else
372 * Once here, registers values are initialized !! 1576 ori r8,r8,2 /* R/W access */
373 * mode. Once all available/eligible CPUs are i !! 1577 #endif /* CONFIG_SMP */
374 * released and start out by executing their ow !! 1578 #ifdef CONFIG_APUS
375 ********************************************** !! 1579 ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
376 smp_slave_stext: !! 1580 #else
377 .proc !! 1581 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
378 .callinfo !! 1582 #endif /* CONFIG_APUS */
379 1583
380 /* !! 1584 #ifdef CONFIG_PPC64BRIDGE
381 ** Initialize Space registers !! 1585 /* clear out the high 32 bits in the BAT */
382 */ !! 1586 clrldi r11,r11,32
383 mtsp %r0,%sr4 !! 1587 clrldi r8,r8,32
384 mtsp %r0,%sr5 !! 1588 #endif /* CONFIG_PPC64BRIDGE */
385 mtsp %r0,%sr6 !! 1589 mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
386 mtsp %r0,%sr7 !! 1590 mtspr DBAT0U,r11 /* bit in upper BAT register */
>> 1591 mtspr IBAT0L,r8
>> 1592 mtspr IBAT0U,r11
>> 1593 isync
>> 1594 blr
387 1595
388 #ifdef CONFIG_64BIT !! 1596 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
>> 1597 setup_disp_bat:
389 /* 1598 /*
390 * Enable Wide mode early, in case th !! 1599 * setup the display bat prepared for us in prom.c
391 * task in smp_init_current_idle_task <<
392 */ 1600 */
393 1: mfia %rp /* cle !! 1601 mflr r8
394 ldo 2f-1b(%rp),%rp !! 1602 bl reloc_offset
395 depdi 0,31,32,%rp !! 1603 mtlr r8
396 bv (%rp) !! 1604 addis r8,r3,disp_BAT@ha
397 ssm PSW_SM_W,%r0 !! 1605 addi r8,r8,disp_BAT@l
398 2: !! 1606 lwz r11,0(r8)
399 #endif !! 1607 lwz r8,4(r8)
>> 1608 mfspr r9,PVR
>> 1609 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
>> 1610 cmpi 0,r9,1
>> 1611 beq 1f
>> 1612 mtspr DBAT3L,r8
>> 1613 mtspr DBAT3U,r11
>> 1614 blr
>> 1615 1: mtspr IBAT3L,r8
>> 1616 mtspr IBAT3U,r11
>> 1617 blr
>> 1618
>> 1619 #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
>> 1620
>> 1621 #else /* CONFIG_POWER4 */
>> 1622 /*
>> 1623 * Load up the SDR1 and segment register values now
>> 1624 * since we don't have the BATs.
>> 1625 * Also make sure we are running in 32-bit mode.
>> 1626 */
400 1627
401 /* Initialize the SP - monarch sets u !! 1628 initial_mm_power4:
402 load32 PA(smp_init_current_id !! 1629 addis r14,r3,_SDR1@ha /* get the value from _SDR1 */
403 LDREG 0(%r6),%r6 !! 1630 lwz r14,_SDR1@l(r14) /* assume hash table below 4GB */
404 mtctl %r6,%cr30 !! 1631 mtspr SDR1,r14
405 tophys_r1 %r6 !! 1632 slbia
406 LDREG TASK_STACK(%r6),%sp !! 1633 lis r4,0x2000 /* set pseudo-segment reg 12 */
407 tophys_r1 %sp !! 1634 ori r5,r4,0x0ccc
408 ldo FRAME_SIZE(%sp),%sp !! 1635 mtsr 12,r5
409 !! 1636 ori r5,r4,0x0888 /* set pseudo-segment reg 8 */
410 /* point CPU to kernel page tables */ !! 1637 mtsr 8,r5 /* (for access to serial port) */
411 load32 PA(swapper_pg_dir),%r4 !! 1638 ori r5,r4,0x0999 /* set pseudo-segment reg 8 */
412 mtctl %r4,%cr24 /* Ini !! 1639 mtsr 9,r5 /* (for access to screen) */
413 mtctl %r4,%cr25 /* Ini !! 1640 mfmsr r0
414 !! 1641 clrldi r0,r0,1
415 #ifdef CONFIG_64BIT !! 1642 sync
416 /* Setup PDCE_PROC entry */ !! 1643 mtmsr r0
417 copy %arg0,%r3 !! 1644 isync
418 #else !! 1645 blr
419 /* Load RFI *return* address in case s <<
420 load32 smp_callin_rtn,%r2 <<
421 #endif <<
422 <<
423 /* Load RFI target address. */ <<
424 load32 smp_callin,%r11 <<
425 <<
426 /* ok...common code can handle the res <<
427 b common_stext <<
428 nop <<
429 1646
430 .procend !! 1647 /*
431 #endif /* CONFIG_SMP */ !! 1648 * On 970 (G5), we pre-set a few bits in HID0 & HID1
>> 1649 */
>> 1650 ppc970_setup_hid:
>> 1651 li r0,0
>> 1652 sync
>> 1653 mtspr 0x3f4,r0
>> 1654 isync
>> 1655 sync
>> 1656 mtspr 0x3f6,r0
>> 1657 isync
>> 1658 mfspr r0,SPRN_HID0
>> 1659 li r11,1 /* clear DOZE, NAP and SLEEP */
>> 1660 rldimi r0,r11,52,8 /* set DPM */
>> 1661 mtspr SPRN_HID0,r0
>> 1662 mfspr r0,SPRN_HID0
>> 1663 mfspr r0,SPRN_HID0
>> 1664 mfspr r0,SPRN_HID0
>> 1665 mfspr r0,SPRN_HID0
>> 1666 mfspr r0,SPRN_HID0
>> 1667 mfspr r0,SPRN_HID0
>> 1668 sync
>> 1669 isync
>> 1670 mfspr r0,SPRN_HID1
>> 1671 li r11,0x1200 /* enable i-fetch cacheability */
>> 1672 sldi r11,r11,44 /* and prefetch */
>> 1673 or r0,r0,r11
>> 1674 mtspr SPRN_HID1,r0
>> 1675 mtspr SPRN_HID1,r0
>> 1676 isync
>> 1677 li r0,0
>> 1678 sync
>> 1679 mtspr 0x137,0
>> 1680 isync
>> 1681 blr
>> 1682 #endif /* CONFIG_POWER4 */
>> 1683
>> 1684 #ifdef CONFIG_8260
>> 1685 /* Jump into the system reset for the rom.
>> 1686 * We first disable the MMU, and then jump to the ROM reset address.
>> 1687 *
>> 1688 * r3 is the board info structure, r4 is the location for starting.
>> 1689 * I use this for building a small kernel that can load other kernels,
>> 1690 * rather than trying to write or rely on a rom monitor that can tftp load.
>> 1691 */
>> 1692 .globl m8260_gorom
>> 1693 m8260_gorom:
>> 1694 mfmsr r0
>> 1695 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
>> 1696 sync
>> 1697 mtmsr r0
>> 1698 sync
>> 1699 mfspr r11, HID0
>> 1700 lis r10, 0
>> 1701 ori r10,r10,HID0_ICE|HID0_DCE
>> 1702 andc r11, r11, r10
>> 1703 mtspr HID0, r11
>> 1704 isync
>> 1705 li r5, MSR_
>> 1706 lis r6,2f@h
>> 1707 addis r6,r6,-KERNELBASE@h
>> 1708 ori r6,r6,2f@l
>> 1709 mtspr SRR0,r6
>> 1710 mtspr SRR1,r5
>> 1711 isync
>> 1712 sync
>> 1713 rfi
>> 1714 2:
>> 1715 mtlr r4
>> 1716 blr
>> 1717 #endif
432 1718
433 #ifndef CONFIG_64BIT <<
434 .section .data..ro_after_init <<
435 1719
436 .align 4 !! 1720 /*
437 .export $global$,data !! 1721 * We put a few things here that have to be page-aligned.
>> 1722 * This stuff goes at the beginning of the data segment,
>> 1723 * which is page-aligned.
>> 1724 */
>> 1725 .data
>> 1726 .globl sdata
>> 1727 sdata:
>> 1728 .globl empty_zero_page
>> 1729 empty_zero_page:
>> 1730 .space 4096
>> 1731
>> 1732 .globl swapper_pg_dir
>> 1733 swapper_pg_dir:
>> 1734 .space 4096
>> 1735
>> 1736 /*
>> 1737 * This space gets a copy of optional info passed to us by the bootstrap
>> 1738 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
>> 1739 */
>> 1740 .globl cmd_line
>> 1741 cmd_line:
>> 1742 .space 512
>> 1743
>> 1744 .globl intercept_table
>> 1745 intercept_table:
>> 1746 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
>> 1747 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
>> 1748 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
>> 1749 .long 0, 0, 0, 0, 0, 0, 0, 0
>> 1750 .long 0, 0, 0, 0, 0, 0, 0, 0
>> 1751 .long 0, 0, 0, 0, 0, 0, 0, 0
438 1752
439 .type $global$,@object !! 1753 /* Room for two PTE pointers, usually the kernel and current user pointers
440 .size $global$,4 !! 1754 * to their respective root page table.
441 $global$: !! 1755 */
442 .word 0 !! 1756 abatron_pteptrs:
443 #endif /*!CONFIG_64BIT*/ !! 1757 .space 8
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.