1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Signal trampolines for 64 bit processes.
4 *
5 * Copyright (C) 2006 Randolph Chung <tausq@deb
6 * Copyright (C) 2018-2022 Helge Deller <deller
7 * Copyright (C) 2022 John David Anglin <dave.a
8 */
9 #include <asm/unistd.h>
10 #include <linux/linkage.h>
11 #include <generated/asm-offsets.h>
12
13 .text
14
15 /* Gdb expects the trampoline is on the stack
16 a 64-byte boundary by 0, 4 or 5 instruction
17 is not on the stack, we need a new variant
18 data to tell gdb where to find the signal c
19
20 Here we put the offset to the context data
21 region and offset the first trampoline by 2
22 not change the trampoline as the code in gd
23 instruction sequence exactly.
24 */
25 .align 64
26 .word SIGFRAME_CONTEXT_REGS
27
28 /* The nop here is a hack. The dwarf2 unwind r
29 the return address to get an address in the
30 call instruction. Since we don't have a cal
31 extend the range covered by the unwind info
32 the real start.
33 */
34 nop
35
36 .globl __kernel_sigtramp_rt
37 .type __kernel_sigtramp_rt, @function
38 __kernel_sigtramp_rt:
39 .proc
40 .callinfo FRAME=ASM_SIGFRAME_SIZE,CALL
41 .entry
42
43 .Lsigrt_start = . - 4
44 0: ldi 0, %r25 /* (in
45 ldi __NR_rt_sigreturn, %r20
46 ble 0x100(%sr2, %r0)
47 nop
48
49 1: ldi 1, %r25 /* (in
50 ldi __NR_rt_sigreturn, %r20
51 ble 0x100(%sr2, %r0)
52 nop
53 .Lsigrt_end:
54 .exit
55 .procend
56 .size __kernel_sigtramp_rt,.-__kernel_
57
58 .section .eh_frame,"a",@progbits
59
60 /* This is where the mcontext_t struct can be
61 #define PTREGS SIGFRAME_CONTEXT_REGS /* 64-
62
63 /* Register REGNO can be found at offset OFS o
64 .macro rsave regno,ofs
65 .byte 0x05 /* DW_CFA_offs
66 .uleb128 \regno; /* regno */
67 .uleb128 \ofs /* factored
68 .endm
69
70 .Lcie:
71 .long .Lcie_end - .Lcie_start
72 .Lcie_start:
73 .long 0 /* CIE ID */
74 .byte 1 /* Version num
75 .stringz "zRS" /* NUL-termina
76 .uleb128 4 /* Code alignm
77 .sleb128 8 /* Data alignm
78 .byte 61 /* Return addr
79 .uleb128 1 /* Augmentatio
80 .byte 0x1b /* DW_EH_PE_pc
81 .byte 0x0f /* DW_CFA_def_
82 .uleb128 9f - 1f /* length */
83 1:
84 .byte 0x8e /* DW_OP_bre
85 .sleb128 PTREGS
86 9:
87 .balign 8
88 .Lcie_end:
89
90 .long .Lfde0_end - .Lfde0_start
91 .Lfde0_start:
92 .long .Lfde0_start - .Lcie /* CIE
93 .long .Lsigrt_start - . /* PC
94 .long .Lsigrt_end - .Lsigrt_start
95 .uleb128 0 /* Aug
96
97 /* General registers */
98 rsave 1, 2
99 rsave 2, 3
100 rsave 3, 4
101 rsave 4, 5
102 rsave 5, 6
103 rsave 6, 7
104 rsave 7, 8
105 rsave 8, 9
106 rsave 9, 10
107 rsave 10, 11
108 rsave 11, 12
109 rsave 12, 13
110 rsave 13, 14
111 rsave 14, 15
112 rsave 15, 16
113 rsave 16, 17
114 rsave 17, 18
115 rsave 18, 19
116 rsave 19, 20
117 rsave 20, 21
118 rsave 21, 22
119 rsave 22, 23
120 rsave 23, 24
121 rsave 24, 25
122 rsave 25, 26
123 rsave 26, 27
124 rsave 27, 28
125 rsave 28, 29
126 rsave 29, 30
127 rsave 30, 31
128 rsave 31, 32
129
130 /* Floating-point registers */
131 rsave 32, 36
132 rsave 33, 37
133 rsave 34, 38
134 rsave 35, 39
135 rsave 36, 40
136 rsave 37, 41
137 rsave 38, 42
138 rsave 39, 43
139 rsave 40, 44
140 rsave 41, 45
141 rsave 42, 46
142 rsave 43, 47
143 rsave 44, 48
144 rsave 45, 49
145 rsave 46, 50
146 rsave 47, 51
147 rsave 48, 52
148 rsave 49, 53
149 rsave 50, 54
150 rsave 51, 55
151 rsave 52, 56
152 rsave 53, 57
153 rsave 54, 58
154 rsave 55, 59
155 rsave 56, 60
156 rsave 57, 61
157 rsave 58, 62
158 rsave 59, 63
159
160 /* SAR register */
161 rsave 60, 67
162
163 /* iaoq[0] return address register */
164 rsave 61, 65
165 .balign 8
166 .Lfde0_end:
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