1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 #ifndef _PPC_BOOT_DCR_H_
3 #define _PPC_BOOT_DCR_H_
4
5 #define mfdcr(rn) \
6 ({ \
7 unsigned long rval; \
8 asm volatile("mfdcr %0,%1" : "
9 rval; \
10 })
11 #define mtdcr(rn, val) \
12 asm volatile("mtdcr %0,%1" : : "i"(rn)
13 #define mfdcrx(rn) \
14 ({ \
15 unsigned long rval; \
16 asm volatile("mfdcrx %0,%1" :
17 rval; \
18 })
19 #define mtdcrx(rn, val) \
20 ({ \
21 asm volatile("mtdcrx %0,%1" :
22 })
23
24 /* 440GP/440GX SDRAM controller DCRs */
25 #define DCRN_SDRAM0_CFGADDR
26 #define DCRN_SDRAM0_CFGDATA
27
28 #define SDRAM0_READ(offset) ({\
29 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
30 mfdcr(DCRN_SDRAM0_CFGDATA); })
31 #define SDRAM0_WRITE(offset, data) ({\
32 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
33 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
34
35 #define SDRAM0_B0CR
36 #define SDRAM0_B1CR
37 #define SDRAM0_B2CR
38 #define SDRAM0_B3CR
39
40 static const unsigned long sdram_bxcr[] = { SD
41 SD
42
43 #define SDRAM_CONFIG_BANK_ENAB
44 #define SDRAM_CONFIG_SIZE_MASK
45 #define SDRAM_CONFIG_BANK_SIZE
46 (0x00400000 << ((reg & SDRAM_CONFIG_SI
47
48 /* 440GP External Bus Controller (EBC) */
49 #define DCRN_EBC0_CFGADDR
50 #define DCRN_EBC0_CFGDATA
51 #define EBC_NUM_BANKS
52 #define EBC_B0CR
53 #define EBC_B1CR
54 #define EBC_B2CR
55 #define EBC_B3CR
56 #define EBC_B4CR
57 #define EBC_B5CR
58 #define EBC_B6CR
59 #define EBC_B7CR
60 #define EBC_BXCR(n)
61 #define EBC_BXCR_BAS
62 #define EBC_BXCR_BS
63 #define EBC_BXCR_BANK_SIZE(reg) \
64 (0x100000 << (((reg) & EBC_BXCR_BS) >>
65 #define EBC_BXCR_BU
66 #define EBC_BXCR_BU_OFF
67 #define EBC_BXCR_BU_RO
68 #define EBC_BXCR_BU_WO
69 #define EBC_BXCR_BU_RW
70 #define EBC_BXCR_BW
71 #define EBC_B0AP
72 #define EBC_B1AP
73 #define EBC_B2AP
74 #define EBC_B3AP
75 #define EBC_B4AP
76 #define EBC_B5AP
77 #define EBC_B6AP
78 #define EBC_B7AP
79 #define EBC_BXAP(n)
80 #define EBC_BEAR
81 #define EBC_BESR
82 #define EBC_CFG
83 #define EBC_CID
84
85 /* 440GP Clock, PM, chip control */
86 #define DCRN_CPC0_SR
87 #define DCRN_CPC0_ER
88 #define DCRN_CPC0_FR
89 #define DCRN_CPC0_SYS0
90 #define CPC0_SYS0_TUNE
91 #define CPC0_SYS0_FBDV_MASK
92 #define CPC0_SYS0_FWDVA_MASK
93 #define CPC0_SYS0_FWDVB_MASK
94 #define CPC0_SYS0_OPDV_MASK
95 #define CPC0_SYS0_EPDV_MASK
96 /* Helper macros to compute the actual clock d
97 * encodings in the CPC0 register */
98 #define CPC0_SYS0_FBDV(reg) \
99 ((((((reg) & CPC0_SYS0_FBDV_MA
100 #define CPC0_SYS0_FWDVA(reg) \
101 (8 - (((reg) & CPC0_SYS0_FWDVA
102 #define CPC0_SYS0_FWDVB(reg) \
103 (8 - (((reg) & CPC0_SYS0_FWDVB
104 #define CPC0_SYS0_OPDV(reg) \
105 ((((reg) & CPC0_SYS0_OPDV_MASK
106 #define CPC0_SYS0_EPDV(reg) \
107 ((((reg) & CPC0_SYS0_EPDV_MASK
108 #define CPC0_SYS0_EXTSL
109 #define CPC0_SYS0_RW_MASK
110 #define CPC0_SYS0_RL
111 #define CPC0_SYS0_ZMIISL_MASK
112 #define CPC0_SYS0_BYPASS
113 #define CPC0_SYS0_NTO1
114 #define DCRN_CPC0_SYS1
115 #define DCRN_CPC0_CUST0
116 #define DCRN_CPC0_CUST1
117 #define DCRN_CPC0_STRP0
118 #define DCRN_CPC0_STRP1
119 #define DCRN_CPC0_STRP2
120 #define DCRN_CPC0_STRP3
121 #define DCRN_CPC0_GPIO
122 #define DCRN_CPC0_PLB
123 #define DCRN_CPC0_CR1
124 #define DCRN_CPC0_CR0
125 #define CPC0_CR0_SWE
126 #define CPC0_CR0_CETE
127 #define CPC0_CR0_U1FCS
128 #define CPC0_CR0_U0DTE
129 #define CPC0_CR0_U0DRE
130 #define CPC0_CR0_U0DC
131 #define CPC0_CR0_U1DTE
132 #define CPC0_CR0_U1DRE
133 #define CPC0_CR0_U1DC
134 #define CPC0_CR0_U0EC
135 #define CPC0_CR0_U1EC
136 #define CPC0_CR0_UDIV_MASK
137 #define CPC0_CR0_UDIV(reg) \
138 ((((reg) & CPC0_CR0_UDIV_MASK)
139 #define DCRN_CPC0_MIRQ0
140 #define DCRN_CPC0_MIRQ1
141 #define DCRN_CPC0_JTAGID
142
143 #define DCRN_MAL0_CFG
144 #define MAL_RESET 0x80000000
145
146 /* 440EP Clock/Power-on Reset regs */
147 #define DCRN_CPR0_ADDR 0xc
148 #define DCRN_CPR0_DATA 0xd
149 #define CPR0_PLLD0 0x60
150 #define CPR0_OPBD0 0xc0
151 #define CPR0_PERD0 0xe0
152 #define CPR0_PRIMBD0 0xa0
153 #define CPR0_SCPID 0x120
154 #define CPR0_PLLC0 0x40
155
156 /* 440GX/405EX Clock Control reg */
157 #define DCRN_CPR0_CLKUPD
158 #define DCRN_CPR0_PLLC
159 #define DCRN_CPR0_PLLD
160 #define DCRN_CPR0_PRIMAD
161 #define DCRN_CPR0_PRIMBD
162 #define DCRN_CPR0_OPBD
163 #define DCRN_CPR0_PERD
164 #define DCRN_CPR0_MALD
165
166 #define DCRN_SDR0_CONFIG_ADDR 0xe
167 #define DCRN_SDR0_CONFIG_DATA 0xf
168
169 /* SDR read/write helper macros */
170 #define SDR0_READ(offset) ({\
171 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset);
172 mfdcr(DCRN_SDR0_CONFIG_DATA); })
173 #define SDR0_WRITE(offset, data) ({\
174 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset);
175 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
176
177 #define DCRN_SDR0_UART0 0x0120
178 #define DCRN_SDR0_UART1 0x0121
179 #define DCRN_SDR0_UART2 0x0122
180 #define DCRN_SDR0_UART3 0x0123
181
182
183 /* CPRs read/write helper macros - based off i
184
185 #define DCRN_CPR0_CFGADDR
186 #define DCRN_CPR0_CFGDATA
187
188 #define CPR0_READ(offset) ({\
189 mtdcr(DCRN_CPR0_CFGADDR, offset); \
190 mfdcr(DCRN_CPR0_CFGDATA); })
191 #define CPR0_WRITE(offset, data) ({\
192 mtdcr(DCRN_CPR0_CFGADDR, offset); \
193 mtdcr(DCRN_CPR0_CFGDATA, data); })
194
195
196
197 #endif /* _PPC_BOOT_DCR_H_ */
198
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