1 /*
2 * Device Tree Source for IBM Embedded PPC 476
3 *
4 * Copyright © 2013 Tony Breeds IBM Corporati
5 * Copyright © 2013 Alistair Popple IBM Corpo
6 *
7 * This file is licensed under the terms of th
8 * License version 2. This program is license
9 * any warranty of any kind, whether express o
10 */
11
12 /dts-v1/;
13
14 /memreserve/ 0x01f00000 0x00100000; // spi
15
16 / {
17 #address-cells = <2>;
18 #size-cells = <2>;
19 model = "ibm,akebono";
20 compatible = "ibm,akebono", "ibm,476gt
21 dcr-parent = <&{/cpus/cpu@0}>;
22
23 aliases {
24 serial0 = &UART0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,476";
34 reg = <0>;
35 clock-frequency = <160
36 timebase-frequency = <
37 i-cache-line-size = <3
38 d-cache-line-size = <3
39 i-cache-size = <32768>
40 d-cache-size = <32768>
41 dcr-controller;
42 dcr-access-method = "n
43 status = "okay";
44 };
45 cpu@1 {
46 device_type = "cpu";
47 model = "PowerPC,476";
48 reg = <1>;
49 clock-frequency = <160
50 timebase-frequency = <
51 i-cache-line-size = <3
52 d-cache-line-size = <3
53 i-cache-size = <32768>
54 d-cache-size = <32768>
55 dcr-controller;
56 dcr-access-method = "n
57 status = "disabled";
58 enable-method = "spin-
59 cpu-release-addr = <0x
60 };
61 };
62
63 memory {
64 device_type = "memory";
65 reg = <0x0 0x0 0x0 0x0>; // fi
66 };
67
68 MPIC: interrupt-controller {
69 compatible = "chrp,open-pic";
70 interrupt-controller;
71 dcr-reg = <0xffc00000 0x000400
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
75 single-cpu-affinity;
76 };
77
78 plb {
79 compatible = "ibm,plb6";
80 #address-cells = <2>;
81 #size-cells = <2>;
82 ranges;
83 clock-frequency = <200000000>;
84
85 HSTA0: hsta@310000e0000 {
86 compatible = "ibm,476g
87 reg = <0x310 0x000e000
88 interrupt-parent = <&M
89 interrupts = <108 0
90 109 0
91 110 0
92 111 0
93 112 0
94 113 0
95 114 0
96 115 0
97 116 0
98 117 0
99 118 0
100 119 0
101 120 0
102 121 0
103 122 0
104 123 0>;
105 };
106
107 MAL0: mcmal {
108 compatible = "ibm,mcma
109 dcr-reg = <0xc0000000
110 num-tx-chans = <1>;
111 num-rx-chans = <1>;
112 #address-cells = <0>;
113 #size-cells = <0>;
114 interrupt-parent = <&M
115 interrupts = < /*TXEO
116 /*RXEO
117 /*SERR
118 /*TXDE
119 /*RXDE
120 };
121
122 SATA0: sata@30000010000 {
123 compatible = "ibm,476g
124 reg = <0x300 0x0001000
125 interrupt-parent = <&M
126 interrupts = <93 2>;
127 };
128
129 EHCI0: usb@30010000000 {
130 compatible = "ibm,476g
131 reg = <0x300 0x1000000
132 interrupt-parent = <&M
133 interrupts = <85 2>;
134 };
135
136 SD0: sd@30000000000 {
137 compatible = "ibm,476g
138 reg = <0x300 0x0000000
139 interrupts = <91 2>;
140 interrupt-parent = <&M
141 };
142
143 OHCI0: usb@30010010000 {
144 compatible = "ibm,476g
145 reg = <0x300 0x1001000
146 interrupt-parent = <&M
147 interrupts = <89 1>;
148 };
149
150 OHCI1: usb@30010020000 {
151 compatible = "ibm,476g
152 reg = <0x300 0x1002000
153 interrupt-parent = <&M
154 interrupts = <88 1>;
155 };
156
157 POB0: opb {
158 compatible = "ibm,opb-
159 #address-cells = <1>;
160 #size-cells = <1>;
161 /* Wish there was a ni
162 * 32-bit range
163 */
164 ranges = <0x00000000 0
165 0x80000000 0
166 clock-frequency = <100
167
168 RGMII0: emac-rgmii-wol
169 compatible = "
170 reg = <0x50004
171 has-mdio;
172 };
173
174 EMAC0: ethernet@30000
175 device_type =
176 compatible = "
177 interrupt-pare
178 interrupts = <
179 #interrupt-cel
180 #address-cells
181 #size-cells =
182 interrupt-map
183
184 reg = <0x30000
185
186 /* local-mac-a
187 * the wrapper
188 * passing dat
189 * local-mac-a
190 * to set it m
191 //local-mac-ad
192
193 mal-device = <
194 mal-tx-channel
195 mal-rx-channel
196 cell-index = <
197 max-frame-size
198 rx-fifo-size =
199 tx-fifo-size =
200 rx-fifo-size-g
201 phy-mode = "rg
202 phy-map = <0x0
203 rgmii-wol-devi
204 has-inverted-s
205 has-new-stacr-
206 };
207
208 UART0: serial@10000 {
209 device_type =
210 compatible = "
211 reg = <0x10000
212 virtual-reg =
213 clock-frequenc
214 current-speed
215 interrupt-pare
216 interrupts = <
217 };
218
219 IIC0: i2c@0 {
220 compatible = "
221 reg = <0x0 0x0
222 interrupt-pare
223 interrupts = <
224 #address-cells
225 #size-cells =
226 rtc@68 {
227 compat
228 reg =
229 };
230 };
231
232 IIC1: i2c@100 {
233 compatible = "
234 reg = <0x100 0
235 interrupt-pare
236 interrupts = <
237 #address-cells
238 #size-cells =
239 avr@58 {
240 compat
241 reg =
242 };
243 };
244
245 FPGA0: fpga@ebc00000 {
246 compatible = "
247 reg = <0xebc00
248 };
249 };
250
251 PCIE0: pcie@10100000000 {
252 device_type = "pci";
253 #interrupt-cells = <1>
254 #size-cells = <2>;
255 #address-cells = <3>;
256 compatible = "ibm,plb-
257 primary;
258 port = <0x0>; /* port
259 reg = <0x00000101 0x00
260 0x00000100 0x00
261 dcr-reg = <0xc0 0x20>;
262
263 // pci_space <
264 ranges = <0x02000000 0
265 0x01000000 0
266
267 /* Inbound starting at
268 * PCI devices must be
269 */
270 dma-ranges = <0x420000
271
272 /* This drives busses
273 bus-range = <0x0 0xf>;
274
275 /* Legacy interrupts (
276 * to invert PCIe lega
277 * We are de-swizzling
278 * port of the root co
279 * to avoid putting a
280 * below are basically
281 * The real slot is on
282 */
283 interrupt-map-mask = <
284 interrupt-map = <
285 0x0 0x0 0x0 0x
286 0x0 0x0 0x0 0x
287 0x0 0x0 0x0 0x
288 0x0 0x0 0x0 0x
289 };
290
291 PCIE1: pcie@20100000000 {
292 device_type = "pci";
293 #interrupt-cells = <1>
294 #size-cells = <2>;
295 #address-cells = <3>;
296 compatible = "ibm,plb-
297 primary;
298 port = <0x1>; /* port
299 reg = <0x00000201 0x00
300 0x00000200 0x00
301 dcr-reg = <0x100 0x20>
302
303 // pci_space <
304 ranges = <0x02000000 0
305 0x01000000 0
306
307 /* Inbound starting at
308 * PCI devices must be
309 */
310 dma-ranges = <0x420000
311
312 /* This drives busses
313 bus-range = <0x0 0xf>;
314
315 /* Legacy interrupts (
316 * to invert PCIe lega
317 * We are de-swizzling
318 * port of the root co
319 * to avoid putting a
320 * below are basically
321 * The real slot is on
322 */
323 interrupt-map-mask = <
324 interrupt-map = <
325 0x0 0x0 0x0 0x
326 0x0 0x0 0x0 0x
327 0x0 0x0 0x0 0x
328 0x0 0x0 0x0 0x
329 };
330
331 PCIE2: pcie@18100000000 {
332 device_type = "pci";
333 #interrupt-cells = <1>
334 #size-cells = <2>;
335 #address-cells = <3>;
336 compatible = "ibm,plb-
337 primary;
338 port = <0x2>; /* port
339 reg = <0x00000181 0x00
340 0x00000180 0x00
341 dcr-reg = <0xe0 0x20>;
342
343 // pci_space <
344 ranges = <0x02000000 0
345 0x01000000 0
346
347 /* Inbound starting at
348 * PCI devices must be
349 */
350 dma-ranges = <0x420000
351
352 /* This drives busses
353 bus-range = <0x0 0xf>;
354
355 /* Legacy interrupts (
356 * to invert PCIe lega
357 * We are de-swizzling
358 * port of the root co
359 * to avoid putting a
360 * below are basically
361 * The real slot is on
362 */
363 interrupt-map-mask = <
364 interrupt-map = <
365 0x0 0x0 0x0 0x
366 0x0 0x0 0x0 0x
367 0x0 0x0 0x0 0x
368 0x0 0x0 0x0 0x
369 };
370
371 PCIE3: pcie@28100000000 {
372 device_type = "pci";
373 #interrupt-cells = <1>
374 #size-cells = <2>;
375 #address-cells = <3>;
376 compatible = "ibm,plb-
377 primary;
378 port = <0x3>; /* port
379 reg = <0x00000281 0x00
380 0x00000280 0x00
381 dcr-reg = <0x120 0x20>
382
383 // pci_space <
384 ranges = <0x02000000 0
385 0x01000000 0
386
387 /* Inbound starting at
388 * PCI devices must be
389 */
390 dma-ranges = <0x420000
391
392 /* This drives busses
393 bus-range = <0x0 0xf>;
394
395 /* Legacy interrupts (
396 * to invert PCIe lega
397 * We are de-swizzling
398 * port of the root co
399 * to avoid putting a
400 * below are basically
401 * The real slot is on
402 */
403 interrupt-map-mask = <
404 interrupt-map = <
405 0x0 0x0 0x0 0x
406 0x0 0x0 0x0 0x
407 0x0 0x0 0x0 0x
408 0x0 0x0 0x0 0x
409 };
410 };
411
412 chosen {
413 stdout-path = &UART0;
414 };
415 };
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