1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Device Tree Source for AMCC Arches (dual 46
4 *
5 * (C) Copyright 2008 Applied Micro Circuits C
6 * Victor Gallardo <vgallardo@amcc.com>
7 * Adam Graham <agraham@amcc.com>
8 *
9 * Based on the glacier.dts file
10 * Stefan Roese <sr@denx.de>
11 * Copyright 2008 DENX Software Engineering
12 *
13 * See file CREDITS for list of people who con
14 * project.
15 */
16
17 /dts-v1/;
18
19 / {
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "amcc,arches";
23 compatible = "amcc,arches";
24 dcr-parent = <&{/cpus/cpu@0}>;
25
26 aliases {
27 ethernet0 = &EMAC0;
28 ethernet1 = &EMAC1;
29 ethernet2 = &EMAC2;
30 serial0 = &UART0;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu@0 {
38 device_type = "cpu";
39 model = "PowerPC,460GT
40 reg = <0x00000000>;
41 clock-frequency = <0>;
42 timebase-frequency = <
43 i-cache-line-size = <3
44 d-cache-line-size = <3
45 i-cache-size = <32768>
46 d-cache-size = <32768>
47 dcr-controller;
48 dcr-access-method = "n
49 next-level-cache = <&L
50 };
51 };
52
53 memory {
54 device_type = "memory";
55 reg = <0x00000000 0x00000000 0
56 };
57
58 UIC0: interrupt-controller0 {
59 compatible = "ibm,uic-460gt","
60 interrupt-controller;
61 cell-index = <0>;
62 dcr-reg = <0x0c0 0x009>;
63 #address-cells = <0>;
64 #size-cells = <0>;
65 #interrupt-cells = <2>;
66 };
67
68 UIC1: interrupt-controller1 {
69 compatible = "ibm,uic-460gt","
70 interrupt-controller;
71 cell-index = <1>;
72 dcr-reg = <0x0d0 0x009>;
73 #address-cells = <0>;
74 #size-cells = <0>;
75 #interrupt-cells = <2>;
76 interrupts = <0x1e 0x4 0x1f 0x
77 interrupt-parent = <&UIC0>;
78 };
79
80 UIC2: interrupt-controller2 {
81 compatible = "ibm,uic-460gt","
82 interrupt-controller;
83 cell-index = <2>;
84 dcr-reg = <0x0e0 0x009>;
85 #address-cells = <0>;
86 #size-cells = <0>;
87 #interrupt-cells = <2>;
88 interrupts = <0xa 0x4 0xb 0x4>
89 interrupt-parent = <&UIC0>;
90 };
91
92 UIC3: interrupt-controller3 {
93 compatible = "ibm,uic-460gt","
94 interrupt-controller;
95 cell-index = <3>;
96 dcr-reg = <0x0f0 0x009>;
97 #address-cells = <0>;
98 #size-cells = <0>;
99 #interrupt-cells = <2>;
100 interrupts = <0x10 0x4 0x11 0x
101 interrupt-parent = <&UIC0>;
102 };
103
104 SDR0: sdr {
105 compatible = "ibm,sdr-460gt";
106 dcr-reg = <0x00e 0x002>;
107 };
108
109 CPR0: cpr {
110 compatible = "ibm,cpr-460gt";
111 dcr-reg = <0x00c 0x002>;
112 };
113
114 L2C0: l2c {
115 compatible = "ibm,l2-cache-460
116 dcr-reg = <0x020 0x008
117 0x030 0x008>;
118 cache-line-size = <32>;
119 cache-size = <262144>;
120 interrupt-parent = <&UIC1>;
121 interrupts = <11 1>;
122 };
123
124 plb {
125 compatible = "ibm,plb-460gt",
126 #address-cells = <2>;
127 #size-cells = <1>;
128 ranges;
129 clock-frequency = <0>; /* Fill
130
131 SDRAM0: sdram {
132 compatible = "ibm,sdra
133 dcr-reg = <0x010 0x002
134 };
135
136 CRYPTO: crypto@180000 {
137 compatible = "amcc,ppc
138 reg = <4 0x00180000 0x
139 interrupt-parent = <&U
140 interrupts = <0x1d 0x4
141 };
142
143 MAL0: mcmal {
144 compatible = "ibm,mcma
145 dcr-reg = <0x180 0x062
146 num-tx-chans = <3>;
147 num-rx-chans = <24>;
148 #address-cells = <0>;
149 #size-cells = <0>;
150 interrupt-parent = <&U
151 interrupts = < /*TXEO
152 /*RXEO
153 /*SERR
154 /*TXDE
155 /*RXDE
156 desc-base-addr-high =
157 };
158
159 POB0: opb {
160 compatible = "ibm,opb-
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges = <0xb0000000 0
164 clock-frequency = <0>;
165
166 EBC0: ebc {
167 compatible = "
168 dcr-reg = <0x0
169 #address-cells
170 #size-cells =
171 clock-frequenc
172 /* ranges prop
173 interrupts = <
174 interrupt-pare
175
176 nor_flash@0,0
177 compat
178 bank-w
179 reg =
180 #addre
181 #size-
182 partit
183
184
185 };
186 partit
187
188
189 };
190 partit
191
192
193 };
194 partit
195
196
197 };
198 partit
199
200
201 };
202 partit
203
204
205 };
206 };
207 };
208
209 UART0: serial@ef600300
210 device_type =
211 compatible = "
212 reg = <0xef600
213 virtual-reg =
214 clock-frequenc
215 current-speed
216 interrupt-pare
217 interrupts = <
218 };
219
220 IIC0: i2c@ef600700 {
221 compatible = "
222 reg = <0xef600
223 interrupt-pare
224 interrupts = <
225 #address-cells
226 #size-cells =
227 sttm@4a {
228 compat
229 reg =
230 interr
231 interr
232 };
233 };
234
235 IIC1: i2c@ef600800 {
236 compatible = "
237 reg = <0xef600
238 interrupt-pare
239 interrupts = <
240 };
241
242 TAH0: emac-tah@ef60135
243 compatible = "
244 reg = <0xef601
245 };
246
247 TAH1: emac-tah@ef60145
248 compatible = "
249 reg = <0xef601
250 };
251
252 EMAC0: ethernet@ef600e
253 device_type =
254 compatible = "
255 interrupt-pare
256 interrupts = <
257 #interrupt-cel
258 #address-cells
259 #size-cells =
260 interrupt-map
261
262 reg = <0xef600
263 local-mac-addr
264 mal-device = <
265 mal-tx-channel
266 mal-rx-channel
267 cell-index = <
268 max-frame-size
269 rx-fifo-size =
270 tx-fifo-size =
271 rx-fifo-size-g
272 phy-mode = "sg
273 phy-map = <0xf
274 gpcs-address =
275 tah-device = <
276 tah-channel =
277 has-inverted-s
278 has-new-stacr-
279 };
280
281 EMAC1: ethernet@ef600f
282 device_type =
283 compatible = "
284 interrupt-pare
285 interrupts = <
286 #interrupt-cel
287 #address-cells
288 #size-cells =
289 interrupt-map
290
291 reg = <0xef600
292 local-mac-addr
293 mal-device = <
294 mal-tx-channel
295 mal-rx-channel
296 cell-index = <
297 max-frame-size
298 rx-fifo-size =
299 tx-fifo-size =
300 rx-fifo-size-g
301 phy-mode = "sg
302 phy-map = <0x0
303 gpcs-address =
304 tah-device = <
305 tah-channel =
306 has-inverted-s
307 has-new-stacr-
308 mdio-device =
309 };
310
311 EMAC2: ethernet@ef6011
312 device_type =
313 compatible = "
314 interrupt-pare
315 interrupts = <
316 #interrupt-cel
317 #address-cells
318 #size-cells =
319 interrupt-map
320
321 reg = <0xef601
322 local-mac-addr
323 mal-device = <
324 mal-tx-channel
325 mal-rx-channel
326 cell-index = <
327 max-frame-size
328 rx-fifo-size =
329 tx-fifo-size =
330 rx-fifo-size-g
331 tx-fifo-size-g
332 phy-mode = "sg
333 phy-map = <0x0
334 gpcs-address =
335 has-inverted-s
336 has-new-stacr-
337 mdio-device =
338 };
339 };
340 };
341 };
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