1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Device Tree for Bluestone (APM821xx) board.
4 *
5 * Copyright (c) 2010, Applied Micro Circuits
6 * Author: Tirumala R Marri <tmarri@apm.com>
7 */
8
9 /dts-v1/;
10
11 / {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "apm,bluestone";
15 compatible = "apm,bluestone";
16 dcr-parent = <&{/cpus/cpu@0}>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 serial0 = &UART0;
21 serial1 = &UART1;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 model = "PowerPC,apm82
31 reg = <0x00000000>;
32 clock-frequency = <0>;
33 timebase-frequency = <
34 i-cache-line-size = <3
35 d-cache-line-size = <3
36 i-cache-size = <32768>
37 d-cache-size = <32768>
38 dcr-controller;
39 dcr-access-method = "n
40 next-level-cache = <&L
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x00000000 0
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <0x1e 0x4 0x1f 0x
68 interrupt-parent = <&UIC0>;
69 };
70
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
75 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 interrupts = <0xa 0x4 0xb 0x4>
80 interrupt-parent = <&UIC0>;
81 };
82
83 UIC3: interrupt-controller3 {
84 compatible = "ibm,uic";
85 interrupt-controller;
86 cell-index = <3>;
87 dcr-reg = <0x0f0 0x009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 #interrupt-cells = <2>;
91 interrupts = <0x10 0x4 0x11 0x
92 interrupt-parent = <&UIC0>;
93 };
94
95 OCM: ocm@400040000 {
96 compatible = "ibm,ocm";
97 status = "okay";
98 cell-index = <1>;
99 /* configured in U-Boot */
100 reg = <4 0x00040000 0x8000>; /
101 };
102
103 SDR0: sdr {
104 compatible = "ibm,sdr-apm821xx
105 dcr-reg = <0x00e 0x002>;
106 };
107
108 CPR0: cpr {
109 compatible = "ibm,cpr-apm821xx
110 dcr-reg = <0x00c 0x002>;
111 };
112
113 L2C0: l2c {
114 compatible = "ibm,l2-cache-apm
115 dcr-reg = <0x020 0x008
116 0x030 0x008>;
117 cache-line-size = <32>;
118 cache-size = <262144>;
119 interrupt-parent = <&UIC1>;
120 interrupts = <11 1>;
121 };
122
123 plb {
124 compatible = "ibm,plb4";
125 #address-cells = <2>;
126 #size-cells = <1>;
127 ranges;
128 clock-frequency = <0>; /* Fill
129
130 SDRAM0: sdram {
131 compatible = "ibm,sdra
132 dcr-reg = <0x010 0x002
133 };
134
135 MAL0: mcmal {
136 compatible = "ibm,mcma
137 descriptor-memory = "o
138 dcr-reg = <0x180 0x062
139 num-tx-chans = <1>;
140 num-rx-chans = <1>;
141 #address-cells = <0>;
142 #size-cells = <0>;
143 interrupt-parent = <&U
144 interrupts = < /*TXEO
145 /*RXEO
146 /*SERR
147 /*TXDE
148 /*RXDE
149 };
150
151 POB0: opb {
152 compatible = "ibm,opb"
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges = <0xb0000000 0
156 clock-frequency = <0>;
157
158 EBC0: ebc {
159 compatible = "
160 dcr-reg = <0x0
161 #address-cells
162 #size-cells =
163 clock-frequenc
164 /* ranges prop
165 ranges = < 0x0
166 interrupts = <
167 interrupt-pare
168
169 nor_flash@0,0
170 compat
171 bank-w
172 reg =
173 #addre
174 #size-
175 partit
176
177
178 };
179 partit
180
181
182 };
183 partit
184
185
186 };
187 };
188
189 ndfc@1,0 {
190 compat
191 reg =
192 ccr =
193 bank-s
194 #addre
195 #size-
196 /* 2Gb
197 nand {
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233 };
234 };
235 };
236
237 UART0: serial@ef600300
238 device_type =
239 compatible = "
240 reg = <0xef600
241 virtual-reg =
242 clock-frequenc
243 current-speed
244 interrupt-pare
245 interrupts = <
246 };
247
248 UART1: serial@ef600400
249 device_type =
250 compatible = "
251 reg = <0xef600
252 virtual-reg =
253 clock-frequenc
254 current-speed
255 interrupt-pare
256 interrupts = <
257 };
258
259 IIC0: i2c@ef600700 {
260 compatible = "
261 reg = <0xef600
262 interrupt-pare
263 interrupts = <
264 #address-cells
265 #size-cells =
266 rtc@68 {
267 compat
268 reg =
269 interr
270 interr
271 };
272 sttm@4C {
273 compat
274 reg =
275 interr
276 interr
277 };
278 };
279
280 IIC1: i2c@ef600800 {
281 compatible = "
282 reg = <0xef600
283 interrupt-pare
284 interrupts = <
285 };
286
287 RGMII0: emac-rgmii@ef6
288 compatible = "
289 reg = <0xef601
290 has-mdio;
291 };
292
293 TAH0: emac-tah@ef60135
294 compatible = "
295 reg = <0xef601
296 };
297
298 EMAC0: ethernet@ef600c
299 device_type =
300 compatible = "
301 interrupt-pare
302 interrupts = <
303 #interrupt-cel
304 #address-cells
305 #size-cells =
306 interrupt-map
307
308 reg = <0xef600
309 local-mac-addr
310 mal-device = <
311 mal-tx-channel
312 mal-rx-channel
313 cell-index = <
314 max-frame-size
315 rx-fifo-size =
316 tx-fifo-size =
317 phy-mode = "rg
318 phy-map = <0x0
319 rgmii-device =
320 rgmii-channel
321 tah-device = <
322 tah-channel =
323 has-inverted-s
324 has-new-stacr-
325 };
326 };
327
328 PCIE0: pcie@d00000000 {
329 device_type = "pci";
330 #interrupt-cells = <1>
331 #size-cells = <2>;
332 #address-cells = <3>;
333 compatible = "ibm,plb-
334 primary;
335 port = <0x0>; /* port
336 reg = <0x0000000d 0x00
337 0x0000000c 0x08
338 dcr-reg = <0x100 0x020
339 sdr-base = <0x300>;
340
341 /* Outbound ranges, on
342 * later cannot be cha
343 */
344 ranges = <0x02000000 0
345 0x02000000 0
346 0x01000000 0
347
348 /* Inbound 2GB range s
349 dma-ranges = <0x420000
350
351 /* This drives busses
352 bus-range = <0x40 0x7f
353
354 /* Legacy interrupts (
355 * to invert PCIe lega
356 * We are de-swizzling
357 * port of the root co
358 * to avoid putting a
359 * below are basically
360 * The real slot is on
361 */
362 interrupt-map-mask = <
363 interrupt-map = <
364 0x0 0x0 0x0 0x
365 0x0 0x0 0x0 0x
366 0x0 0x0 0x0 0x
367 0x0 0x0 0x0 0x
368 };
369 };
370 };
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