1 /*
2 * Device Tree Source for IBM Embedded PPC 476
3 *
4 * Copyright © 2011 Tony Breeds IBM Corporati
5 *
6 * This file is licensed under the terms of th
7 * License version 2. This program is license
8 * any warranty of any kind, whether express o
9 */
10
11 /dts-v1/;
12
13 /memreserve/ 0x01f00000 0x00100000; // spi
14
15 / {
16 #address-cells = <2>;
17 #size-cells = <2>;
18 model = "ibm,currituck";
19 compatible = "ibm,currituck";
20 dcr-parent = <&{/cpus/cpu@0}>;
21
22 aliases {
23 serial0 = &UART0;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 model = "PowerPC,476";
33 reg = <0>;
34 clock-frequency = <160
35 timebase-frequency = <
36 i-cache-line-size = <3
37 d-cache-line-size = <3
38 i-cache-size = <32768>
39 d-cache-size = <32768>
40 dcr-controller;
41 dcr-access-method = "n
42 status = "okay";
43 };
44 cpu@1 {
45 device_type = "cpu";
46 model = "PowerPC,476";
47 reg = <1>;
48 clock-frequency = <160
49 timebase-frequency = <
50 i-cache-line-size = <3
51 d-cache-line-size = <3
52 i-cache-size = <32768>
53 d-cache-size = <32768>
54 dcr-controller;
55 dcr-access-method = "n
56 status = "disabled";
57 enable-method = "spin-
58 cpu-release-addr = <0x
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 reg = <0x0 0x0 0x0 0x0>; // fi
65 };
66
67 MPIC: interrupt-controller {
68 compatible = "chrp,open-pic";
69 interrupt-controller;
70 dcr-reg = <0xffc00000 0x000400
71 #address-cells = <0>;
72 #size-cells = <0>;
73 #interrupt-cells = <2>;
74
75 };
76
77 plb {
78 compatible = "ibm,plb6";
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82 clock-frequency = <200000000>;
83
84 POB0: opb {
85 compatible = "ibm,opb-
86 #address-cells = <1>;
87 #size-cells = <1>;
88 /* Wish there was a ni
89 * 32-bit range
90 */
91 ranges = <0x00000000 0
92 0x80000000 0
93 clock-frequency = <100
94
95 UART0: serial@10000000
96 device_type =
97 compatible = "
98 reg = <0x10000
99 virtual-reg =
100 clock-frequenc
101 current-speed
102 interrupt-pare
103 interrupts = <
104 };
105
106 FPGA0: fpga@50000000 {
107 compatible = "
108 reg = <0x50000
109 };
110
111 IIC0: i2c@0 {
112 compatible = "
113 reg = <0x0 0x0
114 interrupt-pare
115 interrupts = <
116 #address-cells
117 #size-cells =
118 rtc@68 {
119 compat
120 reg =
121 };
122 };
123 };
124
125 PCIE0: pcie@10100000000 {
126 device_type = "pci";
127 #interrupt-cells = <1>
128 #size-cells = <2>;
129 #address-cells = <3>;
130 compatible = "ibm,plb-
131 primary;
132 port = <0x0>; /* port
133 reg = <0x00000101 0x00
134 0x00000100 0x00
135 dcr-reg = <0x80 0x20>;
136
137 // pci_space <
138 ranges = <0x02000000 0
139 0x01000000 0
140
141 /* Inbound starting at
142 dma-ranges = <0x420000
143
144 /* This drives busses
145 bus-range = <0x0 0xf>;
146
147 /* Legacy interrupts (
148 * to invert PCIe lega
149 * We are de-swizzling
150 * port of the root co
151 * to avoid putting a
152 * below are basically
153 * The real slot is on
154 */
155 interrupt-map-mask = <
156 interrupt-map = <
157 0x0 0x0 0x0 0x
158 0x0 0x0 0x0 0x
159 0x0 0x0 0x0 0x
160 0x0 0x0 0x0 0x
161 };
162
163 PCIE1: pcie@30100000000 {
164 device_type = "pci";
165 #interrupt-cells = <1>
166 #size-cells = <2>;
167 #address-cells = <3>;
168 compatible = "ibm,plb-
169 primary;
170 port = <0x1>; /* port
171 reg = <0x00000301 0x00
172 0x00000300 0x00
173 dcr-reg = <0x60 0x20>;
174
175 ranges = <0x02000000 0
176 0x01000000 0
177
178 /* Inbound starting at
179 dma-ranges = <0x420000
180
181 /* This drives busses
182 bus-range = <0x0 0xf>;
183
184 /* Legacy interrupts (
185 * to invert PCIe lega
186 * We are de-swizzling
187 * port of the root co
188 * to avoid putting a
189 * below are basically
190 * The real slot is on
191 */
192 interrupt-map-mask = <
193 interrupt-map = <
194 0x0 0x0 0x0 0x
195 0x0 0x0 0x0 0x
196 0x0 0x0 0x0 0x
197 0x0 0x0 0x0 0x
198 };
199
200 PCIE2: pcie@38100000000 {
201 device_type = "pci";
202 #interrupt-cells = <1>
203 #size-cells = <2>;
204 #address-cells = <3>;
205 compatible = "ibm,plb-
206 primary;
207 port = <0x2>; /* port
208 reg = <0x00000381 0x00
209 0x00000380 0x00
210 dcr-reg = <0xA0 0x20>;
211
212 ranges = <0x02000000 0
213 0x01000000 0
214
215 /* Inbound starting at
216 dma-ranges = <0x420000
217
218 /* This drives busses
219 bus-range = <0x0 0xf>;
220
221 /* Legacy interrupts (
222 * to invert PCIe lega
223 * We are de-swizzling
224 * port of the root co
225 * to avoid putting a
226 * below are basically
227 * The real slot is on
228 */
229 interrupt-map-mask = <
230 interrupt-map = <
231 0x0 0x0 0x0 0x
232 0x0 0x0 0x0 0x
233 0x0 0x0 0x0 0x
234 0x0 0x0 0x0 0x
235 };
236
237 };
238
239 chosen {
240 stdout-path = &UART0;
241 };
242 };
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