1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Digsy MTC board Device Tree Source
4 *
5 * Copyright (C) 2009 Semihalf
6 *
7 * Based on the CM5200 by M. Balakowicz
8 */
9
10 /include/ "mpc5200b.dtsi"
11
12 &gpt0 { gpio-controller; fsl,has-wdt; };
13 &gpt1 { gpio-controller; };
14
15 / {
16 model = "intercontrol,digsy-mtc";
17 compatible = "intercontrol,digsy-mtc";
18
19 memory@0 {
20 reg = <0x00000000 0x02000000>;
21 };
22
23 soc5200@f0000000 {
24 rtc@800 {
25 status = "disabled";
26 };
27
28 psc@2000 { // PSC
29 status = "disabled";
30 };
31
32 psc@2200 { // PSC
33 status = "disabled";
34 };
35
36 psc@2400 { // PSC
37 status = "disabled";
38 };
39
40 psc@2600 { // PSC
41 compatible = "fsl,mpc5
42 };
43
44 psc@2800 { // PSC
45 compatible = "fsl,mpc5
46 };
47
48 psc@2c00 { // PSC
49 status = "disabled";
50 };
51
52 ethernet@3000 {
53 phy-handle = <&phy0>;
54 };
55
56 mdio@3000 {
57 phy0: ethernet-phy@0 {
58 reg = <0>;
59 };
60 };
61
62 i2c@3d00 {
63 eeprom@50 {
64 compatible = "
65 reg = <0x50>;
66 };
67
68 rtc@56 {
69 compatible = "
70 reg = <0x56>;
71 };
72
73 rtc@68 {
74 compatible = "
75 reg = <0x68>;
76 };
77 };
78
79 i2c@3d40 {
80 status = "disabled";
81 };
82 };
83
84 pci@f0000d00 {
85 interrupt-map-mask = <0xf800 0
86 interrupt-map = <0xc000 0 0 1
87 0xc000 0 0 2
88 0xc000 0 0 3
89 0xc000 0 0 4
90 clock-frequency = <0>; // From
91 interrupts = <2 8 0 2 9 0 2 10
92 bus-range = <0 0>;
93 ranges = <0x42000000 0 0x80000
94 <0x02000000 0 0x90000
95 <0x01000000 0 0x00000
96 };
97
98 localbus {
99 ranges = <0 0 0xff000000 0x100
100 4 0 0x60000000 0x000
101
102 // 16-bit flash device at Loca
103 flash@0,0 {
104 compatible = "cfi-flas
105 reg = <0 0 0x1000000>;
106 bank-width = <2>;
107 device-width = <2>;
108 #size-cells = <1>;
109 #address-cells = <1>;
110
111 partition@0 {
112 label = "kerne
113 reg = <0x0 0x0
114 };
115 partition@200000 {
116 label = "root"
117 reg = <0x00200
118 };
119 partition@500000 {
120 label = "user"
121 reg = <0x00500
122 };
123 partition@f00000 {
124 label = "u-boo
125 reg = <0x00f00
126 };
127 };
128
129 can@4,0 {
130 compatible = "nxp,sja1
131 reg = <4 0x000 0x80>;
132 nxp,external-clock-fre
133 interrupts = <1 2 3>;
134 };
135
136 can@4,100 {
137 compatible = "nxp,sja1
138 reg = <4 0x100 0x80>;
139 nxp,external-clock-fre
140 interrupts = <1 2 3>;
141 };
142
143 serial@4,200 {
144 compatible = "nxp,sc28
145 reg = <4 0x200 0x10>;
146 interrupts = <1 3 3>;
147 };
148 };
149 };
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