1 /*
2 * B4420DS Device Tree Source
3 *
4 * Copyright 2012 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * This software is provided by Freescale Semi
24 * express or implied warranties, including, b
25 * warranties of merchantability and fitness f
26 * disclaimed. In no event shall Freescale Sem
27 * direct, indirect, incidental, special, exem
28 * (including, but not limited to, procurement
29 * loss of use, data, or profits; or business
30 * on any theory of liability, whether in cont
31 * (including negligence or otherwise) arising
32 * this software, even if advised of the possi
33 */
34
35 / {
36 model = "fsl,B4QDS";
37 compatible = "fsl,B4QDS";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 crypto = &crypto;
44 phy_sgmii_10 = &phy_sgmii_10;
45 phy_sgmii_11 = &phy_sgmii_11;
46 phy_sgmii_1c = &phy_sgmii_1c;
47 phy_sgmii_1d = &phy_sgmii_1d;
48 };
49
50 ifc: localbus@ffe124000 {
51 reg = <0xf 0xfe124000 0 0x2000
52 ranges = <0 0 0xf 0xe8000000 0
53 2 0 0xf 0xff800000 0
54 3 0 0xf 0xffdf0000 0
55
56 nor@0,0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "cfi-flas
60 reg = <0x0 0x0 0x80000
61 bank-width = <2>;
62 device-width = <1>;
63 };
64
65 nand@2,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "fsl,ifc-
69 reg = <0x2 0x0 0x10000
70
71 partition@0 {
72 /* This locati
73 /* 1MB for u-b
74 reg = <0x0 0x0
75 label = "NAND
76 read-only;
77 };
78
79 partition@100000 {
80 /* 1MB for DTB
81 reg = <0x00100
82 label = "NAND
83 };
84
85 partition@200000 {
86 /* 10MB for Li
87 reg = <0x00200
88 label = "NAND
89 };
90
91 partition@c00000 {
92 /* 500MB for R
93 reg = <0x00c00
94 label = "NAND
95 };
96 };
97
98 board-control@3,0 {
99 compatible = "fsl,b4qd
100 reg = <3 0 0x300>;
101 };
102 };
103
104 memory {
105 device_type = "memory";
106 };
107
108 reserved-memory {
109 #address-cells = <2>;
110 #size-cells = <2>;
111 ranges;
112
113 bman_fbpr: bman-fbpr {
114 size = <0 0x1000000>;
115 alignment = <0 0x10000
116 };
117 qman_fqd: qman-fqd {
118 size = <0 0x400000>;
119 alignment = <0 0x40000
120 };
121 qman_pfdr: qman-pfdr {
122 size = <0 0x2000000>;
123 alignment = <0 0x20000
124 };
125 };
126
127 dcsr: dcsr@f00000000 {
128 ranges = <0x00000000 0xf 0x000
129 };
130
131 bportals: bman-portals@ff4000000 {
132 ranges = <0x0 0xf 0xf4000000 0
133 };
134
135 qportals: qman-portals@ff6000000 {
136 ranges = <0x0 0xf 0xf6000000 0
137 };
138
139 soc: soc@ffe000000 {
140 ranges = <0x00000000 0xf 0xfe0
141 reg = <0xf 0xfe000000 0 0x0000
142 spi@110000 {
143 flash@0 {
144 #address-cells
145 #size-cells =
146 compatible = "
147 reg = <0>;
148 spi-max-freque
149 };
150 };
151
152 sdhc@114000 {
153 /*Disabled as there is
154 status = "disabled";
155 };
156
157 i2c@118000 {
158 mux@77 {
159 compatible = "
160 reg = <0x77>;
161 #address-cells
162 #size-cells =
163
164 i2c@0 {
165 #addre
166 #size-
167 reg =
168
169 eeprom
170
171
172 };
173 eeprom
174
175
176 };
177 eeprom
178
179
180 };
181 eeprom
182
183
184 };
185 rtc@68
186
187
188 };
189 };
190
191 i2c@2 {
192 #addre
193 #size-
194 reg =
195
196 ina220
197
198
199
200 };
201 };
202
203 i2c@3 {
204 #addre
205 #size-
206 reg =
207
208 adt746
209
210
211 };
212 };
213 };
214 };
215
216 usb@210000 {
217 dr_mode = "host";
218 phy_type = "ulpi";
219 };
220
221 fman@400000 {
222 ethernet@e0000 {
223 phy-handle = <
224 phy-connection
225 };
226
227 ethernet@e2000 {
228 phy-handle = <
229 phy-connection
230 };
231
232 ethernet@e4000 {
233 phy-handle = <
234 phy-connection
235 };
236
237 ethernet@e6000 {
238 phy-handle = <
239 phy-connection
240 };
241
242 mdio@fc000 {
243 phy_sgmii_10:
244 reg =
245 };
246
247 phy_sgmii_11:
248 reg =
249 };
250
251 phy_sgmii_1c:
252 reg =
253 status
254 };
255
256 phy_sgmii_1d:
257 reg =
258 status
259 };
260 };
261 };
262 };
263
264 pci0: pcie@ffe200000 {
265 reg = <0xf 0xfe200000 0 0x1000
266 ranges = <0x02000000 0 0xe0000
267 0x01000000 0 0x00000
268 pcie@0 {
269 ranges = <0x02000000 0
270 0x02000000 0
271 0 0x20000000
272
273 0x01000000 0
274 0x01000000 0
275 0 0x00010000
276 };
277 };
278 };
279
280 /include/ "b4si-post.dtsi"
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