1 /*
2 * BSC9131 Silicon/SoC Device Tree Source (pos
3 *
4 * Copyright 2011-2012 Freescale Semiconductor
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 &ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc";
39 interrupts = <16 2 0 0 20 2 0 0>;
40 };
41
42 &soc {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 device_type = "soc";
46 compatible = "fsl,bsc9131-immr", "simp
47 bus-frequency = <0>; // Fil
48
49 ecm-law@0 {
50 compatible = "fsl,ecm-law";
51 reg = <0x0 0x1000>;
52 fsl,num-laws = <12>;
53 };
54
55 ecm@1000 {
56 compatible = "fsl,bsc9131-ecm"
57 reg = <0x1000 0x1000>;
58 interrupts = <16 2 0 0>;
59 };
60
61 memory-controller@2000 {
62 compatible = "fsl,bsc9131-memo
63 reg = <0x2000 0x1000>;
64 interrupts = <16 2 0 0>;
65 };
66
67 /include/ "pq3-i2c-0.dtsi"
68 i2c@3000 {
69 interrupts = <17 2 0 0>;
70 };
71
72 /include/ "pq3-i2c-1.dtsi"
73 i2c@3100 {
74 interrupts = <17 2 0 0>;
75 };
76
77 /include/ "pq3-duart-0.dtsi"
78 serial0: serial@4500 {
79 interrupts = <18 2 0 0>;
80 };
81
82 serial1: serial@4600 {
83 interrupts = <18 2 0 0 >;
84 };
85 /include/ "pq3-espi-0.dtsi"
86 spi0: spi@7000 {
87 fsl,espi-num-chipselects = <1>
88 interrupts = <22 0x2 0 0>;
89 };
90
91 /include/ "pq3-gpio-0.dtsi"
92 gpio-controller@f000 {
93 interrupts = <19 0x2 0 0>;
94 };
95
96 L2: l2-cache-controller@20000 {
97 compatible = "fsl,bsc9131-l2-c
98 reg = <0x20000 0x1000>;
99 cache-line-size = <32>; // 32
100 cache-size = <0x40000>; // L2,
101 interrupts = <16 2 0 0>;
102 };
103
104 /include/ "pq3-dma-0.dtsi"
105
106 dma@21300 {
107
108 dma-channel@0 {
109 interrupts = <62 2 0 0>;
110 };
111
112 dma-channel@80 {
113 interrupts = <63 2 0 0>;
114 };
115
116 dma-channel@100 {
117 interrupts = <64 2 0 0>;
118 };
119
120 dma-channel@180 {
121 interrupts = <65 2 0 0>;
122 };
123 };
124
125 /include/ "pq3-usb2-dr-0.dtsi"
126 usb@22000 {
127 compatible = "fsl-usb2-dr","fsl-usb2-d
128 interrupts = <40 0x2 0 0>;
129 };
130
131 /include/ "pq3-esdhc-0.dtsi"
132 sdhc@2e000 {
133 sdhci,auto-cmd12;
134 interrupts = <41 0x2 0 0>;
135 };
136
137 /include/ "pq3-sec4.4-0.dtsi"
138 crypto@30000 {
139 interrupts = <57 2 0 0>;
140
141 sec_jr0: jr@1000 {
142 interrupts = <58 2 0 0>;
143 };
144
145 sec_jr1: jr@2000 {
146 interrupts = <59 2 0 0>;
147 };
148
149 sec_jr2: jr@3000 {
150 interrupts = <60 2 0 0>;
151 };
152
153 sec_jr3: jr@4000 {
154 interrupts = <61 2 0 0>;
155 };
156 };
157
158 /include/ "pq3-mpic.dtsi"
159
160 timer@41100 {
161 compatible = "fsl,mpic-v1.2-msgr", "fs
162 reg = <0x41400 0x200>;
163 interrupts = <
164 0xb0 2
165 0xb1 2
166 0xb2 2
167 0xb3 2>;
168 };
169
170 /include/ "pq3-etsec2-0.dtsi"
171 enet0: ethernet@b0000 {
172 queue-group@b0000 {
173 interrupts = <26 2 0 0 27 2 0
174 };
175 };
176
177 /include/ "pq3-etsec2-1.dtsi"
178 enet1: ethernet@b1000 {
179 queue-group@b1000 {
180 interrupts = <33 2 0 0 34 2 0
181 };
182 };
183
184 global-utilities@e0000 {
185 compatible = "fsl,bsc9131-guts
186 reg = <0xe0000 0x1000>;
187 fsl,has-rstcr;
188 };
189 };
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