1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * GE SBC610 Device Tree Source
4 *
5 * Copyright 2008 GE Intelligent Platforms Emb
6 *
7 * Based on: SBS CM6 Device Tree Source
8 * Copyright 2007 SBS Technologies GmbH & Co.
9 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device
10 * Copyright 2006 Freescale Semiconductor Inc.
11 */
12
13 /*
14 * Compiled with dtc -I dts -O dtb -o gef_sbc6
15 */
16
17 /include/ "mpc8641si-pre.dtsi"
18
19 / {
20 model = "GEF_SBC610";
21 compatible = "gef,sbc610";
22
23 memory {
24 device_type = "memory";
25 reg = <0x0 0x40000000>; // set
26 };
27
28 lbc: localbus@fef05000 {
29 reg = <0xfef05000 0x1000>;
30
31 ranges = <0 0 0xff000000 0x010
32 1 0 0xe8000000 0x080
33 2 0 0xe0000000 0x080
34 3 0 0xfc100000 0x000
35 4 0 0xfc000000 0x000
36 5 0 0xfc008000 0x000
37 6 0 0xfd000000 0x008
38 7 0 0xfd800000 0x008
39
40 /* flash@0,0 is a mirror of pa
41 flash@0,0 {
42 compatible = "gef,sbc6
43 reg = <0x0 0x0 0x10000
44 bank-width = <4>;
45 device-width = <2>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48 partition@0 {
49 label = "firmw
50 reg = <0x0 0x1
51 read-only;
52 };
53 };
54 */
55
56 flash@1,0 {
57 compatible = "gef,sbc6
58 reg = <0x1 0x0 0x80000
59 bank-width = <4>;
60 device-width = <2>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63 partition@0 {
64 label = "user"
65 reg = <0x0 0x7
66 };
67 partition@7800000 {
68 label = "firmw
69 reg = <0x78000
70 read-only;
71 };
72 };
73
74 nvram@3,0 {
75 device_type = "nvram";
76 compatible = "simtek,s
77 reg = <0x3 0x0 0x20000
78 };
79
80 fpga@4,0 {
81 compatible = "gef,fpga
82 reg = <0x4 0x0 0x40>;
83 };
84
85 wdt@4,2000 {
86 compatible = "gef,fpga
87 reg = <0x4 0x2000 0x8>
88 interrupts = <0x1a 0x4
89 interrupt-parent = <&g
90 };
91 /* Second watchdog available,
92 wdt@4,2010 {
93 compatible = "gef,fpga
94 reg = <0x4 0x2010 0x8>
95 interrupts = <0x1b 0x4
96 interrupt-parent = <&g
97 };
98 */
99 gef_pic: pic@4,4000 {
100 #interrupt-cells = <1>
101 interrupt-controller;
102 compatible = "gef,fpga
103 reg = <0x4 0x4000 0x20
104 interrupts = <0x8 0x9
105
106 };
107 gef_gpio: gpio@7,14000 {
108 #gpio-cells = <2>;
109 compatible = "gef,sbc6
110 reg = <0x7 0x14000 0x2
111 gpio-controller;
112 };
113 };
114
115 soc: soc@fef00000 {
116 ranges = <0x0 0xfef00000 0x001
117
118 i2c@3000 {
119 hwmon@48 {
120 compatible = "
121 reg = <0x48>;
122 };
123
124 hwmon@4c {
125 compatible = "
126 reg = <0x4c>;
127 };
128
129 rtc@51 {
130 compatible = "
131 reg = <0x00000
132 };
133
134 eti@6b {
135 compatible = "
136 reg = <0x6b>;
137 };
138 };
139
140 enet0: ethernet@24000 {
141 tbi-handle = <&tbi0>;
142 phy-handle = <&phy0>;
143 phy-connection-type =
144 };
145
146 mdio@24520 {
147 phy0: ethernet-phy@0 {
148 interrupt-pare
149 interrupts = <
150 reg = <1>;
151 };
152 phy2: ethernet-phy@2 {
153 interrupt-pare
154 interrupts = <
155 reg = <3>;
156 };
157 tbi0: tbi-phy@11 {
158 reg = <0x11>;
159 device_type =
160 };
161 };
162
163 enet1: ethernet@26000 {
164 tbi-handle = <&tbi2>;
165 phy-handle = <&phy2>;
166 phy-connection-type =
167 };
168
169 mdio@26520 {
170 tbi2: tbi-phy@11 {
171 reg = <0x11>;
172 device_type =
173 };
174 };
175
176 enet2: ethernet@25000 {
177 status = "disabled";
178 };
179
180 mdio@25520 {
181 status = "disabled";
182 };
183
184 enet3: ethernet@27000 {
185 status = "disabled";
186 };
187
188 mdio@27520 {
189 status = "disabled";
190 };
191 };
192
193 pci0: pcie@fef08000 {
194 reg = <0xfef08000 0x1000>;
195 ranges = <0x02000000 0x0 0x800
196 0x01000000 0x0 0x000
197
198 pcie@0 {
199 ranges = <0x02000000 0
200 0x02000000 0
201 0x0 0x400000
202
203 0x01000000 0
204 0x01000000 0
205 0x0 0x004000
206 };
207 };
208
209 pci1: pcie@fef09000 {
210 status = "disabled";
211 };
212 };
213
214 /include/ "mpc8641si-post.dtsi"
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