1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Keymile kmcent2 Device Tree Source, based o
4 *
5 * (C) Copyright 2016
6 * Valentin Longchamp, Keymile AG, valentin.lo
7 *
8 * Copyright 2014 - 2015 Freescale Semiconduct
9 */
10
11 /include/ "t104xsi-pre.dtsi"
12
13 / {
14 model = "keymile,kmcent2";
15 compatible = "keymile,kmcent2";
16
17 aliases {
18 front_phy = &front_phy;
19 };
20
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
24 ranges;
25
26 bman_fbpr: bman-fbpr {
27 size = <0 0x1000000>;
28 alignment = <0 0x10000
29 };
30 qman_fqd: qman-fqd {
31 size = <0 0x400000>;
32 alignment = <0 0x40000
33 };
34 qman_pfdr: qman-pfdr {
35 size = <0 0x2000000>;
36 alignment = <0 0x20000
37 };
38 };
39
40 ifc: localbus@ffe124000 {
41 reg = <0xf 0xfe124000 0 0x2000
42 ranges = <0 0 0xf 0xe8000000 0
43 1 0 0xf 0xfa000000 0
44 2 0 0xf 0xfb000000 0
45 4 0 0xf 0xc0000000 0
46 6 0 0xf 0xd0000000 0
47 7 0 0xf 0xd8000000 0
48
49 nor@0,0 {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 compatible = "cfi-flas
53 reg = <0x0 0x0 0x04000
54 bank-width = <2>;
55 device-width = <2>;
56 };
57
58 nand@1,0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "fsl,ifc-
62 reg = <0x1 0x0 0x10000
63 };
64
65 board-control@2,0 {
66 compatible = "keymile,
67 reg = <0x2 0x0 0x80>;
68 };
69
70 chassis-mgmt@6,0 {
71 compatible = "keymile,
72 reg = <6 0 0x100>;
73 interrupt-controller;
74 interrupt-parent = <&m
75 interrupts = <11 1 0 0
76 #interrupt-cells = <1>
77 };
78
79 };
80
81 memory {
82 device_type = "memory";
83 };
84
85 dcsr: dcsr@f00000000 {
86 ranges = <0x00000000 0xf 0x000
87 };
88
89 bportals: bman-portals@ff4000000 {
90 ranges = <0x0 0xf 0xf4000000 0
91 };
92
93 qportals: qman-portals@ff6000000 {
94 ranges = <0x0 0xf 0xf6000000 0
95 };
96
97 soc: soc@ffe000000 {
98 ranges = <0x00000000 0xf 0xfe0
99 reg = <0xf 0xfe000000 0 0x0000
100
101 spi@110000 {
102 network-clock@1 {
103 compatible = "
104 reg = <1>;
105 spi-max-freque
106 };
107 };
108
109 sdhc@114000 {
110 status = "disabled";
111 };
112
113 i2c@118000 {
114 clock-frequency = <100
115
116 mux@70 {
117 compatible = "
118 reg = <0x70>;
119 #address-cells
120 #size-cells =
121 i2c-mux-idle-d
122
123 i2c@0 {
124 reg =
125 #addre
126 #size-
127
128 eeprom
129
130
131
132
133
134 };
135 };
136
137 i2c@7 {
138 reg =
139 #addre
140 #size-
141
142 temp-s
143
144
145
146 };
147 temp-s
148
149
150
151 };
152 temp-s
153
154
155
156 };
157 };
158 };
159 };
160
161 i2c@118100 {
162 clock-frequency = <100
163
164 eeprom@50 {
165 compatible = "
166 reg = <0x50>;
167 pagesize = <16
168 };
169
170 eeprom@54 {
171 compatible = "
172 reg = <0x54>;
173 pagesize = <16
174 };
175 };
176
177 i2c@119000 {
178 status = "disabled";
179 };
180
181 i2c@119100 {
182 status = "disabled";
183 };
184
185 serial2: serial@11d500 {
186 status = "disabled";
187 };
188
189 serial3: serial@11d600 {
190 status = "disabled";
191 };
192
193 usb0: usb@210000 {
194 status = "disabled";
195 };
196 usb1: usb@211000 {
197 status = "disabled";
198 };
199
200 display@180000 {
201 status = "disabled";
202 };
203
204 sata@220000 {
205 status = "disabled";
206 };
207 sata@221000 {
208 status = "disabled";
209 };
210
211 fman@400000 {
212 ethernet@e0000 {
213 phy-mode = "sg
214 fixed-link {
215 speed
216 full-d
217 };
218 };
219
220 ethernet@e2000 {
221 phy-mode = "sg
222 fixed-link {
223 speed
224 full-d
225 };
226 };
227
228 ethernet@e4000 {
229 status = "disa
230 };
231
232 ethernet@e6000 {
233 status = "disa
234 };
235
236 ethernet@e8000 {
237 phy-handle = <
238 phy-mode = "rg
239 };
240
241 mdio0: mdio@fc000 {
242 front_phy: eth
243 reg =
244 };
245 };
246 };
247 };
248
249
250 pci0: pcie@ffe240000 {
251 reg = <0xf 0xfe240000 0 0x1000
252 ranges = <0x02000000 0 0xe0000
253 0x01000000 0 0x00000
254 pcie@0 {
255 ranges = <0x02000000 0
256 0x02000000 0
257 0 0x20000000
258
259 0x01000000 0
260 0x01000000 0
261 0 0x00010000
262 };
263 };
264
265 pci1: pcie@ffe250000 {
266 status = "disabled";
267 reg = <0xf 0xfe250000 0 0x1000
268 ranges = <0x02000000 0 0xe0000
269 0x01000000 0 0 0xf 0
270 pcie@0 {
271 ranges = <0x02000000 0
272 0x02000000 0
273 0 0x10000000
274
275 0x01000000 0
276 0x01000000 0
277 0 0x00010000
278 };
279 };
280
281 pci2: pcie@ffe260000 {
282 status = "disabled";
283 reg = <0xf 0xfe260000 0 0x1000
284 ranges = <0x02000000 0 0xe0000
285 0x01000000 0 0x00000
286 pcie@0 {
287 ranges = <0x02000000 0
288 0x02000000 0
289 0 0x10000000
290
291 0x01000000 0
292 0x01000000 0
293 0 0x00010000
294 };
295 };
296
297 pci3: pcie@ffe270000 {
298 status = "disabled";
299 reg = <0xf 0xfe270000 0 0x1000
300 ranges = <0x02000000 0 0xe0000
301 0x01000000 0 0x00000
302 pcie@0 {
303 ranges = <0x02000000 0
304 0x02000000 0
305 0 0x10000000
306
307 0x01000000 0
308 0x01000000 0
309 0 0x00010000
310 };
311 };
312
313 qe: qe@ffe140000 {
314 ranges = <0x0 0xf 0xfe140000 0
315 reg = <0xf 0xfe140000 0 0x480>
316 brg-frequency = <0>;
317 bus-frequency = <0>;
318
319 si1: si@700 {
320 compatible = "fsl,t104
321 reg = <0x700 0x80>;
322 };
323
324 siram1: siram@1000 {
325 compatible = "fsl,t104
326 reg = <0x1000 0x800>;
327 };
328
329 ucc_hdlc: ucc@2000 {
330 device_type = "hdlc";
331 compatible = "fsl,ucc-
332 rx-clock-name = "clk9"
333 tx-clock-name = "clk9"
334 fsl,hdlc-bus;
335 };
336 };
337 };
338
339 #include "t1040si-post.dtsi"
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