1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC8568E MDS Device Tree Source 4 * 5 * Copyright 2007, 2008 Freescale Semiconducto 6 */ 7 8 /include/ "mpc8568si-pre.dtsi" 9 10 / { 11 model = "MPC8568EMDS"; 12 compatible = "MPC8568EMDS", "MPC85xxMD 13 14 aliases { 15 pci0 = &pci0; 16 pci1 = &pci1; 17 rapidio0 = &rio; 18 }; 19 20 memory { 21 device_type = "memory"; 22 reg = <0x0 0x0 0x0 0x0>; 23 }; 24 25 lbc: localbus@e0005000 { 26 reg = <0x0 0xe0005000 0x0 0x10 27 ranges = <0x0 0x0 0xfe000000 0 28 0x1 0x0 0xf8000000 0 29 0x2 0x0 0xf0000000 0 30 0x4 0x0 0xf8008000 0 31 0x5 0x0 0xf8010000 0 32 33 nor@0,0 { 34 #address-cells = <1>; 35 #size-cells = <1>; 36 compatible = "cfi-flas 37 reg = <0x0 0x0 0x02000 38 bank-width = <2>; 39 device-width = <2>; 40 }; 41 42 bcsr@1,0 { 43 #address-cells = <1>; 44 #size-cells = <1>; 45 compatible = "fsl,mpc8 46 reg = <1 0 0x8000>; 47 ranges = <0 1 0 0x8000 48 49 bcsr5: gpio-controller 50 #gpio-cells = 51 compatible = " 52 reg = <0x5 0x1 53 gpio-controlle 54 }; 55 }; 56 57 pib@4,0 { 58 compatible = "fsl,mpc8 59 reg = <4 0 0x8000>; 60 }; 61 62 pib@5,0 { 63 compatible = "fsl,mpc8 64 reg = <5 0 0x8000>; 65 }; 66 }; 67 68 soc: soc8568@e0000000 { 69 ranges = <0x0 0x0 0xe0000000 0 70 71 i2c-sleep-nexus { 72 i2c@3000 { 73 rtc@68 { 74 compat 75 reg = 76 interr 77 }; 78 }; 79 }; 80 81 enet0: ethernet@24000 { 82 tbi-handle = <&tbi0>; 83 phy-handle = <&phy2>; 84 }; 85 86 mdio@24520 { 87 phy0: ethernet-phy@7 { 88 interrupts = < 89 reg = <0x7>; 90 }; 91 phy1: ethernet-phy@1 { 92 interrupts = < 93 reg = <0x1>; 94 }; 95 phy2: ethernet-phy@2 { 96 interrupts = < 97 reg = <0x2>; 98 }; 99 phy3: ethernet-phy@3 { 100 interrupts = < 101 reg = <0x3>; 102 }; 103 tbi0: tbi-phy@11 { 104 reg = <0x11>; 105 device_type = 106 }; 107 }; 108 109 enet1: ethernet@25000 { 110 tbi-handle = <&tbi1>; 111 phy-handle = <&phy3>; 112 sleep = <&pmc 0x000000 113 }; 114 115 mdio@25520 { 116 tbi1: tbi-phy@11 { 117 reg = <0x11>; 118 device_type = 119 }; 120 }; 121 122 par_io@e0100 { 123 num-ports = <7>; 124 125 pio1: ucc_pin@1 { 126 pio-map = < 127 /* port pin dir ope 128 0x4 0 129 0x4 0 130 0x4 0 131 0x4 0 132 0x4 0 133 0x4 0 134 0x4 0 135 0x4 0 136 0x4 0 137 0x4 0 138 0x4 0 139 0x4 0 140 0x4 0 141 0x4 0 142 0x4 0 143 0x4 0 144 0x4 0 145 0x4 0 146 0x4 0 147 0x4 0 148 0x4 0 149 0x4 0 150 0x1 0 151 }; 152 153 pio2: ucc_pin@2 { 154 pio-map = < 155 /* port pin dir ope 156 0x5 0 157 0x5 0 158 0x5 0 159 0x5 0 160 0x5 0 161 0x5 0 162 0x5 0 163 0x5 0 164 0x5 0 165 0x5 0 166 0x5 0 167 0x5 0 168 0x5 0 169 0x5 0 170 0x5 0 171 0x5 0 172 0x5 0 173 0x5 0 174 0x5 0 175 0x5 0 176 0x5 0 177 0x5 0 178 0x1 0 179 0x4 0 180 0x4 0 181 }; 182 }; 183 }; 184 185 qe: qe@e0080000 { 186 ranges = <0x0 0x0 0xe0080000 0 187 reg = <0x0 0xe0080000 0x0 0x48 188 189 spi@4c0 { 190 mode = "cpu"; 191 }; 192 193 spi@500 { 194 mode = "cpu"; 195 }; 196 197 enet2: ucc@2000 { 198 device_type = "network 199 compatible = "ucc_geth 200 local-mac-address = [ 201 rx-clock-name = "none" 202 tx-clock-name = "clk16 203 pio-handle = <&pio1>; 204 phy-handle = <&phy0>; 205 phy-connection-type = 206 }; 207 208 enet3: ucc@3000 { 209 device_type = "network 210 compatible = "ucc_geth 211 local-mac-address = [ 212 rx-clock-name = "none" 213 tx-clock-name = "clk16 214 pio-handle = <&pio2>; 215 phy-handle = <&phy1>; 216 phy-connection-type = 217 }; 218 219 mdio@2120 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 reg = <0x2120 0x18>; 223 compatible = "fsl,ucc- 224 225 /* These are the same 226 * gianfar's MDIO bus 227 qe_phy0: ethernet-phy@ 228 interrupt-pare 229 interrupts = < 230 reg = <0x7>; 231 }; 232 qe_phy1: ethernet-phy@ 233 interrupt-pare 234 interrupts = < 235 reg = <0x1>; 236 }; 237 qe_phy2: ethernet-phy@ 238 interrupt-pare 239 interrupts = < 240 reg = <0x2>; 241 }; 242 qe_phy3: ethernet-phy@ 243 interrupt-pare 244 interrupts = < 245 reg = <0x3>; 246 }; 247 }; 248 }; 249 250 pci0: pci@e0008000 { 251 reg = <0x0 0xe0008000 0x0 0x10 252 ranges = <0x2000000 0x0 0x8000 253 0x1000000 0x0 0x0000 254 clock-frequency = <66666666>; 255 interrupt-map-mask = <0xf800 0 256 interrupt-map = < 257 /* IDSEL 0x12 AD18 */ 258 0x9000 0x0 0x0 0x1 &mp 259 0x9000 0x0 0x0 0x2 &mp 260 0x9000 0x0 0x0 0x3 &mp 261 0x9000 0x0 0x0 0x4 &mp 262 263 /* IDSEL 0x13 AD19 */ 264 0x9800 0x0 0x0 0x1 &mp 265 0x9800 0x0 0x0 0x2 &mp 266 0x9800 0x0 0x0 0x3 &mp 267 0x9800 0x0 0x0 0x4 &mp 268 }; 269 270 /* PCI Express */ 271 pci1: pcie@e000a000 { 272 ranges = <0x2000000 0x0 0xa000 273 0x1000000 0x0 0x0000 274 reg = <0x0 0xe000a000 0x0 0x10 275 pcie@0 { 276 ranges = <0x2000000 0x 277 0x2000000 0x 278 0x0 0x100000 279 280 0x1000000 0x 281 0x1000000 0x 282 0x0 0x800000 283 }; 284 }; 285 286 rio: rapidio@e00c00000 { 287 reg = <0x0 0xe00c0000 0x0 0x20 288 port1 { 289 ranges = <0x0 0x0 0x0 290 }; 291 }; 292 293 leds { 294 compatible = "gpio-leds"; 295 296 green { 297 gpios = <&bcsr5 1 0>; 298 }; 299 300 amber { 301 gpios = <&bcsr5 2 0>; 302 }; 303 304 red { 305 gpios = <&bcsr5 3 0>; 306 }; 307 }; 308 }; 309 310 /include/ "mpc8568si-post.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.