1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8569E MDS Device Tree Source
4 *
5 * Copyright (C) 2009 Freescale Semiconductor
6 */
7
8 /include/ "mpc8569si-pre.dtsi"
9
10 / {
11 model = "MPC8569EMDS";
12 compatible = "fsl,MPC8569EMDS";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
16
17 aliases {
18 ethernet2 = &enet2;
19 ethernet3 = &enet3;
20 ethernet5 = &enet5;
21 ethernet7 = &enet7;
22 rapidio0 = &rio;
23 };
24
25 memory {
26 device_type = "memory";
27 };
28
29 lbc: localbus@e0005000 {
30 reg = <0x0 0xe0005000 0x0 0x10
31
32 ranges = <0x0 0x0 0x0 0xfe0000
33 0x1 0x0 0x0 0xf80000
34 0x2 0x0 0x0 0xf00000
35 0x3 0x0 0x0 0xfc0000
36 0x4 0x0 0x0 0xf80080
37 0x5 0x0 0x0 0xf80100
38
39 nor@0,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flas
43 reg = <0x0 0x0 0x02000
44 bank-width = <1>;
45 device-width = <1>;
46 partition@0 {
47 label = "ramdi
48 reg = <0x00000
49 };
50 partition@1c00000 {
51 label = "kerne
52 reg = <0x01c00
53 };
54 partition@1ee0000 {
55 label = "dtb";
56 reg = <0x01ee0
57 };
58 partition@1f00000 {
59 label = "firmw
60 reg = <0x01f00
61 read-only;
62 };
63 partition@1f80000 {
64 label = "u-boo
65 reg = <0x01f80
66 read-only;
67 };
68 };
69
70 bcsr@1,0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8
74 reg = <1 0 0x8000>;
75 ranges = <0 1 0 0x8000
76
77 bcsr17: gpio-controlle
78 #gpio-cells =
79 compatible = "
80 reg = <0x11 0x
81 gpio-controlle
82 };
83 };
84
85 nand@3,0 {
86 compatible = "fsl,mpc8
87 "fsl,elbc
88 reg = <3 0 0x8000>;
89 };
90
91 pib@4,0 {
92 compatible = "fsl,mpc8
93 reg = <4 0 0x8000>;
94 };
95
96 pib@5,0 {
97 compatible = "fsl,mpc8
98 reg = <5 0 0x8000>;
99 };
100 };
101
102 soc: soc@e0000000 {
103 ranges = <0x0 0x0 0xe0000000 0
104
105 i2c-sleep-nexus {
106 i2c@3000 {
107 rtc@68 {
108 compat
109 reg =
110 interr
111 };
112 };
113 };
114
115 sdhc@2e000 {
116 status = "disabled";
117 sdhci,1-bit-only;
118 bus-width = <1>;
119 };
120
121 par_io@e0100 {
122 num-ports = <7>;
123
124 qe_pio_e: gpio-control
125 #gpio-cells =
126 compatible = "
127 "
128 reg = <0x80 0x
129 gpio-controlle
130 };
131
132 qe_pio_f: gpio-control
133 #gpio-cells =
134 compatible = "
135 "
136 reg = <0xa0 0x
137 gpio-controlle
138 };
139
140 pio1: ucc_pin@1 {
141 pio-map = <
142 /* port pin dir ope
143 0x2 0
144 0x2 0
145 0x2 0
146 0x0 0
147 0x0 0
148 0x0 0
149 0x0 0
150 0x0 0
151 0x0 0
152 0x0 0
153 0x0 0
154 0x0 0
155 0x0 0
156 0x2 0
157 0x2 0
158 };
159
160 pio2: ucc_pin@2 {
161 pio-map = <
162 /* port pin dir ope
163 0x2 0
164 0x2 0
165 0x2 0
166 0x0 0
167 0x0 0
168 0x0 0
169 0x0 0
170 0x0 0
171 0x0 0
172 0x0 0
173 0x0 0
174 0x0 0
175 0x0 0
176 0x2 0
177 0x2 0
178 };
179
180 pio3: ucc_pin@3 {
181 pio-map = <
182 /* port pin dir ope
183 0x2 0
184 0x2 0
185 0x2 0
186 0x0 0
187 0x0 0
188 0x0 0
189 0x1 0
190 0x1 0
191 0x1 0
192 0x1 0
193 0x1 0
194 0x1 0
195 0x1 0
196 0x2 0
197 0x2 0
198 };
199
200 pio4: ucc_pin@4 {
201 pio-map = <
202 /* port pin dir ope
203 0x2 0
204 0x2 0
205 0x2 0
206 0x1 0
207 0x1 0
208 0x1 0
209 0x1 0
210 0x1 0
211 0x1 0
212 0x1 0
213 0x1 0
214 0x1 0
215 0x1 0
216 0x2 0
217 0x2 0
218 };
219 };
220 };
221
222 qe: qe@e0080000 {
223 ranges = <0x0 0x0 0xe0080000 0
224 reg = <0x0 0xe0080000 0x0 0x48
225
226 spi@4c0 {
227 gpios = <&qe_pio_e 30
228 mode = "cpu-qe";
229
230 serial-flash@0 {
231 compatible = "
232 reg = <0>;
233 spi-max-freque
234 };
235 };
236
237 spi@500 {
238 mode = "cpu";
239 };
240
241 usb@6c0 {
242 fsl,fullspeed-clock =
243 fsl,lowspeed-clock = "
244 gpios = <&qe_pio_f 3 0
245 &qe_pio_f 4 0
246 &qe_pio_f 5 0
247 &qe_pio_f 6 0
248 &qe_pio_f 8 0
249 &bcsr17 1 0
250 &bcsr17 2 0
251 };
252
253 enet0: ucc@2000 {
254 device_type = "network
255 compatible = "ucc_geth
256 local-mac-address = [
257 rx-clock-name = "none"
258 tx-clock-name = "clk12
259 pio-handle = <&pio1>;
260 tbi-handle = <&tbi1>;
261 phy-handle = <&qe_phy0
262 phy-connection-type =
263 };
264
265 mdio@2120 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 reg = <0x2120 0x18>;
269 compatible = "fsl,ucc-
270
271 qe_phy0: ethernet-phy@
272 interrupt-pare
273 interrupts = <
274 reg = <0x7>;
275 };
276 qe_phy1: ethernet-phy@
277 interrupt-pare
278 interrupts = <
279 reg = <0x1>;
280 };
281 qe_phy2: ethernet-phy@
282 interrupt-pare
283 interrupts = <
284 reg = <0x2>;
285 };
286 qe_phy3: ethernet-phy@
287 interrupt-pare
288 interrupts = <
289 reg = <0x3>;
290 };
291 qe_phy5: ethernet-phy@
292 reg = <0x04>;
293 };
294 qe_phy7: ethernet-phy@
295 reg = <0x6>;
296 };
297 tbi1: tbi-phy@11 {
298 reg = <0x11>;
299 device_type =
300 };
301 };
302 mdio@3520 {
303 #address-cells = <1>;
304 #size-cells = <0>;
305 reg = <0x3520 0x18>;
306 compatible = "fsl,ucc-
307
308 tbi6: tbi-phy@15 {
309 reg = <0x15>;
310 device_type = "tbi-phy
311 };
312 };
313 mdio@3720 {
314 #address-cells = <1>;
315 #size-cells = <0>;
316 reg = <0x3720 0x38>;
317 compatible = "fsl,ucc-
318 tbi8: tbi-phy@17 {
319 reg = <0x17>;
320 device_type =
321 };
322 };
323
324 enet2: ucc@2200 {
325 device_type = "network
326 compatible = "ucc_geth
327 local-mac-address = [
328 rx-clock-name = "none"
329 tx-clock-name = "clk12
330 pio-handle = <&pio3>;
331 tbi-handle = <&tbi3>;
332 phy-handle = <&qe_phy2
333 phy-connection-type =
334 };
335
336 mdio@2320 {
337 #address-cells = <1>;
338 #size-cells = <0>;
339 reg = <0x2320 0x18>;
340 compatible = "fsl,ucc-
341 tbi3: tbi-phy@11 {
342 reg = <0x11>;
343 device_type =
344 };
345 };
346
347 enet1: ucc@3000 {
348 device_type = "network
349 compatible = "ucc_geth
350 local-mac-address = [
351 rx-clock-name = "none"
352 tx-clock-name = "clk17
353 pio-handle = <&pio2>;
354 tbi-handle = <&tbi2>;
355 phy-handle = <&qe_phy1
356 phy-connection-type =
357 };
358
359 mdio@3120 {
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0x3120 0x18>;
363 compatible = "fsl,ucc-
364 tbi2: tbi-phy@11 {
365 reg = <0x11>;
366 device_type =
367 };
368 };
369
370 enet3: ucc@3200 {
371 device_type = "network
372 compatible = "ucc_geth
373 local-mac-address = [
374 rx-clock-name = "none"
375 tx-clock-name = "clk17
376 pio-handle = <&pio4>;
377 tbi-handle = <&tbi4>;
378 phy-handle = <&qe_phy3
379 phy-connection-type =
380 };
381
382 mdio@3320 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 reg = <0x3320 0x18>;
386 compatible = "fsl,ucc-
387 tbi4: tbi-phy@11 {
388 reg = <0x11>;
389 device_type =
390 };
391 };
392
393 enet5: ucc@3400 {
394 device_type = "network
395 compatible = "ucc_geth
396 local-mac-address = [
397 rx-clock-name = "none"
398 tx-clock-name = "none"
399 tbi-handle = <&tbi6>;
400 phy-handle = <&qe_phy5
401 phy-connection-type =
402 };
403
404 enet7: ucc@3600 {
405 device_type = "network
406 compatible = "ucc_geth
407 local-mac-address = [
408 rx-clock-name = "none"
409 tx-clock-name = "none"
410 tbi-handle = <&tbi8>;
411 phy-handle = <&qe_phy7
412 phy-connection-type =
413 };
414 };
415
416 /* PCI Express */
417 pci1: pcie@e000a000 {
418 reg = <0x0 0xe000a000 0x0 0x10
419 ranges = <0x2000000 0x0 0xa000
420 0x1000000 0x0 0x0000
421 pcie@0 {
422 ranges = <0x2000000 0x
423 0x2000000 0x
424 0x0 0x100000
425
426 0x1000000 0x
427 0x1000000 0x
428 0x0 0x800000
429 };
430 };
431
432 rio: rapidio@e00c00000 {
433 reg = <0x0 0xe00c0000 0x0 0x20
434 port1 {
435 ranges = <0x0 0x0 0x0
436 };
437 port2 {
438 status = "disabled";
439 };
440 };
441 };
442
443 /include/ "mpc8569si-post.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.