1 /*
2 * P1010 RDB Device Tree Source stub (no addre
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 memory {
36 device_type = "memory";
37 };
38
39 board_ifc: ifc: memory-controller@fffe1e000 {
40 /* NOR, NAND Flashes and CPLD on board
41 ranges = <0x0 0x0 0xf 0xee000000 0x020
42 0x1 0x0 0xf 0xff800000 0x000
43 0x3 0x0 0xf 0xffb00000 0x000
44 reg = <0xf 0xffe1e000 0 0x2000>;
45 };
46
47 board_soc: soc: soc@fffe00000 {
48 ranges = <0x0 0xf 0xffe00000 0x100000>
49 };
50
51 pci0: pcie@fffe09000 {
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc
54 0x1000000 0x0 0x00000000 0xf
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc000
57 0x2000000 0x0 0xc000
58 0x0 0x20000000
59
60 0x1000000 0x0 0x0
61 0x1000000 0x0 0x0
62 0x0 0x100000>;
63 };
64 };
65
66 pci1: pcie@fffe0a000 {
67 reg = <0xf 0xffe0a000 0 0x1000>;
68 ranges = <0x2000000 0x0 0xc0000000 0xc
69 0x1000000 0x0 0x00000000 0xf
70 pcie@0 {
71 ranges = <0x2000000 0x0 0xc000
72 0x2000000 0x0 0xc000
73 0x0 0x20000000
74
75 0x1000000 0x0 0x0
76 0x1000000 0x0 0x0
77 0x0 0x100000>;
78 };
79 };
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