1 /*
2 * P1021/P1012 Silicon/SoC Device Tree Source
3 *
4 * Copyright 2011-2012 Freescale Semiconductor
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 &lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,el
39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
41 };
42
43 /* controller at 0x9000 */
44 &pci0 {
45 compatible = "fsl,mpc8548-pcie";
46 device_type = "pci";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
51 interrupts = <16 2 0 0>;
52
53 pcie@0 {
54 reg = <0 0 0 0 0>;
55 #interrupt-cells = <1>;
56 #size-cells = <2>;
57 #address-cells = <3>;
58 device_type = "pci";
59 interrupts = <16 2 0 0>;
60 interrupt-map-mask = <0xf800 0
61 interrupt-map = <
62 /* IDSEL 0x0 */
63 0000 0x0 0x0 0x1 &mpic
64 0000 0x0 0x0 0x2 &mpic
65 0000 0x0 0x0 0x3 &mpic
66 0000 0x0 0x0 0x4 &mpic
67 >;
68 };
69 };
70
71 /* controller at 0xa000 */
72 &pci1 {
73 compatible = "fsl,mpc8548-pcie";
74 device_type = "pci";
75 #size-cells = <2>;
76 #address-cells = <3>;
77 bus-range = <0 255>;
78 clock-frequency = <33333333>;
79 interrupts = <16 2 0 0>;
80
81 pcie@0 {
82 reg = <0 0 0 0 0>;
83 #interrupt-cells = <1>;
84 #size-cells = <2>;
85 #address-cells = <3>;
86 device_type = "pci";
87 interrupts = <16 2 0 0>;
88 interrupt-map-mask = <0xf800 0
89
90 interrupt-map = <
91 /* IDSEL 0x0 */
92 0000 0x0 0x0 0x1 &mpic
93 0000 0x0 0x0 0x2 &mpic
94 0000 0x0 0x0 0x3 &mpic
95 0000 0x0 0x0 0x4 &mpic
96 >;
97 };
98 };
99
100 &soc {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 device_type = "soc";
104 compatible = "fsl,p1021-immr", "simple
105 bus-frequency = <0>; // Fil
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <12>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,p1021-ecm",
115 reg = <0x1000 0x1000>;
116 interrupts = <16 2 0 0>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,p1021-memory
121 reg = <0x2000 0x1000>;
122 interrupts = <16 2 0 0>;
123 };
124
125 /include/ "pq3-i2c-0.dtsi"
126 /include/ "pq3-i2c-1.dtsi"
127 /include/ "pq3-duart-0.dtsi"
128
129 /include/ "pq3-espi-0.dtsi"
130 spi@7000 {
131 fsl,espi-num-chipselects = <4>
132 };
133
134 /include/ "pq3-gpio-0.dtsi"
135
136 L2: l2-cache-controller@20000 {
137 compatible = "fsl,p1021-l2-cac
138 reg = <0x20000 0x1000>;
139 cache-line-size = <32>; // 32
140 cache-size = <0x40000>; // L2,
141 interrupts = <16 2 0 0>;
142 };
143
144 /include/ "pq3-dma-0.dtsi"
145 /include/ "pq3-usb2-dr-0.dtsi"
146 usb@22000 {
147 compatible = "fsl-usb2-dr-v1.6
148 };
149
150 /include/ "pq3-esdhc-0.dtsi"
151 sdhc@2e000 {
152 sdhci,auto-cmd12;
153 };
154
155 /include/ "pq3-sec3.3-0.dtsi"
156
157 /include/ "pq3-mpic.dtsi"
158 /include/ "pq3-mpic-timer-B.dtsi"
159
160 /include/ "pq3-etsec2-0.dtsi"
161 enet0: enet0_grp2: ethernet@b0000 {
162 fsl,pmc-handle = <&etsec1_clk>
163 };
164
165 /include/ "pq3-etsec2-1.dtsi"
166 enet1: enet1_grp2: ethernet@b1000 {
167 fsl,pmc-handle = <&etsec2_clk>
168 };
169
170 /include/ "pq3-etsec2-2.dtsi"
171 enet2: enet2_grp2: ethernet@b2000 {
172 fsl,pmc-handle = <&etsec3_clk>
173 };
174
175 global-utilities@e0000 {
176 compatible = "fsl,p1021-guts";
177 reg = <0xe0000 0x1000>;
178 fsl,has-rstcr;
179 };
180
181 /include/ "pq3-power.dtsi"
182 };
183
184 &qe {
185 #address-cells = <1>;
186 #size-cells = <1>;
187 device_type = "qe";
188 compatible = "fsl,qe";
189 fsl,qe-num-riscs = <1>;
190 fsl,qe-num-snums = <28>;
191
192 qeic: interrupt-controller@80 {
193 interrupt-controller;
194 compatible = "fsl,qe-ic";
195 #address-cells = <0>;
196 #interrupt-cells = <1>;
197 reg = <0x80 0x80>;
198 interrupts = <63 2 0 0 60 2 0
199 };
200
201 ucc@2000 {
202 cell-index = <1>;
203 reg = <0x2000 0x200>;
204 interrupts = <32>;
205 interrupt-parent = <&qeic>;
206 };
207
208 mdio@2120 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 reg = <0x2120 0x18>;
212 compatible = "fsl,ucc-mdio";
213 };
214
215 ucc@2400 {
216 cell-index = <5>;
217 reg = <0x2400 0x200>;
218 interrupts = <40>;
219 interrupt-parent = <&qeic>;
220 };
221
222 ucc@2600 {
223 cell-index = <7>;
224 reg = <0x2600 0x200>;
225 interrupts = <42>;
226 interrupt-parent = <&qeic>;
227 };
228
229 ucc@2200 {
230 cell-index = <3>;
231 reg = <0x2200 0x200>;
232 interrupts = <34>;
233 interrupt-parent = <&qeic>;
234 };
235
236 muram@10000 {
237 #address-cells = <1>;
238 #size-cells = <1>;
239 compatible = "fsl,qe-muram", "
240 ranges = <0x0 0x10000 0x6000>;
241
242 data-only@0 {
243 compatible = "fsl,qe-m
244 "fsl,cpm-muram-data";
245 reg = <0x0 0x6000>;
246 };
247 };
248 };
249
250 /include/ "pq3-etsec2-grp2-0.dtsi"
251 /include/ "pq3-etsec2-grp2-1.dtsi"
252 /include/ "pq3-etsec2-grp2-2.dtsi"
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