1 /*
2 * P1025 TWR Device Tree Source stub (no addre
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /{
36 aliases {
37 ethernet3 = &enet3;
38 ethernet4 = &enet4;
39 };
40 };
41
42 &lbc {
43 nor@0,0 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
47 reg = <0x0 0x0 0x4000000>;
48 bank-width = <2>;
49 device-width = <1>;
50
51 partition@0 {
52 /* This location must
53 /* 256KB for Vitesse 7
54 reg = <0x0 0x00040000>
55 label = "NOR Vitesse-7
56 read-only;
57 };
58
59 partition@40000 {
60 /* 256KB for DTB Image
61 reg = <0x00040000 0x00
62 label = "NOR DTB Image
63 };
64
65 partition@80000 {
66 /* 5.5 MB for Linux Ke
67 reg = <0x00080000 0x00
68 label = "NOR Linux Ker
69 };
70
71 partition@400000 {
72 /* 56.75MB for Root fi
73 reg = <0x00600000 0x03
74 label = "NOR Root File
75 };
76
77 partition@ec0000 {
78 /* This location must
79 /* 256KB for QE ucode
80 reg = <0x03ec0000 0x00
81 label = "NOR QE microc
82 read-only;
83 };
84
85 partition@f00000 {
86 /* This location must
87 /* 512KB for u-boot Bo
88 /* 512KB for u-boot En
89 reg = <0x03f00000 0x00
90 label = "NOR U-Boot Im
91 read-only;
92 };
93 };
94
95 /* CS2 for Display */
96 display@2,0 {
97 compatible = "solomon,ssd1289f
98 reg = <0x2 0x0000 0x0004>;
99 };
100
101 };
102
103 &soc {
104 usb@22000 {
105 phy_type = "ulpi";
106 };
107
108 mdio@24000 {
109 phy0: ethernet-phy@2 {
110 interrupt-parent = <&m
111 interrupts = <1 1 0 0>
112 reg = <0x2>;
113 };
114
115 phy1: ethernet-phy@1 {
116 interrupt-parent = <&m
117 interrupts = <2 1 0 0>
118 reg = <0x1>;
119 };
120
121 tbi0: tbi-phy@11 {
122 reg = <0x11>;
123 device_type = "tbi-phy
124 };
125 };
126
127 mdio@25000 {
128 tbi1: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy
131 };
132 };
133
134 mdio@26000 {
135 tbi2: tbi-phy@11 {
136 reg = <0x11>;
137 device_type = "tbi-phy
138 };
139 };
140
141 ptp_clock@b0e00 {
142 compatible = "fsl,etsec-ptp";
143 reg = <0xb0e00 0xb0>;
144 interrupts = <68 2 0 0 69 2 0
145 fsl,tclk-period = <10>;
146 fsl,tmr-prsc = <2>;
147 fsl,tmr-add = <0xc0000021>
148 fsl,tmr-fiper1 = <999999990>;
149 fsl,tmr-fiper2 = <99990>;
150 fsl,max-adj = <133333332>;
151 };
152
153 enet0: ethernet@b0000 {
154 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-i
156
157 };
158
159 enet1: ethernet@b1000 {
160 status = "disabled";
161 };
162
163 enet2: ethernet@b2000 {
164 phy-handle = <&phy1>;
165 phy-connection-type = "rgmii-i
166 };
167
168 par_io@e0100 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 reg = <0xe0100 0x60>;
172 ranges = <0x0 0xe0100 0x60>;
173 device_type = "par_io";
174 num-ports = <3>;
175 pio1: ucc_pin@1 {
176 pio-map = <
177 /* port pin dir open_drain
178 0x1 0x13 0x1
179 0x1 0x14 0x3
180 0x0 0x17 0x2
181 0x0 0x18 0x2
182 0x0 0x7 0x1
183 0x0 0x9 0x1
184 0x0 0xb 0x1
185 0x0 0xc 0x1
186 0x0 0x6 0x2
187 0x0 0xa 0x2
188 0x0 0xe 0x2
189 0x0 0xf 0x2
190 0x0 0x5 0x1
191 0x0 0xd 0x1
192 0x0 0x4 0x2
193 0x0 0x8 0x2
194 0x0 0x11 0x2
195 0x0 0x10 0x2
196 };
197
198 pio2: ucc_pin@2 {
199 pio-map = <
200 /* port pin dir open_drain
201 0x1 0x13 0x1
202 0x1 0x14 0x3
203 0x1 0xb 0x2
204 0x1 0x7 0x1
205 0x1 0xa 0x1
206 0x1 0x6 0x2
207 0x1 0x9 0x2
208 0x1 0x5 0x1
209 0x1 0x4 0x2
210 0x1 0x8 0x2
211 };
212
213 pio3: ucc_pin@3 {
214 pio-map = <
215 /* port pin dir open_drain
216 0x0 0x16 0x2
217 0x0 0x12 0x2
218 0x0 0x13 0x1
219 0x0 0x14 0x2
220 0x0 0x15 0x1
221 };
222
223 pio4: ucc_pin@4 {
224 pio-map = <
225 /* port pin dir open_drain
226 0x1 0x0 0x2
227 0x0 0x1c 0x2
228 0x0 0x1d 0x1
229 0x0 0x1e 0x2
230 0x0 0x1f 0x1
231 };
232 };
233 };
234
235 &qe {
236 enet3: ucc@2000 {
237 device_type = "network";
238 compatible = "ucc_geth";
239 rx-clock-name = "clk12";
240 tx-clock-name = "clk9";
241 pio-handle = <&pio1>;
242 phy-handle = <&qe_phy0>;
243 phy-connection-type = "mii";
244 };
245
246 mdio@2120 {
247 qe_phy0: ethernet-phy@18 {
248 interrupt-parent = <&m
249 interrupts = <4 1 0 0>
250 reg = <0x18>;
251 device_type = "etherne
252 };
253 qe_phy1: ethernet-phy@19 {
254 interrupt-parent = <&m
255 interrupts = <5 1 0 0>
256 reg = <0x19>;
257 device_type = "etherne
258 };
259 tbi-phy@11 {
260 reg = <0x11>;
261 device_type = "tbi-phy
262 };
263 };
264
265 enet4: ucc@2400 {
266 device_type = "network";
267 compatible = "ucc_geth";
268 rx-clock-name = "none";
269 tx-clock-name = "clk13";
270 pio-handle = <&pio2>;
271 phy-handle = <&qe_phy1>;
272 phy-connection-type = "rmii";
273 };
274
275 serial2: ucc@2600 {
276 device_type = "serial";
277 compatible = "ucc_uart";
278 port-number = <0>;
279 rx-clock-name = "brg6";
280 tx-clock-name = "brg6";
281 pio-handle = <&pio3>;
282 };
283
284 serial3: ucc@2200 {
285 device_type = "serial";
286 compatible = "ucc_uart";
287 port-number = <1>;
288 rx-clock-name = "brg2";
289 tx-clock-name = "brg2";
290 pio-handle = <&pio4>;
291 };
292 };
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