1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * P2020 DS Device Tree Source
4 *
5 * Copyright 2009-2011 Freescale Semiconductor
6 */
7
8 /include/ "p2020si-pre.dtsi"
9
10 / {
11 model = "fsl,P2020DS";
12 compatible = "fsl,P2020DS";
13
14 memory {
15 device_type = "memory";
16 };
17
18 board_lbc: lbc: localbus@ffe05000 {
19 ranges = <0x0 0x0 0x0 0xe80000
20 0x1 0x0 0x0 0xe00000
21 0x2 0x0 0x0 0xffa000
22 0x3 0x0 0x0 0xffdf00
23 0x4 0x0 0x0 0xffa400
24 0x5 0x0 0x0 0xffa800
25 0x6 0x0 0x0 0xffac00
26 reg = <0 0xffe05000 0 0x1000>;
27 };
28
29 board_soc: soc: soc@ffe00000 {
30 ranges = <0x0 0x0 0xffe00000 0
31 };
32
33 pci2: pcie@ffe08000 {
34 ranges = <0x2000000 0x0 0x8000
35 0x1000000 0x0 0x0000
36 reg = <0 0xffe08000 0 0x1000>;
37 pcie@0 {
38 ranges = <0x2000000 0x
39 0x2000000 0x
40 0x0 0x200000
41
42 0x1000000 0x
43 0x1000000 0x
44 0x0 0x10000>
45 };
46 };
47
48 board_pci1: pci1: pcie@ffe09000 {
49 ranges = <0x2000000 0x0 0xa000
50 0x1000000 0x0 0x0000
51 reg = <0 0xffe09000 0 0x1000>;
52 pcie@0 {
53 ranges = <0x2000000 0x
54 0x2000000 0x
55 0x0 0x200000
56
57 0x1000000 0x
58 0x1000000 0x
59 0x0 0x10000>
60 };
61 };
62
63 pci0: pcie@ffe0a000 {
64 ranges = <0x2000000 0x0 0xc000
65 0x1000000 0x0 0x0000
66 reg = <0 0xffe0a000 0 0x1000>;
67 pcie@0 {
68 ranges = <0x2000000 0x
69 0x2000000 0x
70 0x0 0x200000
71
72 0x1000000 0x
73 0x1000000 0x
74 0x0 0x10000>
75 };
76 };
77 };
78
79 /*
80 * p2020ds.dtsi must be last to ensure board_p
81 * for interrupt-map & interrupt-map-mask
82 */
83
84 /include/ "p2020si-post.dtsi"
85 /include/ "p2020ds.dtsi"
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