1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * P2020 RDB Device Tree Source
4 *
5 * Copyright 2009-2012 Freescale Semiconductor
6 */
7
8 /include/ "p2020si-pre.dtsi"
9
10 / {
11 model = "fsl,P2020RDB";
12 compatible = "fsl,P2020RDB";
13
14 aliases {
15 ethernet0 = &enet0;
16 ethernet1 = &enet1;
17 ethernet2 = &enet2;
18 serial0 = &serial0;
19 serial1 = &serial1;
20 pci0 = &pci0;
21 pci1 = &pci1;
22 };
23
24 memory {
25 device_type = "memory";
26 };
27
28 lbc: localbus@ffe05000 {
29 reg = <0 0xffe05000 0 0x1000>;
30
31 /* NOR and NAND Flashes */
32 ranges = <0x0 0x0 0x0 0xef0000
33 0x1 0x0 0x0 0xffa000
34 0x2 0x0 0x0 0xffb000
35
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flas
40 reg = <0x0 0x0 0x10000
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This locati
46 /* 256KB for V
47 reg = <0x0 0x0
48 label = "NOR (
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for D
54 reg = <0x00040
55 label = "NOR (
56 read-only;
57 };
58
59 partition@80000 {
60 /* 3.5 MB for
61 reg = <0x00080
62 label = "NOR (
63 read-only;
64 };
65
66 partition@400000 {
67 /* 11MB for JF
68 reg = <0x00400
69 label = "NOR (
70 };
71
72 partition@f00000 {
73 /* This locati
74 /* 512KB for u
75 /* 512KB for u
76 reg = <0x00f00
77 label = "NOR (
78 read-only;
79 };
80 };
81
82 nand@1,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "fsl,p202
86 "fsl,elbc
87 reg = <0x1 0x0 0x40000
88
89 partition@0 {
90 /* This locati
91 /* 1MB for u-b
92 reg = <0x0 0x0
93 label = "NAND
94 read-only;
95 };
96
97 partition@100000 {
98 /* 1MB for DTB
99 reg = <0x00100
100 label = "NAND
101 read-only;
102 };
103
104 partition@200000 {
105 /* 4MB for Lin
106 reg = <0x00200
107 label = "NAND
108 read-only;
109 };
110
111 partition@600000 {
112 /* 4MB for Com
113 reg = <0x00600
114 label = "NAND
115 read-only;
116 };
117
118 partition@a00000 {
119 /* 7MB for JFF
120 reg = <0x00a00
121 label = "NAND
122 };
123
124 partition@1100000 {
125 /* 15MB for JF
126 reg = <0x01100
127 label = "NAND
128 };
129 };
130
131 L2switch@2,0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "vitesse-
135 reg = <0x2 0x0 0x20000
136 };
137
138 };
139
140 soc: soc@ffe00000 {
141 ranges = <0x0 0x0 0xffe00000 0
142
143 i2c@3000 {
144 rtc@68 {
145 compatible = "
146 reg = <0x68>;
147 };
148 };
149
150 spi@7000 {
151 flash@0 {
152 #address-cells
153 #size-cells =
154 compatible = "
155 reg = <0>;
156 spi-max-freque
157
158 partition@0 {
159 /* 512
160 reg =
161 label
162 read-o
163 };
164
165 partition@8000
166 /* 512
167 reg =
168 label
169 read-o
170 };
171
172 partition@1000
173 /* 4MB
174 reg =
175 label
176 read-o
177 };
178
179 partition@5000
180 /* 4MB
181 reg =
182 label
183 read-o
184 };
185
186 partition@9000
187 /* 7MB
188 reg =
189 label
190 };
191 };
192 };
193
194 usb@22000 {
195 phy_type = "ulpi";
196 dr_mode = "host";
197 };
198
199 mdio@24520 {
200 phy0: ethernet-phy@0 {
201 interrupts = <
202 reg = <0x0>;
203 };
204 phy1: ethernet-phy@1 {
205 interrupts = <
206 reg = <0x1>;
207 };
208 tbi-phy@2 {
209 device_type =
210 reg = <0x2>;
211 };
212 };
213
214 mdio@25520 {
215 tbi0: tbi-phy@11 {
216 reg = <0x11>;
217 device_type =
218 };
219 };
220
221 mdio@26520 {
222 status = "disabled";
223 };
224
225 ptp_clock@24e00 {
226 fsl,tclk-period = <5>;
227 fsl,tmr-prsc = <200>;
228 fsl,tmr-add = <0xCCCCC
229 fsl,tmr-fiper1 = <0x3B
230 fsl,tmr-fiper2 = <0x00
231 fsl,max-adj = <2499999
232 };
233
234 enet0: ethernet@24000 {
235 fixed-link = <1 1 1000
236 phy-connection-type =
237 };
238
239 enet1: ethernet@25000 {
240 tbi-handle = <&tbi0>;
241 phy-handle = <&phy0>;
242 phy-connection-type =
243 };
244
245 enet2: ethernet@26000 {
246 phy-handle = <&phy1>;
247 phy-connection-type =
248 };
249 };
250
251 pci0: pcie@ffe08000 {
252 reg = <0 0xffe08000 0 0x1000>;
253 status = "disabled";
254 };
255
256 pci1: pcie@ffe09000 {
257 reg = <0 0xffe09000 0 0x1000>;
258 ranges = <0x2000000 0x0 0xa000
259 0x1000000 0x0 0x0000
260 pcie@0 {
261 ranges = <0x2000000 0x
262 0x2000000 0x
263 0x0 0x200000
264
265 0x1000000 0x
266 0x1000000 0x
267 0x0 0x100000
268 };
269 };
270
271 pci2: pcie@ffe0a000 {
272 reg = <0 0xffe0a000 0 0x1000>;
273 ranges = <0x2000000 0x0 0x8000
274 0x1000000 0x0 0x0000
275 pcie@0 {
276 ranges = <0x2000000 0x
277 0x2000000 0x
278 0x0 0x200000
279
280 0x1000000 0x
281 0x1000000 0x
282 0x0 0x100000
283 };
284 };
285 };
286
287 /include/ "p2020si-post.dtsi"
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