1 /*
2 * P2041 Silicon/SoC Device Tree Source (pre i
3 *
4 * Copyright 2011 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /dts-v1/;
36
37 /include/ "e500mc_power_isa.dtsi"
38
39 / {
40 compatible = "fsl,P2041";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 pci0 = &pci0;
54 pci1 = &pci1;
55 pci2 = &pci2;
56 usb0 = &usb0;
57 usb1 = &usb1;
58 dma0 = &dma0;
59 dma1 = &dma1;
60 sdhc = &sdhc;
61 msi0 = &msi0;
62 msi1 = &msi1;
63 msi2 = &msi2;
64
65 crypto = &crypto;
66 sec_jr0 = &sec_jr0;
67 sec_jr1 = &sec_jr1;
68 sec_jr2 = &sec_jr2;
69 sec_jr3 = &sec_jr3;
70 rtic_a = &rtic_a;
71 rtic_b = &rtic_b;
72 rtic_c = &rtic_c;
73 rtic_d = &rtic_d;
74 sec_mon = &sec_mon;
75
76 fman0 = &fman0;
77 ethernet0 = &enet0;
78 ethernet1 = &enet1;
79 ethernet2 = &enet2;
80 ethernet3 = &enet3;
81 ethernet4 = &enet4;
82 ethernet5 = &enet5;
83 };
84
85 cpus {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 cpu0: PowerPC,e500mc@0 {
90 device_type = "cpu";
91 reg = <0>;
92 clocks = <&clockgen 1
93 next-level-cache = <&L
94 fsl,portid-mapping = <
95 L2_0: l2-cache {
96 next-level-cac
97 };
98 };
99 cpu1: PowerPC,e500mc@1 {
100 device_type = "cpu";
101 reg = <1>;
102 clocks = <&clockgen 1
103 next-level-cache = <&L
104 fsl,portid-mapping = <
105 L2_1: l2-cache {
106 next-level-cac
107 };
108 };
109 cpu2: PowerPC,e500mc@2 {
110 device_type = "cpu";
111 reg = <2>;
112 clocks = <&clockgen 1
113 next-level-cache = <&L
114 fsl,portid-mapping = <
115 L2_2: l2-cache {
116 next-level-cac
117 };
118 };
119 cpu3: PowerPC,e500mc@3 {
120 device_type = "cpu";
121 reg = <3>;
122 clocks = <&clockgen 1
123 next-level-cache = <&L
124 fsl,portid-mapping = <
125 L2_3: l2-cache {
126 next-level-cac
127 };
128 };
129 };
130 };
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