1 /*
2 * P4080/P4040 Silicon/SoC Device Tree Source
3 *
4 * Copyright 2011 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /dts-v1/;
36
37 /include/ "e500mc_power_isa.dtsi"
38
39 / {
40 compatible = "fsl,P4080";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 pci0 = &pci0;
54 pci1 = &pci1;
55 pci2 = &pci2;
56 usb0 = &usb0;
57 usb1 = &usb1;
58 dma0 = &dma0;
59 dma1 = &dma1;
60 sdhc = &sdhc;
61 msi0 = &msi0;
62 msi1 = &msi1;
63 msi2 = &msi2;
64
65 crypto = &crypto;
66 sec_jr0 = &sec_jr0;
67 sec_jr1 = &sec_jr1;
68 sec_jr2 = &sec_jr2;
69 sec_jr3 = &sec_jr3;
70 rtic_a = &rtic_a;
71 rtic_b = &rtic_b;
72 rtic_c = &rtic_c;
73 rtic_d = &rtic_d;
74 sec_mon = &sec_mon;
75
76 fman0 = &fman0;
77 fman1 = &fman1;
78 ethernet0 = &enet0;
79 ethernet1 = &enet1;
80 ethernet2 = &enet2;
81 ethernet3 = &enet3;
82 ethernet4 = &enet4;
83 ethernet5 = &enet5;
84 ethernet6 = &enet6;
85 ethernet7 = &enet7;
86 ethernet8 = &enet8;
87 ethernet9 = &enet9;
88 };
89
90 cpus {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 cpu0: PowerPC,e500mc@0 {
95 device_type = "cpu";
96 reg = <0>;
97 clocks = <&clockgen 1
98 next-level-cache = <&L
99 fsl,portid-mapping = <
100 L2_0: l2-cache {
101 next-level-cac
102 };
103 };
104 cpu1: PowerPC,e500mc@1 {
105 device_type = "cpu";
106 reg = <1>;
107 clocks = <&clockgen 1
108 next-level-cache = <&L
109 fsl,portid-mapping = <
110 L2_1: l2-cache {
111 next-level-cac
112 };
113 };
114 cpu2: PowerPC,e500mc@2 {
115 device_type = "cpu";
116 reg = <2>;
117 clocks = <&clockgen 1
118 next-level-cache = <&L
119 fsl,portid-mapping = <
120 L2_2: l2-cache {
121 next-level-cac
122 };
123 };
124 cpu3: PowerPC,e500mc@3 {
125 device_type = "cpu";
126 reg = <3>;
127 clocks = <&clockgen 1
128 next-level-cache = <&L
129 fsl,portid-mapping = <
130 L2_3: l2-cache {
131 next-level-cac
132 };
133 };
134 cpu4: PowerPC,e500mc@4 {
135 device_type = "cpu";
136 reg = <4>;
137 clocks = <&clockgen 1
138 next-level-cache = <&L
139 fsl,portid-mapping = <
140 L2_4: l2-cache {
141 next-level-cac
142 };
143 };
144 cpu5: PowerPC,e500mc@5 {
145 device_type = "cpu";
146 reg = <5>;
147 clocks = <&clockgen 1
148 next-level-cache = <&L
149 fsl,portid-mapping = <
150 L2_5: l2-cache {
151 next-level-cac
152 };
153 };
154 cpu6: PowerPC,e500mc@6 {
155 device_type = "cpu";
156 reg = <6>;
157 clocks = <&clockgen 1
158 next-level-cache = <&L
159 fsl,portid-mapping = <
160 L2_6: l2-cache {
161 next-level-cac
162 };
163 };
164 cpu7: PowerPC,e500mc@7 {
165 device_type = "cpu";
166 reg = <7>;
167 clocks = <&clockgen 1
168 next-level-cache = <&L
169 fsl,portid-mapping = <
170 L2_7: l2-cache {
171 next-level-cac
172 };
173 };
174 };
175 };
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