1 /*
2 * P5020/P5010 Silicon/SoC Device Tree Source
3 *
4 * Copyright 2011 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /dts-v1/;
36
37 /include/ "e5500_power_isa.dtsi"
38
39 / {
40 compatible = "fsl,P5020";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 pci0 = &pci0;
54 pci1 = &pci1;
55 pci2 = &pci2;
56 pci3 = &pci3;
57 usb0 = &usb0;
58 usb1 = &usb1;
59 dma0 = &dma0;
60 dma1 = &dma1;
61 sdhc = &sdhc;
62 msi0 = &msi0;
63 msi1 = &msi1;
64 msi2 = &msi2;
65
66 crypto = &crypto;
67 sec_jr0 = &sec_jr0;
68 sec_jr1 = &sec_jr1;
69 sec_jr2 = &sec_jr2;
70 sec_jr3 = &sec_jr3;
71 rtic_a = &rtic_a;
72 rtic_b = &rtic_b;
73 rtic_c = &rtic_c;
74 rtic_d = &rtic_d;
75 sec_mon = &sec_mon;
76
77 raideng = &raideng;
78 raideng_jr0 = &raideng_jr0;
79 raideng_jr1 = &raideng_jr1;
80 raideng_jr2 = &raideng_jr2;
81 raideng_jr3 = &raideng_jr3;
82
83 fman0 = &fman0;
84 ethernet0 = &enet0;
85 ethernet1 = &enet1;
86 ethernet2 = &enet2;
87 ethernet3 = &enet3;
88 ethernet4 = &enet4;
89 ethernet5 = &enet5;
90 };
91
92 cpus {
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 cpu0: PowerPC,e5500@0 {
97 device_type = "cpu";
98 reg = <0>;
99 clocks = <&clockgen 1
100 next-level-cache = <&L
101 fsl,portid-mapping = <
102 L2_0: l2-cache {
103 next-level-cac
104 };
105 };
106 cpu1: PowerPC,e5500@1 {
107 device_type = "cpu";
108 reg = <1>;
109 clocks = <&clockgen 1
110 next-level-cache = <&L
111 fsl,portid-mapping = <
112 L2_1: l2-cache {
113 next-level-cac
114 };
115 };
116 };
117 };
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