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Linux/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi

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Diff markup

Differences between /arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi (Version linux-6.12-rc7) and /arch/i386/boot/dts/fsl/p5040si-pre.dtsi (Version linux-5.12.19)


  1 /*                                                
  2  * P5040 Silicon/SoC Device Tree Source (pre i    
  3  *                                                
  4  * Copyright 2012 - 2015 Freescale Semiconduct    
  5  *                                                
  6  * Redistribution and use in source and binary    
  7  * modification, are permitted provided that t    
  8  *     * Redistributions of source code must r    
  9  *       notice, this list of conditions and t    
 10  *     * Redistributions in binary form must r    
 11  *       notice, this list of conditions and t    
 12  *       documentation and/or other materials     
 13  *     * Neither the name of Freescale Semicon    
 14  *       names of its contributors may be used    
 15  *       derived from this software without sp    
 16  *                                                
 17  *                                                
 18  * ALTERNATIVELY, this software may be distrib    
 19  * GNU General Public License ("GPL") as publi    
 20  * Foundation, either version 2 of that Licens    
 21  * later version.                                 
 22  *                                                
 23  * This software is provided by Freescale Semi    
 24  * express or implied warranties, including, b    
 25  * warranties of merchantability and fitness f    
 26  * disclaimed. In no event shall Freescale Sem    
 27  * direct, indirect, incidental, special, exem    
 28  * (including, but not limited to, procurement    
 29  * loss of use, data, or profits; or business     
 30  * on any theory of liability, whether in cont    
 31  * (including negligence or otherwise) arising    
 32  * software, even if advised of the possibilit    
 33  */                                               
 34                                                   
 35 /dts-v1/;                                         
 36                                                   
 37 /include/ "e5500_power_isa.dtsi"                  
 38                                                   
 39 / {                                               
 40         compatible = "fsl,P5040";                 
 41         #address-cells = <2>;                     
 42         #size-cells = <2>;                        
 43         interrupt-parent = <&mpic>;               
 44                                                   
 45         aliases {                                 
 46                 ccsr = &soc;                      
 47                 dcsr = &dcsr;                     
 48                                                   
 49                 serial0 = &serial0;               
 50                 serial1 = &serial1;               
 51                 serial2 = &serial2;               
 52                 serial3 = &serial3;               
 53                 pci0 = &pci0;                     
 54                 pci1 = &pci1;                     
 55                 pci2 = &pci2;                     
 56                 usb0 = &usb0;                     
 57                 usb1 = &usb1;                     
 58                 dma0 = &dma0;                     
 59                 dma1 = &dma1;                     
 60                 sdhc = &sdhc;                     
 61                 msi0 = &msi0;                     
 62                 msi1 = &msi1;                     
 63                 msi2 = &msi2;                     
 64                                                   
 65                 crypto = &crypto;                 
 66                 sec_jr0 = &sec_jr0;               
 67                 sec_jr1 = &sec_jr1;               
 68                 sec_jr2 = &sec_jr2;               
 69                 sec_jr3 = &sec_jr3;               
 70                 rtic_a = &rtic_a;                 
 71                 rtic_b = &rtic_b;                 
 72                 rtic_c = &rtic_c;                 
 73                 rtic_d = &rtic_d;                 
 74                 sec_mon = &sec_mon;               
 75                                                   
 76                 raideng = &raideng;               
 77                 raideng_jr0 = &raideng_jr0;       
 78                 raideng_jr1 = &raideng_jr1;       
 79                 raideng_jr2 = &raideng_jr2;       
 80                 raideng_jr3 = &raideng_jr3;       
 81                                                   
 82                 fman0 = &fman0;                   
 83                 fman1 = &fman1;                   
 84                 ethernet0 = &enet0;               
 85                 ethernet1 = &enet1;               
 86                 ethernet2 = &enet2;               
 87                 ethernet3 = &enet3;               
 88                 ethernet4 = &enet4;               
 89                 ethernet5 = &enet5;               
 90                 ethernet6 = &enet6;               
 91                 ethernet7 = &enet7;               
 92                 ethernet8 = &enet8;               
 93                 ethernet9 = &enet9;               
 94                 ethernet10 = &enet10;             
 95                 ethernet11 = &enet11;             
 96         };                                        
 97                                                   
 98         cpus {                                    
 99                 #address-cells = <1>;             
100                 #size-cells = <0>;                
101                                                   
102                 cpu0: PowerPC,e5500@0 {           
103                         device_type = "cpu";      
104                         reg = <0>;                
105                         clocks = <&clockgen 1     
106                         next-level-cache = <&L    
107                         fsl,portid-mapping = <    
108                         L2_0: l2-cache {          
109                                 next-level-cac    
110                         };                        
111                 };                                
112                 cpu1: PowerPC,e5500@1 {           
113                         device_type = "cpu";      
114                         reg = <1>;                
115                         clocks = <&clockgen 1     
116                         next-level-cache = <&L    
117                         fsl,portid-mapping = <    
118                         L2_1: l2-cache {          
119                                 next-level-cac    
120                         };                        
121                 };                                
122                 cpu2: PowerPC,e5500@2 {           
123                         device_type = "cpu";      
124                         reg = <2>;                
125                         clocks = <&clockgen 1     
126                         next-level-cache = <&L    
127                         fsl,portid-mapping = <    
128                         L2_2: l2-cache {          
129                                 next-level-cac    
130                         };                        
131                 };                                
132                 cpu3: PowerPC,e5500@3 {           
133                         device_type = "cpu";      
134                         reg = <3>;                
135                         clocks = <&clockgen 1     
136                         next-level-cache = <&L    
137                         fsl,portid-mapping = <    
138                         L2_3: l2-cache {          
139                                 next-level-cac    
140                         };                        
141                 };                                
142         };                                        
143 };                                                
                                                      

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