1 /*
2 * QorIQ MPIC device tree stub [ controller @
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 mpic: pic@40000 {
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic", "chrp,open-pi
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
43 };
44
45 timer@41100 {
46 compatible = "fsl,mpic-global-timer";
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
52 };
53
54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
56 reg = <0x41600 0x200 0x44140 4>;
57 msi-available-ranges = <0 0x100>;
58 interrupts = <
59 0xe0 0 0 0
60 0xe1 0 0 0
61 0xe2 0 0 0
62 0xe3 0 0 0
63 0xe4 0 0 0
64 0xe5 0 0 0
65 0xe6 0 0 0
66 0xe7 0 0 0>;
67 };
68
69 msi1: msi@41800 {
70 compatible = "fsl,mpic-msi";
71 reg = <0x41800 0x200 0x45140 4>;
72 msi-available-ranges = <0 0x100>;
73 interrupts = <
74 0xe8 0 0 0
75 0xe9 0 0 0
76 0xea 0 0 0
77 0xeb 0 0 0
78 0xec 0 0 0
79 0xed 0 0 0
80 0xee 0 0 0
81 0xef 0 0 0>;
82 };
83
84 msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi";
86 reg = <0x41a00 0x200 0x46140 4>;
87 msi-available-ranges = <0 0x100>;
88 interrupts = <
89 0xf0 0 0 0
90 0xf1 0 0 0
91 0xf2 0 0 0
92 0xf3 0 0 0
93 0xf4 0 0 0
94 0xf5 0 0 0
95 0xf6 0 0 0
96 0xf7 0 0 0>;
97 };
98
99 timer@42100 {
100 compatible = "fsl,mpic-global-timer";
101 reg = <0x42100 0x100 0x42300 4>;
102 interrupts = <4 0 3 0
103 5 0 3 0
104 6 0 3 0
105 7 0 3 0>;
106 };
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