1 /*
2 * T1024 RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "t102xsi-pre.dtsi"
36
37 / {
38 model = "fsl,T1024RDB";
39 compatible = "fsl,T1024RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 sg_2500_aqr105_phy4 = &sg_2500
46 };
47
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
51 ranges;
52
53 bman_fbpr: bman-fbpr {
54 size = <0 0x1000000>;
55 alignment = <0 0x10000
56 };
57
58 qman_fqd: qman-fqd {
59 size = <0 0x400000>;
60 alignment = <0 0x40000
61 };
62
63 qman_pfdr: qman-pfdr {
64 size = <0 0x2000000>;
65 alignment = <0 0x20000
66 };
67 };
68
69 ifc: localbus@ffe124000 {
70 reg = <0xf 0xfe124000 0 0x2000
71 ranges = <0 0 0xf 0xe8000000 0
72 2 0 0xf 0xff800000 0
73 3 0 0xf 0xffdf0000 0
74
75 nor@0,0 {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "cfi-flas
79 reg = <0x0 0x0 0x80000
80 bank-width = <2>;
81 device-width = <1>;
82 };
83
84 nand@1,0 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 compatible = "fsl,ifc-
88 reg = <0x2 0x0 0x10000
89 };
90
91 board-control@2,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,t102
95 reg = <3 0 0x300>;
96 ranges = <0 3 0 0x300>
97 bank-width = <1>;
98 device-width = <1>;
99 };
100 };
101
102 memory {
103 device_type = "memory";
104 };
105
106 dcsr: dcsr@f00000000 {
107 ranges = <0x00000000 0xf 0x000
108 };
109
110 bportals: bman-portals@ff4000000 {
111 ranges = <0x0 0xf 0xf4000000 0
112 };
113
114 qportals: qman-portals@ff6000000 {
115 ranges = <0x0 0xf 0xf6000000 0
116 };
117
118 soc: soc@ffe000000 {
119 ranges = <0x00000000 0xf 0xfe0
120 reg = <0xf 0xfe000000 0 0x0000
121 spi@110000 {
122 flash@0 {
123 #address-cells
124 #size-cells =
125 compatible = "
126 reg = <0>;
127 spi-max-freque
128 };
129
130 slic@1 {
131 compatible = "
132 reg = <1>;
133 spi-max-freque
134 };
135
136 slic@2 {
137 compatible = "
138 reg = <2>;
139 spi-max-freque
140 };
141 };
142
143 i2c@118000 {
144 adt7461@4c {
145 /* Thermal Mon
146 compatible = "
147 reg = <0x4c>;
148 };
149
150 current-sensor@40 {
151 compatible = "
152 reg = <0x40>;
153 shunt-resistor
154 };
155
156 eeprom@50 {
157 compatible = "
158 reg = <0x50>;
159 };
160
161 rtc@68 {
162 compatible = "
163 reg = <0x68>;
164 };
165 };
166
167 i2c@118100 {
168 i2c-mux@77 {
169 compatible = "
170 reg = <0x77>;
171 #address-cells
172 #size-cells =
173 };
174 };
175
176 fman@400000 {
177 fm1mac1: ethernet@e000
178 phy-handle = <
179 phy-connection
180 sleep = <&rcpm
181 };
182
183 fm1mac2: ethernet@e200
184 sleep = <&rcpm
185 };
186
187 fm1mac3: ethernet@e400
188 phy-handle = <
189 phy-connection
190 sleep = <&rcpm
191 };
192
193 fm1mac4: ethernet@e600
194 phy-handle = <
195 phy-connection
196 sleep = <&rcpm
197 };
198
199
200 mdio0: mdio@fc000 {
201 rgmii_phy1: et
202 reg =
203 };
204 rgmii_phy2: et
205 reg =
206 };
207 };
208
209 xmdio0: mdio@fd000 {
210 xg_aqr105_phy3
211 compat
212 reg =
213 };
214 sg_2500_aqr105
215 compat
216 reg =
217 };
218 };
219 };
220 };
221
222 pci0: pcie@ffe240000 {
223 reg = <0xf 0xfe240000 0 0x1000
224 ranges = <0x02000000 0 0xe0000
225 0x01000000 0 0x00000
226 pcie@0 {
227 ranges = <0x02000000 0
228 0x02000000 0
229 0 0x10000000
230
231 0x01000000 0
232 0x01000000 0
233 0 0x00010000
234 };
235 };
236
237 pci1: pcie@ffe250000 {
238 reg = <0xf 0xfe250000 0 0x1000
239 ranges = <0x02000000 0 0xe0000
240 0x01000000 0 0x00000
241 pcie@0 {
242 ranges = <0x02000000 0
243 0x02000000 0
244 0 0x10000000
245
246 0x01000000 0
247 0x01000000 0
248 0 0x00010000
249 };
250 };
251
252 pci2: pcie@ffe260000 {
253 reg = <0xf 0xfe260000 0 0x1000
254 ranges = <0x02000000 0 0xe0000
255 0x01000000 0 0x00000
256 pcie@0 {
257 ranges = <0x02000000 0
258 0x02000000 0
259 0 0x10000000
260
261 0x01000000 0
262 0x01000000 0
263 0 0x00010000
264 };
265 };
266 };
267
268 #include "t1024si-post.dtsi"
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