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Linux/arch/powerpc/boot/dts/fsl/t104xqds.dtsi

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Diff markup

Differences between /arch/powerpc/boot/dts/fsl/t104xqds.dtsi (Version linux-6.12-rc7) and /arch/i386/boot/dts/fsl/t104xqds.dtsi (Version linux-5.16.20)


  1 /*                                                
  2  * T104xQDS Device Tree Source                    
  3  *                                                
  4  * Copyright 2013 - 2015 Freescale Semiconduct    
  5  *                                                
  6  * Redistribution and use in source and binary    
  7  * modification, are permitted provided that t    
  8  *     * Redistributions of source code must r    
  9  *       notice, this list of conditions and t    
 10  *     * Redistributions in binary form must r    
 11  *       notice, this list of conditions and t    
 12  *       documentation and/or other materials     
 13  *     * Neither the name of Freescale Semicon    
 14  *       names of its contributors may be used    
 15  *       derived from this software without sp    
 16  *                                                
 17  *                                                
 18  * ALTERNATIVELY, this software may be distrib    
 19  * GNU General Public License ("GPL") as publi    
 20  * Foundation, either version 2 of that Licens    
 21  * later version.                                 
 22  *                                                
 23  * THIS SOFTWARE IS PROVIDED BY Freescale Semi    
 24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B    
 25  * WARRANTIES OF MERCHANTABILITY AND FITNESS F    
 26  * DISCLAIMED. IN NO EVENT SHALL Freescale Sem    
 27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM    
 28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT    
 29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS     
 30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONT    
 31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING    
 32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT    
 33  */                                               
 34                                                   
 35 / {                                               
 36         model = "fsl,T1040QDS";                   
 37         #address-cells = <2>;                     
 38         #size-cells = <2>;                        
 39         interrupt-parent = <&mpic>;               
 40                                                   
 41         aliases {                                 
 42                 emi1_rgmii0 = &t1040mdio0;        
 43                 emi1_rgmii1 = &t1040mdio1;        
 44                 emi1_slot3 = &t1040mdio3;         
 45                 emi1_slot5 = &t1040mdio5;         
 46                 emi1_slot6 = &t1040mdio6;         
 47                 emi1_slot7 = &t1040mdio7;         
 48                 rgmii_phy1 = &rgmii_phy1;         
 49                 rgmii_phy2 = &rgmii_phy2;         
 50                 phy_s3_01 = &phy_s3_01;           
 51                 phy_s3_02 = &phy_s3_02;           
 52                 phy_s3_03 = &phy_s3_03;           
 53                 phy_s3_04 = &phy_s3_04;           
 54                 phy_s5_01 = &phy_s5_01;           
 55                 phy_s5_02 = &phy_s5_02;           
 56                 phy_s5_03 = &phy_s5_03;           
 57                 phy_s5_04 = &phy_s5_04;           
 58                 phy_s6_01 = &phy_s6_01;           
 59                 phy_s6_02 = &phy_s6_02;           
 60                 phy_s6_03 = &phy_s6_03;           
 61                 phy_s6_04 = &phy_s6_04;           
 62                 phy_s7_01 = &phy_s7_01;           
 63                 phy_s7_02 = &phy_s7_02;           
 64                 phy_s7_03 = &phy_s7_03;           
 65                 phy_s7_04 = &phy_s7_04;           
 66         };                                        
 67                                                   
 68         reserved-memory {                         
 69                 #address-cells = <2>;             
 70                 #size-cells = <2>;                
 71                 ranges;                           
 72                                                   
 73                 bman_fbpr: bman-fbpr {            
 74                         size = <0 0x1000000>;     
 75                         alignment = <0 0x10000    
 76                 };                                
 77                 qman_fqd: qman-fqd {              
 78                         size = <0 0x400000>;      
 79                         alignment = <0 0x40000    
 80                 };                                
 81                 qman_pfdr: qman-pfdr {            
 82                         size = <0 0x2000000>;     
 83                         alignment = <0 0x20000    
 84                 };                                
 85         };                                        
 86                                                   
 87         ifc: localbus@ffe124000 {                 
 88                 reg = <0xf 0xfe124000 0 0x2000    
 89                 ranges = <0 0 0xf 0xe8000000 0    
 90                           2 0 0xf 0xff800000 0    
 91                           3 0 0xf 0xffdf0000 0    
 92                                                   
 93                 nor@0,0 {                         
 94                         #address-cells = <1>;     
 95                         #size-cells = <1>;        
 96                         compatible = "cfi-flas    
 97                         reg = <0x0 0x0 0x80000    
 98                                                   
 99                         bank-width = <2>;         
100                         device-width = <1>;       
101                 };                                
102                                                   
103                 nand@2,0 {                        
104                         #address-cells = <1>;     
105                         #size-cells = <1>;        
106                         compatible = "fsl,ifc-    
107                         reg = <0x2 0x0 0x10000    
108                 };                                
109                                                   
110                 board-control@3,0 {               
111                         #address-cells = <1>;     
112                         #size-cells = <1>;        
113                         compatible = "fsl,fpga    
114                         reg = <3 0 0x300>;        
115                         ranges = <0 3 0 0x300>    
116                                                   
117                         mdio-mux-emi1 {           
118                                 #address-cells    
119                                 #size-cells =     
120                                 compatible = "    
121                                 mdio-parent-bu    
122                                 reg = <0x54 1>    
123                                 mux-mask = <0x    
124                                                   
125                                 t1040mdio0: md    
126                                         #addre    
127                                         #size-    
128                                         reg =     
129                                         status    
130                                                   
131                                         rgmii_    
132                                                   
133                                         };        
134                                 };                
135                                                   
136                                 t1040mdio1: md    
137                                         #addre    
138                                         #size-    
139                                         reg =     
140                                         status    
141                                                   
142                                         rgmii_    
143                                                   
144                                         };        
145                                 };                
146                                                   
147                                 t1040mdio3: md    
148                                         #addre    
149                                         #size-    
150                                         reg =     
151                                         status    
152                                                   
153                                         phy_s3    
154                                                   
155                                         };        
156                                                   
157                                         phy_s3    
158                                                   
159                                         };        
160                                                   
161                                         phy_s3    
162                                                   
163                                         };        
164                                                   
165                                         phy_s3    
166                                                   
167                                         };        
168                                 };                
169                                                   
170                                 t1040mdio5: md    
171                                         #addre    
172                                         #size-    
173                                         reg =     
174                                                   
175                                         phy_s5    
176                                                   
177                                         };        
178                                                   
179                                         phy_s5    
180                                                   
181                                         };        
182                                                   
183                                         phy_s5    
184                                                   
185                                         };        
186                                                   
187                                         phy_s5    
188                                                   
189                                         };        
190                                 };                
191                                                   
192                                 t1040mdio6: md    
193                                         #addre    
194                                         #size-    
195                                         reg =     
196                                                   
197                                         phy_s6    
198                                                   
199                                         };        
200                                                   
201                                         phy_s6    
202                                                   
203                                         };        
204                                                   
205                                         phy_s6    
206                                                   
207                                         };        
208                                                   
209                                         phy_s6    
210                                                   
211                                         };        
212                                 };                
213                                                   
214                                 t1040mdio7: md    
215                                         #addre    
216                                         #size-    
217                                         reg =     
218                                         status    
219                                                   
220                                         phy_s7    
221                                                   
222                                         };        
223                                                   
224                                         phy_s7    
225                                                   
226                                         };        
227                                                   
228                                         phy_s7    
229                                                   
230                                         };        
231                                                   
232                                         phy_s7    
233                                                   
234                                         };        
235                                 };                
236                         };                        
237                 };                                
238         };                                        
239                                                   
240         memory {                                  
241                 device_type = "memory";           
242         };                                        
243                                                   
244         dcsr: dcsr@f00000000 {                    
245                 ranges = <0x00000000 0xf 0x000    
246         };                                        
247                                                   
248         bportals: bman-portals@ff4000000 {        
249                 ranges = <0x0 0xf 0xf4000000 0    
250         };                                        
251                                                   
252         qportals: qman-portals@ff6000000 {        
253                 ranges = <0x0 0xf 0xf6000000 0    
254         };                                        
255                                                   
256         soc: soc@ffe000000 {                      
257                 ranges = <0x00000000 0xf 0xfe0    
258                 reg = <0xf 0xfe000000 0 0x0000    
259                                                   
260                 spi@110000 {                      
261                         flash@0 {                 
262                                 #address-cells    
263                                 #size-cells =     
264                                 compatible = "    
265                                 reg = <0>;        
266                                 spi-max-freque    
267                         };                        
268                 };                                
269                                                   
270                 i2c@118000 {                      
271                         i2c-mux@77 {              
272                                 compatible = "    
273                                 reg = <0x77>;     
274                         };                        
275                         rtc@68 {                  
276                                 compatible = "    
277                                 reg = <0x68>;     
278                                 interrupts = <    
279                         };                        
280                 };                                
281                                                   
282                 fman@400000 {                     
283                         ethernet@e0000 {          
284                                 fixed-link = <    
285                                 phy-connection    
286                         };                        
287                                                   
288                         ethernet@e2000 {          
289                                 fixed-link = <    
290                                 phy-connection    
291                         };                        
292                                                   
293                         ethernet@e4000 {          
294                                 phy-handle = <    
295                                 phy-connection    
296                         };                        
297                                                   
298                         ethernet@e6000 {          
299                                 phy-handle = <    
300                                 phy-connection    
301                         };                        
302                                                   
303                         ethernet@e8000 {          
304                                 phy-handle = <    
305                                 phy-connection    
306                         };                        
307                 };                                
308         };                                        
309                                                   
310         pci0: pcie@ffe240000 {                    
311                 reg = <0xf 0xfe240000 0 0x1000    
312                 ranges = <0x02000000 0 0xe0000    
313                           0x01000000 0 0x00000    
314                 pcie@0 {                          
315                         ranges = <0x02000000 0    
316                                   0x02000000 0    
317                                   0 0x10000000    
318                                                   
319                                   0x01000000 0    
320                                   0x01000000 0    
321                                   0 0x00010000    
322                 };                                
323         };                                        
324                                                   
325         pci1: pcie@ffe250000 {                    
326                 reg = <0xf 0xfe250000 0 0x1000    
327                 ranges = <0x02000000 0x0 0xe00    
328                           0x01000000 0x0 0x000    
329                 pcie@0 {                          
330                         ranges = <0x02000000 0    
331                                   0x02000000 0    
332                                   0 0x10000000    
333                                                   
334                                   0x01000000 0    
335                                   0x01000000 0    
336                                   0 0x00010000    
337                 };                                
338         };                                        
339                                                   
340         pci2: pcie@ffe260000 {                    
341                 reg = <0xf 0xfe260000 0 0x1000    
342                 ranges = <0x02000000 0 0xe0000    
343                           0x01000000 0 0x00000    
344                 pcie@0 {                          
345                         ranges = <0x02000000 0    
346                                   0x02000000 0    
347                                   0 0x10000000    
348                                                   
349                                   0x01000000 0    
350                                   0x01000000 0    
351                                   0 0x00010000    
352                 };                                
353         };                                        
354                                                   
355         pci3: pcie@ffe270000 {                    
356                 reg = <0xf 0xfe270000 0 0x1000    
357                 ranges = <0x02000000 0 0xe0000    
358                           0x01000000 0 0x00000    
359                 pcie@0 {                          
360                         ranges = <0x02000000 0    
361                                   0x02000000 0    
362                                   0 0x10000000    
363                                                   
364                                   0x01000000 0    
365                                   0x01000000 0    
366                                   0 0x00010000    
367                 };                                
368         };                                        
369                                                   
370         qe: qe@ffe140000 {                        
371                 ranges = <0x0 0xf 0xfe140000 0    
372                 reg = <0xf 0xfe140000 0 0x480>    
373                 brg-frequency = <0>;              
374                 bus-frequency = <0>;              
375                                                   
376                 si1: si@700 {                     
377                         compatible = "fsl,t104    
378                         reg = <0x700 0x80>;       
379                 };                                
380                                                   
381                 siram1: siram@1000 {              
382                         compatible = "fsl,t104    
383                         reg = <0x1000 0x800>;     
384                 };                                
385                                                   
386                 ucc_hdlc: ucc@2000 {              
387                         compatible = "fsl,ucc-    
388                         rx-clock-name = "clk8"    
389                         tx-clock-name = "clk9"    
390                         fsl,rx-sync-clock = "r    
391                         fsl,tx-sync-clock = "t    
392                         fsl,tx-timeslot-mask =    
393                         fsl,rx-timeslot-mask =    
394                         fsl,tdm-framer-type =     
395                         fsl,tdm-id = <0>;         
396                         fsl,siram-entry-id = <    
397                         fsl,tdm-interface;        
398                 };                                
399                                                   
400                 ucc_serial: ucc@2200 {            
401                         compatible = "fsl,t104    
402                         port-number = <0>;        
403                         rx-clock-name = "brg2"    
404                         tx-clock-name = "brg2"    
405                 };                                
406         };                                        
407 };                                                
                                                      

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