1 /*
2 * T2080QDS Device Tree Source
3 *
4 * Copyright 2013 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "t208xsi-pre.dtsi"
36 /include/ "t208xqds.dtsi"
37
38 / {
39 model = "fsl,T2080QDS";
40 compatible = "fsl,T2080QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 emi1_slot1 = &t2080mdio2;
47 emi1_slot2 = &t2080mdio3;
48 emi1_slot3 = &t2080mdio4;
49 };
50
51 rio: rapidio@ffe0c0000 {
52 reg = <0xf 0xfe0c0000 0 0x1100
53
54 port1 {
55 ranges = <0 0 0xc 0x20
56 };
57 port2 {
58 ranges = <0 0 0xc 0x30
59 };
60 };
61 };
62
63 &soc {
64 fman@400000 {
65 ethernet@e0000 {
66 phy-handle = <&phy_sgm
67 phy-connection-type =
68 };
69
70 ethernet@e2000 {
71 phy-handle = <&phy_sgm
72 phy-connection-type =
73 };
74
75 ethernet@e4000 {
76 phy-handle = <&rgmii_p
77 phy-connection-type =
78 };
79
80 ethernet@e6000 {
81 phy-handle = <&rgmii_p
82 phy-connection-type =
83 };
84
85 ethernet@e8000 {
86 phy-handle = <&phy_sgm
87 phy-connection-type =
88 };
89
90 ethernet@ea000 {
91 phy-handle = <&phy_sgm
92 phy-connection-type =
93 };
94
95 ethernet@f0000 {
96 phy-handle = <&phy_xau
97 phy-connection-type =
98 };
99
100 ethernet@f2000 {
101 phy-handle = <&phy_sgm
102 phy-connection-type =
103 };
104
105 mdio@fd000 {
106 phy_xaui_slot3: ethern
107 compatible = "
108 reg = <0x3>;
109 };
110 };
111 };
112 };
113
114 &boardctrl {
115 mdio-mux-emi1 {
116 compatible = "mdio-mux-mmioreg
117 mdio-parent-bus = <&mdio0>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x54 1>;
121 mux-mask = <0xe0>;
122
123 t2080mdio0: mdio@0 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <0>;
127
128 rgmii_phy1: ethernet-p
129 reg = <0x1>;
130 };
131 };
132
133 t2080mdio1: mdio@20 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 reg = <0x20>;
137
138 rgmii_phy2: ethernet-p
139 reg = <0x2>;
140 };
141 };
142
143 t2080mdio2: mdio@40 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 reg = <0x40>;
147 status = "disabled";
148
149 phy_sgmii_s1_1c: ether
150 reg = <0x1c>;
151 };
152
153 phy_sgmii_s1_1d: ether
154 reg = <0x1d>;
155 };
156
157 phy_sgmii_s1_1e: ether
158 reg = <0x1e>;
159 };
160
161 phy_sgmii_s1_1f: ether
162 reg = <0x1f>;
163 };
164 };
165
166 t2080mdio3: mdio@c0 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg = <0xc0>;
170
171 phy_sgmii_s2_1c: ether
172 reg = <0x1c>;
173 };
174
175 phy_sgmii_s2_1d: ether
176 reg = <0x1d>;
177 };
178
179 phy_sgmii_s2_1e: ether
180 reg = <0x1e>;
181 };
182
183 phy_sgmii_s2_1f: ether
184 reg = <0x1f>;
185 };
186 };
187
188 t2080mdio4: mdio@60 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 reg = <0x60>;
192 status = "disabled";
193
194 phy_sgmii_s3_1c: ether
195 reg = <0x1c>;
196 };
197
198 phy_sgmii_s3_1d: ether
199 reg = <0x1d>;
200 };
201
202 phy_sgmii_s3_1e: ether
203 reg = <0x1e>;
204 };
205
206 phy_sgmii_s3_1f: ether
207 reg = <0x1f>;
208 };
209 };
210 };
211 };
212
213 /include/ "t2080si-post.dtsi"
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