1 /*
2 * T2080PCIe-RDB Board Device Tree Source
3 *
4 * Copyright 2014 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "t208xsi-pre.dtsi"
36 /include/ "t208xrdb.dtsi"
37
38 / {
39 model = "fsl,T2080RDB";
40 compatible = "fsl,T2080RDB";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 rio: rapidio@ffe0c0000 {
46 reg = <0xf 0xfe0c0000 0 0x1100
47
48 port1 {
49 ranges = <0 0 0xc 0x20
50 };
51 port2 {
52 ranges = <0 0 0xc 0x30
53 };
54 };
55 };
56
57 &soc {
58 fman@400000 {
59 ethernet@e0000 {
60 phy-handle = <&xg_aq12
61 phy-connection-type =
62 };
63
64 ethernet@e2000 {
65 phy-handle = <&xg_aq12
66 phy-connection-type =
67 };
68
69 ethernet@e4000 {
70 phy-handle = <&rgmii_p
71 phy-connection-type =
72 };
73
74 ethernet@e6000 {
75 phy-handle = <&rgmii_p
76 phy-connection-type =
77 };
78
79 ethernet@f0000 {
80 phy-handle = <&xg_cs43
81 phy-connection-type =
82 };
83
84 ethernet@f2000 {
85 phy-handle = <&xg_cs43
86 phy-connection-type =
87 };
88
89 mdio@fc000 {
90 rgmii_phy1: ethernet-p
91 reg = <0x1>;
92 };
93 rgmii_phy2: ethernet-p
94 reg = <0x2>;
95 };
96 };
97
98 mdio@fd000 {
99 xg_cs4315_phy1: ethern
100 compatible = "
101 reg = <0xc>;
102 };
103
104 xg_cs4315_phy2: ethern
105 compatible = "
106 reg = <0xd>;
107 };
108
109 xg_aq1202_phy3: ethern
110 compatible = "
111 reg = <0x0>;
112 };
113
114 xg_aq1202_phy4: ethern
115 compatible = "
116 reg = <0x1>;
117 };
118 };
119 };
120 };
121
122 /include/ "t2080si-post.dtsi"
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