1 /*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008-2010 DENX Software Engineeri<
5 *
6 * This file is licensed under the terms of th
7 * License version 2. This program is license
8 * any warranty of any kind, whether express o
9 */
10
11 /dts-v1/;
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,glacier";
17 compatible = "amcc,glacier";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 ethernet2 = &EMAC2;
24 ethernet3 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 model = "PowerPC,460GT
36 reg = <0x00000000>;
37 clock-frequency = <0>;
38 timebase-frequency = <
39 i-cache-line-size = <3
40 d-cache-line-size = <3
41 i-cache-size = <32768>
42 d-cache-size = <32768>
43 dcr-controller;
44 dcr-access-method = "n
45 next-level-cache = <&L
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x00000000 0
52 };
53
54 UIC0: interrupt-controller0 {
55 compatible = "ibm,uic-460gt","
56 interrupt-controller;
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
62 };
63
64 UIC1: interrupt-controller1 {
65 compatible = "ibm,uic-460gt","
66 interrupt-controller;
67 cell-index = <1>;
68 dcr-reg = <0x0d0 0x009>;
69 #address-cells = <0>;
70 #size-cells = <0>;
71 #interrupt-cells = <2>;
72 interrupts = <0x1e 0x4 0x1f 0x
73 interrupt-parent = <&UIC0>;
74 };
75
76 UIC2: interrupt-controller2 {
77 compatible = "ibm,uic-460gt","
78 interrupt-controller;
79 cell-index = <2>;
80 dcr-reg = <0x0e0 0x009>;
81 #address-cells = <0>;
82 #size-cells = <0>;
83 #interrupt-cells = <2>;
84 interrupts = <0xa 0x4 0xb 0x4>
85 interrupt-parent = <&UIC0>;
86 };
87
88 UIC3: interrupt-controller3 {
89 compatible = "ibm,uic-460gt","
90 interrupt-controller;
91 cell-index = <3>;
92 dcr-reg = <0x0f0 0x009>;
93 #address-cells = <0>;
94 #size-cells = <0>;
95 #interrupt-cells = <2>;
96 interrupts = <0x10 0x4 0x11 0x
97 interrupt-parent = <&UIC0>;
98 };
99
100 SDR0: sdr {
101 compatible = "ibm,sdr-460gt";
102 dcr-reg = <0x00e 0x002>;
103 };
104
105 CPR0: cpr {
106 compatible = "ibm,cpr-460gt";
107 dcr-reg = <0x00c 0x002>;
108 };
109
110 L2C0: l2c {
111 compatible = "ibm,l2-cache-460
112 dcr-reg = <0x020 0x008
113 0x030 0x008>;
114 cache-line-size = <32>;
115 cache-size = <262144>;
116 interrupt-parent = <&UIC1>;
117 interrupts = <11 1>;
118 };
119
120 plb {
121 compatible = "ibm,plb-460gt",
122 #address-cells = <2>;
123 #size-cells = <1>;
124 ranges;
125 clock-frequency = <0>; /* Fill
126
127 SDRAM0: sdram {
128 compatible = "ibm,sdra
129 dcr-reg = <0x010 0x002
130 };
131
132 CRYPTO: crypto@180000 {
133 compatible = "amcc,ppc
134 "amcc,ppc4xx-c
135 reg = <4 0x00180000 0x
136 interrupt-parent = <&U
137 interrupts = <0x1d 0x4
138 };
139
140 HWRNG: hwrng@110000 {
141 compatible = "amcc,ppc
142 reg = <4 0x00110000 0x
143 };
144
145 MAL0: mcmal {
146 compatible = "ibm,mcma
147 dcr-reg = <0x180 0x062
148 num-tx-chans = <4>;
149 num-rx-chans = <32>;
150 #address-cells = <0>;
151 #size-cells = <0>;
152 interrupt-parent = <&U
153 interrupts = < /*TXEO
154 /*RXEO
155 /*SERR
156 /*TXDE
157 /*RXDE
158 desc-base-addr-high =
159 };
160
161 POB0: opb {
162 compatible = "ibm,opb-
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0xb0000000 0
166 clock-frequency = <0>;
167
168 EBC0: ebc {
169 compatible = "
170 dcr-reg = <0x0
171 #address-cells
172 #size-cells =
173 clock-frequenc
174 /* ranges prop
175 interrupts = <
176 interrupt-pare
177
178 nor_flash@0,0
179 compat
180 bank-w
181 reg =
182 #addre
183 #size-
184 partit
185
186
187 };
188 partit
189
190
191 };
192 partit
193
194
195 };
196 partit
197
198
199 };
200 partit
201
202
203 };
204 partit
205
206
207 };
208 partit
209
210
211 };
212 };
213
214 ndfc@3,0 {
215 compat
216 reg =
217 ccr =
218 bank-s
219 #addre
220 #size-
221
222 nand {
223
224
225
226
227
228
229
230
231
232
233
234 };
235 };
236 };
237
238 UART0: serial@ef600300
239 device_type =
240 compatible = "
241 reg = <0xef600
242 virtual-reg =
243 clock-frequenc
244 current-speed
245 interrupt-pare
246 interrupts = <
247 };
248
249 UART1: serial@ef600400
250 device_type =
251 compatible = "
252 reg = <0xef600
253 virtual-reg =
254 clock-frequenc
255 current-speed
256 interrupt-pare
257 interrupts = <
258 };
259
260 UART2: serial@ef600500
261 device_type =
262 compatible = "
263 reg = <0xef600
264 virtual-reg =
265 clock-frequenc
266 current-speed
267 interrupt-pare
268 interrupts = <
269 };
270
271 UART3: serial@ef600600
272 device_type =
273 compatible = "
274 reg = <0xef600
275 virtual-reg =
276 clock-frequenc
277 current-speed
278 interrupt-pare
279 interrupts = <
280 };
281
282 IIC0: i2c@ef600700 {
283 compatible = "
284 reg = <0xef600
285 interrupt-pare
286 interrupts = <
287 #address-cells
288 #size-cells =
289 rtc@68 {
290 compat
291 reg =
292 interr
293 interr
294 };
295 sttm@48 {
296 compat
297 reg =
298 interr
299 interr
300 };
301 };
302
303 IIC1: i2c@ef600800 {
304 compatible = "
305 reg = <0xef600
306 interrupt-pare
307 interrupts = <
308 };
309
310 ZMII0: emac-zmii@ef600
311 compatible = "
312 reg = <0xef600
313 };
314
315 RGMII0: emac-rgmii@ef6
316 compatible = "
317 reg = <0xef601
318 has-mdio;
319 };
320
321 RGMII1: emac-rgmii@ef6
322 compatible = "
323 reg = <0xef601
324 has-mdio;
325 };
326
327 TAH0: emac-tah@ef60135
328 compatible = "
329 reg = <0xef601
330 };
331
332 TAH1: emac-tah@ef60145
333 compatible = "
334 reg = <0xef601
335 };
336
337 EMAC0: ethernet@ef600e
338 device_type =
339 compatible = "
340 interrupt-pare
341 interrupts = <
342 #interrupt-cel
343 #address-cells
344 #size-cells =
345 interrupt-map
346
347 reg = <0xef600
348 local-mac-addr
349 mal-device = <
350 mal-tx-channel
351 mal-rx-channel
352 cell-index = <
353 max-frame-size
354 rx-fifo-size =
355 tx-fifo-size =
356 rx-fifo-size-g
357 phy-mode = "rg
358 phy-map = <0x0
359 rgmii-device =
360 rgmii-channel
361 tah-device = <
362 tah-channel =
363 has-inverted-s
364 has-new-stacr-
365 };
366
367 EMAC1: ethernet@ef600f
368 device_type =
369 compatible = "
370 interrupt-pare
371 interrupts = <
372 #interrupt-cel
373 #address-cells
374 #size-cells =
375 interrupt-map
376
377 reg = <0xef600
378 local-mac-addr
379 mal-device = <
380 mal-tx-channel
381 mal-rx-channel
382 cell-index = <
383 max-frame-size
384 rx-fifo-size =
385 tx-fifo-size =
386 rx-fifo-size-g
387 phy-mode = "rg
388 phy-map = <0x0
389 rgmii-device =
390 rgmii-channel
391 tah-device = <
392 tah-channel =
393 has-inverted-s
394 has-new-stacr-
395 mdio-device =
396 };
397
398 EMAC2: ethernet@ef6011
399 device_type =
400 compatible = "
401 interrupt-pare
402 interrupts = <
403 #interrupt-cel
404 #address-cells
405 #size-cells =
406 interrupt-map
407
408 reg = <0xef601
409 local-mac-addr
410 mal-device = <
411 mal-tx-channel
412 mal-rx-channel
413 cell-index = <
414 max-frame-size
415 rx-fifo-size =
416 tx-fifo-size =
417 rx-fifo-size-g
418 tx-fifo-size-g
419 phy-mode = "rg
420 phy-map = <0x0
421 rgmii-device =
422 rgmii-channel
423 has-inverted-s
424 has-new-stacr-
425 mdio-device =
426 };
427
428 EMAC3: ethernet@ef6012
429 device_type =
430 compatible = "
431 interrupt-pare
432 interrupts = <
433 #interrupt-cel
434 #address-cells
435 #size-cells =
436 interrupt-map
437
438 reg = <0xef601
439 local-mac-addr
440 mal-device = <
441 mal-tx-channel
442 mal-rx-channel
443 cell-index = <
444 max-frame-size
445 rx-fifo-size =
446 tx-fifo-size =
447 rx-fifo-size-g
448 tx-fifo-size-g
449 phy-mode = "rg
450 phy-map = <0x0
451 rgmii-device =
452 rgmii-channel
453 has-inverted-s
454 has-new-stacr-
455 mdio-device =
456 };
457 };
458
459 PCIX0: pci@c0ec00000 {
460 device_type = "pci";
461 #interrupt-cells = <1>
462 #size-cells = <2>;
463 #address-cells = <3>;
464 compatible = "ibm,plb-
465 primary;
466 large-inbound-windows;
467 enable-msi-hole;
468 reg = <0x0000000c 0x0e
469 0x00000000 0x00
470 0x0000000c 0x0e
471 0x0000000c 0x0e
472 0x0000000c 0x0e
473
474 /* Outbound ranges, on
475 * later cannot be cha
476 */
477 ranges = <0x02000000 0
478 0x02000000 0
479 0x01000000 0
480
481 /* Inbound 2GB range s
482 dma-ranges = <0x420000
483
484 /* This drives busses
485 bus-range = <0x0 0x3f>
486
487 /* All PCI interrupts
488 interrupt-map-mask = <
489 interrupt-map = < 0x0
490 };
491
492 PCIE0: pcie@d00000000 {
493 device_type = "pci";
494 #interrupt-cells = <1>
495 #size-cells = <2>;
496 #address-cells = <3>;
497 compatible = "ibm,plb-
498 primary;
499 port = <0x0>; /* port
500 reg = <0x0000000d 0x00
501 0x0000000c 0x08
502 dcr-reg = <0x100 0x020
503 sdr-base = <0x300>;
504
505 /* Outbound ranges, on
506 * later cannot be cha
507 */
508 ranges = <0x02000000 0
509 0x02000000 0
510 0x01000000 0
511
512 /* Inbound 2GB range s
513 dma-ranges = <0x420000
514
515 /* This drives busses
516 bus-range = <0x40 0x7f
517
518 /* Legacy interrupts (
519 * to invert PCIe lega
520 * We are de-swizzling
521 * port of the root co
522 * to avoid putting a
523 * below are basically
524 * The real slot is on
525 */
526 interrupt-map-mask = <
527 interrupt-map = <
528 0x0 0x0 0x0 0x
529 0x0 0x0 0x0 0x
530 0x0 0x0 0x0 0x
531 0x0 0x0 0x0 0x
532 };
533
534 PCIE1: pcie@d20000000 {
535 device_type = "pci";
536 #interrupt-cells = <1>
537 #size-cells = <2>;
538 #address-cells = <3>;
539 compatible = "ibm,plb-
540 primary;
541 port = <0x1>; /* port
542 reg = <0x0000000d 0x20
543 0x0000000c 0x08
544 dcr-reg = <0x120 0x020
545 sdr-base = <0x340>;
546
547 /* Outbound ranges, on
548 * later cannot be cha
549 */
550 ranges = <0x02000000 0
551 0x02000000 0
552 0x01000000 0
553
554 /* Inbound 2GB range s
555 dma-ranges = <0x420000
556
557 /* This drives busses
558 bus-range = <0x80 0xbf
559
560 /* Legacy interrupts (
561 * to invert PCIe lega
562 * We are de-swizzling
563 * port of the root co
564 * to avoid putting a
565 * below are basically
566 * The real slot is on
567 */
568 interrupt-map-mask = <
569 interrupt-map = <
570 0x0 0x0 0x0 0x
571 0x0 0x0 0x0 0x
572 0x0 0x0 0x0 0x
573 0x0 0x0 0x0 0x
574 };
575 };
576 };
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