1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8313E RDB Device Tree Source
4 *
5 * Copyright 2005, 2006, 2007 Freescale Semico
6 */
7
8 /dts-v1/;
9
10 / {
11 model = "MPC8313ERDB";
12 compatible = "MPC8313ERDB", "MPC831xRD
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,8313@0 {
29 device_type = "cpu";
30 reg = <0x0>;
31 d-cache-line-size = <3
32 i-cache-line-size = <3
33 d-cache-size = <16384>
34 i-cache-size = <16384>
35 timebase-frequency = <
36 bus-frequency = <0>;
37 clock-frequency = <0>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x08000000>;
44 };
45
46 localbus@e0005000 {
47 #address-cells = <2>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc8313-elbc
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
52 interrupt-parent = <&ipic>;
53
54 // CS0 and CS1 are swapped whe
55 // booting from nand, but the
56 // addresses are the same.
57 ranges = <0x0 0x0 0xfe000000 0
58 0x1 0x0 0xe2800000 0
59 0x2 0x0 0xf0000000 0
60 0x3 0x0 0xfa000000 0
61
62 flash@0,0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "cfi-flas
66 reg = <0x0 0x0 0x80000
67 bank-width = <2>;
68 device-width = <1>;
69 };
70
71 nand@1,0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "fsl,mpc8
75 "fsl,elbc
76 reg = <0x1 0x0 0x2000>
77
78 u-boot@0 {
79 reg = <0x0 0x1
80 read-only;
81 };
82
83 kernel@100000 {
84 reg = <0x10000
85 };
86
87 fs@400000 {
88 reg = <0x40000
89 };
90 };
91 };
92
93 soc8313@e0000000 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 compatible = "simple-bus";
98 ranges = <0x0 0xe0000000 0x001
99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>;
101
102 wdt@200 {
103 device_type = "watchdo
104 compatible = "mpc83xx_
105 reg = <0x200 0x100>;
106 };
107
108 sleep-nexus {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-b
112 sleep = <&pmc 0x030000
113 ranges;
114
115 i2c@3000 {
116 #address-cells
117 #size-cells =
118 cell-index = <
119 compatible = "
120 reg = <0x3000
121 interrupts = <
122 interrupt-pare
123 dfsrr;
124 rtc@68 {
125 compat
126 reg =
127 };
128 };
129
130 crypto@30000 {
131 compatible = "
132 "
133 reg = <0x30000
134 interrupts = <
135 interrupt-pare
136 fsl,num-channe
137 fsl,channel-fi
138 fsl,exec-units
139 fsl,descriptor
140 };
141 };
142
143 i2c@3100 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 compatible = "fsl-i2c"
148 reg = <0x3100 0x100>;
149 interrupts = <15 0x8>;
150 interrupt-parent = <&i
151 dfsrr;
152 };
153
154 spi@7000 {
155 cell-index = <0>;
156 compatible = "fsl,spi"
157 reg = <0x7000 0x1000>;
158 interrupts = <16 0x8>;
159 interrupt-parent = <&i
160 mode = "cpu";
161 };
162
163 /* phy type (ULPI, UTMI, UTMI_
164 usb@23000 {
165 compatible = "fsl-usb2
166 reg = <0x23000 0x1000>
167 #address-cells = <1>;
168 #size-cells = <0>;
169 interrupt-parent = <&i
170 interrupts = <38 0x8>;
171 phy_type = "utmi_wide"
172 sleep = <&pmc 0x003000
173 };
174
175 ptp_clock@24E00 {
176 compatible = "fsl,etse
177 reg = <0x24E00 0xB0>;
178 interrupts = <12 0x8 1
179 interrupt-parent = < &
180 fsl,tclk-period = <10>
181 fsl,tmr-prsc = <100
182 fsl,tmr-add = <0x9
183 fsl,tmr-fiper1 = <0x3
184 fsl,tmr-fiper2 = <0x0
185 fsl,max-adj = <659
186 };
187
188 enet0: ethernet@24000 {
189 #address-cells = <1>;
190 #size-cells = <1>;
191 sleep = <&pmc 0x200000
192 ranges = <0x0 0x24000
193
194 cell-index = <0>;
195 device_type = "network
196 model = "eTSEC";
197 compatible = "gianfar"
198 reg = <0x24000 0x1000>
199 local-mac-address = [
200 interrupts = <37 0x8 3
201 interrupt-parent = <&i
202 tbi-handle = < &tbi0 >
203 /* Vitesse 7385 isn't
204 fixed-link = <1 1 1000
205 fsl,magic-packet;
206
207 mdio@520 {
208 #address-cells
209 #size-cells =
210 compatible = "
211 reg = <0x520 0
212 phy4: ethernet
213 interr
214 interr
215 reg =
216 };
217 tbi0: tbi-phy@
218 reg =
219 device
220 };
221 };
222 };
223
224 enet1: ethernet@25000 {
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <1>;
228 device_type = "network
229 model = "eTSEC";
230 compatible = "gianfar"
231 reg = <0x25000 0x1000>
232 ranges = <0x0 0x25000
233 local-mac-address = [
234 interrupts = <34 0x8 3
235 interrupt-parent = <&i
236 tbi-handle = < &tbi1 >
237 phy-handle = < &phy4 >
238 sleep = <&pmc 0x100000
239 fsl,magic-packet;
240
241 mdio@520 {
242 #address-cells
243 #size-cells =
244 compatible = "
245 reg = <0x520 0
246
247 tbi1: tbi-phy@
248 reg =
249 device
250 };
251 };
252
253
254 };
255
256 serial0: serial@4500 {
257 cell-index = <0>;
258 device_type = "serial"
259 compatible = "fsl,ns16
260 reg = <0x4500 0x100>;
261 clock-frequency = <0>;
262 interrupts = <9 0x8>;
263 interrupt-parent = <&i
264 };
265
266 serial1: serial@4600 {
267 cell-index = <1>;
268 device_type = "serial"
269 compatible = "fsl,ns16
270 reg = <0x4600 0x100>;
271 clock-frequency = <0>;
272 interrupts = <10 0x8>;
273 interrupt-parent = <&i
274 };
275
276 /* IPIC
277 * interrupts cell = <intr #,
278 * sense values match linux IO
279 * sense == 8: Level, low asse
280 * sense == 2: Edge, high-to-l
281 */
282 ipic: pic@700 {
283 interrupt-controller;
284 #address-cells = <0>;
285 #interrupt-cells = <2>
286 reg = <0x700 0x100>;
287 device_type = "ipic";
288 };
289
290 pmc: power@b00 {
291 compatible = "fsl,mpc8
292 reg = <0xb00 0x100 0xa
293 interrupts = <80 8>;
294 interrupt-parent = <&i
295 fsl,mpc8313-wakeup-tim
296
297 /* Remove this (or cha
298 * a REVA3 or later bo
299 * workarounds listed
300 * manual, or if you a
301 * to a different boar
302 */
303 status = "fail";
304 };
305
306 gtm1: timer@500 {
307 compatible = "fsl,mpc8
308 reg = <0x500 0x100>;
309 interrupts = <90 8 78
310 interrupt-parent = <&i
311 };
312
313 timer@600 {
314 compatible = "fsl,mpc8
315 reg = <0x600 0x100>;
316 interrupts = <91 8 79
317 interrupt-parent = <&i
318 };
319 };
320
321 sleep-nexus {
322 #address-cells = <1>;
323 #size-cells = <1>;
324 compatible = "simple-bus";
325 sleep = <&pmc 0x00010000>;
326 ranges;
327
328 pci0: pci@e0008500 {
329 cell-index = <1>;
330 interrupt-map-mask = <
331 interrupt-map = <
332 /* IDS
333 0x700
334 0x700
335 0x700
336 0x700
337
338 /* IDS
339 0x780
340 0x780
341 0x780
342 0x780
343 interrupt-parent = <&i
344 interrupts = <66 0x8>;
345 bus-range = <0x0 0x0>;
346 ranges = <0x02000000 0
347 0x42000000 0
348 0x01000000 0
349 clock-frequency = <666
350 #interrupt-cells = <1>
351 #size-cells = <2>;
352 #address-cells = <3>;
353 reg = <0xe0008500 0x10
354 0xe0008300 0x8>
355 compatible = "fsl,mpc8
356 device_type = "pci";
357 };
358
359 dma@82a8 {
360 #address-cells = <1>;
361 #size-cells = <1>;
362 compatible = "fsl,mpc8
363 reg = <0xe00082a8 4>;
364 ranges = <0 0xe0008100
365 interrupt-parent = <&i
366 interrupts = <71 8>;
367
368 dma-channel@0 {
369 compatible = "
370 "
371 reg = <0 0x28>
372 interrupt-pare
373 interrupts = <
374 cell-index = <
375 };
376
377 dma-channel@80 {
378 compatible = "
379 "
380 reg = <0x80 0x
381 interrupt-pare
382 interrupts = <
383 cell-index = <
384 };
385
386 dma-channel@100 {
387 compatible = "
388 "
389 reg = <0x100 0
390 interrupt-pare
391 interrupts = <
392 cell-index = <
393 };
394
395 dma-channel@180 {
396 compatible = "
397 "
398 reg = <0x180 0
399 interrupt-pare
400 interrupts = <
401 cell-index = <
402 };
403 };
404 };
405 };
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