1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8360E RDK Device Tree Source
4 *
5 * Copyright 2006 Freescale Semiconductor Inc.
6 * Copyright 2007-2008 MontaVista Software, In
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvist
9 */
10
11 /dts-v1/;
12
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "fsl,mpc8360rdk";
17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 serial2 = &serial2;
22 serial3 = &serial3;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 pci0 = &pci0;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8360@0 {
35 device_type = "cpu";
36 reg = <0>;
37 d-cache-line-size = <3
38 i-cache-line-size = <3
39 d-cache-size = <32768>
40 i-cache-size = <32768>
41 /* filled by u-boot */
42 timebase-frequency = <
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 /* filled by u-boot */
51 reg = <0 0>;
52 };
53
54 soc@e0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 device_type = "soc";
58 compatible = "fsl,mpc8360-immr
59 "simple-bus";
60 ranges = <0 0xe0000000 0x20000
61 reg = <0xe0000000 0x200>;
62 /* filled by u-boot */
63 bus-frequency = <0>;
64
65 wdt@200 {
66 compatible = "mpc83xx_
67 reg = <0x200 0x100>;
68 };
69
70 pmc: power@b00 {
71 compatible = "fsl,mpc8
72 reg = <0xb00 0x100 0xa
73 interrupts = <80 0x8>;
74 interrupt-parent = <&i
75 };
76
77 i2c@3000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c"
82 reg = <0x3000 0x100>;
83 interrupts = <14 8>;
84 interrupt-parent = <&i
85 dfsrr;
86 };
87
88 i2c@3100 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <1>;
92 compatible = "fsl-i2c"
93 reg = <0x3100 0x100>;
94 interrupts = <16 8>;
95 interrupt-parent = <&i
96 dfsrr;
97 };
98
99 serial0: serial@4500 {
100 device_type = "serial"
101 compatible = "fsl,ns16
102 reg = <0x4500 0x100>;
103 interrupts = <9 8>;
104 interrupt-parent = <&i
105 /* filled by u-boot */
106 clock-frequency = <0>;
107 };
108
109 serial1: serial@4600 {
110 device_type = "serial"
111 compatible = "fsl,ns16
112 reg = <0x4600 0x100>;
113 interrupts = <10 8>;
114 interrupt-parent = <&i
115 /* filled by u-boot */
116 clock-frequency = <0>;
117 };
118
119 dma@82a8 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,mpc8
123 reg = <0x82a8 4>;
124 ranges = <0 0x8100 0x1
125 interrupt-parent = <&i
126 interrupts = <71 8>;
127 cell-index = <0>;
128 dma-channel@0 {
129 compatible = "
130 reg = <0 0x80>
131 cell-index = <
132 interrupt-pare
133 interrupts = <
134 };
135 dma-channel@80 {
136 compatible = "
137 reg = <0x80 0x
138 cell-index = <
139 interrupt-pare
140 interrupts = <
141 };
142 dma-channel@100 {
143 compatible = "
144 reg = <0x100 0
145 cell-index = <
146 interrupt-pare
147 interrupts = <
148 };
149 dma-channel@180 {
150 compatible = "
151 reg = <0x180 0
152 cell-index = <
153 interrupt-pare
154 interrupts = <
155 };
156 };
157
158 crypto@30000 {
159 compatible = "fsl,sec2
160 reg = <0x30000 0x10000
161 interrupts = <11 0x8>;
162 interrupt-parent = <&i
163 fsl,num-channels = <4>
164 fsl,channel-fifo-len =
165 fsl,exec-units-mask =
166 fsl,descriptor-types-m
167 sleep = <&pmc 0x030000
168 };
169
170 ipic: interrupt-controller@700
171 #address-cells = <0>;
172 #interrupt-cells = <2>
173 compatible = "fsl,pq2p
174 interrupt-controller;
175 reg = <0x700 0x100>;
176 };
177
178 qe_pio_b: gpio-controller@1418
179 #gpio-cells = <2>;
180 compatible = "fsl,mpc8
181 "fsl,mpc8
182 reg = <0x1418 0x18>;
183 gpio-controller;
184 };
185
186 qe_pio_e: gpio-controller@1460
187 #gpio-cells = <2>;
188 compatible = "fsl,mpc8
189 "fsl,mpc8
190 reg = <0x1460 0x18>;
191 gpio-controller;
192 };
193
194 qe@100000 {
195 #address-cells = <1>;
196 #size-cells = <1>;
197 device_type = "qe";
198 compatible = "fsl,qe",
199 ranges = <0 0x100000 0
200 reg = <0x100000 0x480>
201 /* filled by u-boot */
202 clock-frequency = <0>;
203 bus-frequency = <0>;
204 brg-frequency = <0>;
205 fsl,qe-num-riscs = <2>
206 fsl,qe-num-snums = <28
207
208 muram@10000 {
209 #address-cells
210 #size-cells =
211 compatible = "
212 ranges = <0 0x
213
214 data-only@0 {
215 compat
216
217 reg =
218 };
219 };
220
221 timer@440 {
222 compatible = "
223 "
224 reg = <0x440 0
225 interrupts = <
226 interrupt-pare
227 clock-frequenc
228 };
229
230 usb@6c0 {
231 compatible = "
232 "
233 reg = <0x6c0 0
234 interrupts = <
235 interrupt-pare
236 fsl,fullspeed-
237 gpios = <&qe_p
238 &qe_p
239 &qe_p
240 &qe_p
241 &qe_p
242 &qe_p
243 &qe_p
244 };
245
246 spi@4c0 {
247 cell-index = <
248 compatible = "
249 reg = <0x4c0 0
250 interrupts = <
251 interrupt-pare
252 mode = "cpu-qe
253 };
254
255 spi@500 {
256 cell-index = <
257 compatible = "
258 reg = <0x500 0
259 interrupts = <
260 interrupt-pare
261 mode = "cpu-qe
262 };
263
264 enet0: ucc@2000 {
265 device_type =
266 compatible = "
267 cell-index = <
268 reg = <0x2000
269 interrupts = <
270 interrupt-pare
271 rx-clock-name
272 tx-clock-name
273 phy-handle = <
274 phy-connection
275 /* filled by u
276 local-mac-addr
277 };
278
279 enet1: ucc@3000 {
280 device_type =
281 compatible = "
282 cell-index = <
283 reg = <0x3000
284 interrupts = <
285 interrupt-pare
286 rx-clock-name
287 tx-clock-name
288 phy-handle = <
289 phy-connection
290 /* filled by u
291 local-mac-addr
292 };
293
294 enet2: ucc@2600 {
295 device_type =
296 compatible = "
297 cell-index = <
298 reg = <0x2600
299 interrupts = <
300 interrupt-pare
301 rx-clock-name
302 tx-clock-name
303 phy-handle = <
304 phy-connection
305 /* filled by u
306 local-mac-addr
307 };
308
309 enet3: ucc@3200 {
310 device_type =
311 compatible = "
312 cell-index = <
313 reg = <0x3200
314 interrupts = <
315 interrupt-pare
316 rx-clock-name
317 tx-clock-name
318 phy-handle = <
319 phy-connection
320 /* filled by u
321 local-mac-addr
322 };
323
324 mdio@2120 {
325 #address-cells
326 #size-cells =
327 compatible = "
328 reg = <0x2120
329
330 phy1: ethernet
331 compat
332 reg =
333 };
334
335 phy2: ethernet
336 compat
337 reg =
338 };
339
340 phy3: ethernet
341 compat
342 reg =
343 };
344
345 phy4: ethernet
346 compat
347 reg =
348 };
349 };
350
351 serial2: ucc@2400 {
352 device_type =
353 compatible = "
354 reg = <0x2400
355 cell-index = <
356 port-number =
357 rx-clock-name
358 tx-clock-name
359 interrupts = <
360 interrupt-pare
361 soft-uart;
362 };
363
364 serial3: ucc@3400 {
365 device_type =
366 compatible = "
367 reg = <0x3400
368 cell-index = <
369 port-number =
370 rx-clock-name
371 tx-clock-name
372 interrupts = <
373 interrupt-pare
374 soft-uart;
375 };
376
377 qeic: interrupt-contro
378 #address-cells
379 #interrupt-cel
380 compatible = "
381 interrupt-cont
382 reg = <0x80 0x
383 big-endian;
384 interrupts = <
385 interrupt-pare
386 };
387 };
388 };
389
390 localbus@e0005000 {
391 #address-cells = <2>;
392 #size-cells = <1>;
393 compatible = "fsl,mpc8360-loca
394 "simple-bus";
395 reg = <0xe0005000 0xd8>;
396 ranges = <0 0 0xff800000 0x080
397 1 0 0x60000000 0x000
398 2 0 0x70000000 0x400
399
400 flash@0,0 {
401 compatible = "intel,PC
402 reg = <0 0 0x800000>;
403 bank-width = <2>;
404 device-width = <1>;
405 };
406
407 upm@1,0 {
408 compatible = "fsl,upm-
409 reg = <1 0 1>;
410 fsl,upm-addr-offset =
411 fsl,upm-cmd-offset = <
412 gpios = <&qe_pio_e 18
413
414 flash {
415 compatible = "
416 };
417 };
418
419 display@2,0 {
420 device_type = "display
421 compatible = "fujitsu,
422 reg = <2 0 0x4000000>;
423 fujitsu,sh3;
424 little-endian;
425 /* filled by u-boot */
426 address = <0>;
427 depth = <0>;
428 width = <0>;
429 height = <0>;
430 linebytes = <0>;
431 /* linux,opened; - add
432 };
433 };
434
435 pci0: pci@e0008500 {
436 #address-cells = <3>;
437 #size-cells = <2>;
438 #interrupt-cells = <1>;
439 device_type = "pci";
440 compatible = "fsl,mpc8360-pci"
441 reg = <0xe0008500 0x100
442 0xe0008300 0x8>;
443 ranges = <0x02000000 0 0x90000
444 0x42000000 0 0x80000
445 0x01000000 0 0xe0300
446 interrupts = <66 8>;
447 interrupt-parent = <&ipic>;
448 interrupt-map-mask = <0xf800 0
449 interrupt-map = </* miniPCI0 I
450 0xa000 0 0 1
451 0xa000 0 0 2
452
453 /* PCI1 IDSEL
454 0xa800 0 0 1
455 0xa800 0 0 2
456 0xa800 0 0 3
457 0xa800 0 0 4
458 sleep = <&pmc 0x00010000>;
459 /* filled by u-boot */
460 bus-range = <0 0>;
461 clock-frequency = <0>;
462 };
463 };
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