1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8379E RDB Device Tree Source
4 *
5 * Copyright 2007, 2008 Freescale Semiconducto
6 */
7
8 /dts-v1/;
9
10 / {
11 compatible = "fsl,mpc8379rdb";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 ethernet0 = &enet0;
17 ethernet1 = &enet1;
18 serial0 = &serial0;
19 serial1 = &serial1;
20 pci0 = &pci0;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,8379@0 {
28 device_type = "cpu";
29 reg = <0x0>;
30 d-cache-line-size = <3
31 i-cache-line-size = <3
32 d-cache-size = <32768>
33 i-cache-size = <32768>
34 timebase-frequency = <
35 bus-frequency = <0>;
36 clock-frequency = <0>;
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x10000000>;
43 };
44
45 localbus@e0005000 {
46 #address-cells = <2>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc8379-elbc
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
51 interrupt-parent = <&ipic>;
52
53 // CS0 and CS1 are swapped whe
54 // booting from nand, but the
55 // addresses are the same.
56 ranges = <0x0 0x0 0xfe000000 0
57 0x1 0x0 0xe0600000 0
58 0x2 0x0 0xf0000000 0
59 0x3 0x0 0xfa000000 0
60
61 flash@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flas
65 reg = <0x0 0x0 0x80000
66 bank-width = <2>;
67 device-width = <1>;
68 };
69
70 nand@1,0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8
74 "fsl,elbc
75 reg = <0x1 0x0 0x8000>
76
77 u-boot@0 {
78 reg = <0x0 0x1
79 read-only;
80 };
81
82 kernel@100000 {
83 reg = <0x10000
84 };
85 fs@400000 {
86 reg = <0x40000
87 };
88 };
89 };
90
91 immr@e0000000 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 device_type = "soc";
95 compatible = "simple-bus";
96 ranges = <0x0 0xe0000000 0x001
97 reg = <0xe0000000 0x00000200>;
98 bus-frequency = <0>;
99
100 wdt@200 {
101 device_type = "watchdo
102 compatible = "mpc83xx_
103 reg = <0x200 0x100>;
104 };
105
106 gpio1: gpio-controller@c00 {
107 #gpio-cells = <2>;
108 compatible = "fsl,mpc8
109 reg = <0xc00 0x100>;
110 interrupts = <74 0x8>;
111 interrupt-parent = <&i
112 gpio-controller;
113 };
114
115 gpio2: gpio-controller@d00 {
116 #gpio-cells = <2>;
117 compatible = "fsl,mpc8
118 reg = <0xd00 0x100>;
119 interrupts = <75 0x8>;
120 interrupt-parent = <&i
121 gpio-controller;
122 };
123
124 sleep-nexus {
125 #address-cells = <1>;
126 #size-cells = <1>;
127 compatible = "simple-b
128 sleep = <&pmc 0x0c0000
129 ranges;
130
131 i2c@3000 {
132 #address-cells
133 #size-cells =
134 cell-index = <
135 compatible = "
136 reg = <0x3000
137 interrupts = <
138 interrupt-pare
139 dfsrr;
140
141 dtt@48 {
142 compat
143 reg =
144 };
145
146 at24@50 {
147 compat
148 reg =
149 };
150
151 rtc@68 {
152 compat
153 reg =
154 };
155
156 mcu_pio: mcu@a
157 #gpio-
158 compat
159
160 reg =
161 gpio-c
162 };
163 };
164
165 sdhci@2e000 {
166 compatible = "
167 reg = <0x2e000
168 interrupts = <
169 interrupt-pare
170 sdhci,wp-inver
171 /* Filled in b
172 clock-frequenc
173 };
174 };
175
176 i2c@3100 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 cell-index = <1>;
180 compatible = "fsl-i2c"
181 reg = <0x3100 0x100>;
182 interrupts = <15 0x8>;
183 interrupt-parent = <&i
184 dfsrr;
185 };
186
187 spi@7000 {
188 cell-index = <0>;
189 compatible = "fsl,spi"
190 reg = <0x7000 0x1000>;
191 interrupts = <16 0x8>;
192 interrupt-parent = <&i
193 mode = "cpu";
194 };
195
196 dma@82a8 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 compatible = "fsl,mpc8
200 reg = <0x82a8 4>;
201 ranges = <0 0x8100 0x1
202 interrupt-parent = <&i
203 interrupts = <71 8>;
204 cell-index = <0>;
205 dma-channel@0 {
206 compatible = "
207 reg = <0 0x80>
208 cell-index = <
209 interrupt-pare
210 interrupts = <
211 };
212 dma-channel@80 {
213 compatible = "
214 reg = <0x80 0x
215 cell-index = <
216 interrupt-pare
217 interrupts = <
218 };
219 dma-channel@100 {
220 compatible = "
221 reg = <0x100 0
222 cell-index = <
223 interrupt-pare
224 interrupts = <
225 };
226 dma-channel@180 {
227 compatible = "
228 reg = <0x180 0
229 cell-index = <
230 interrupt-pare
231 interrupts = <
232 };
233 };
234
235 usb@23000 {
236 compatible = "fsl-usb2
237 reg = <0x23000 0x1000>
238 #address-cells = <1>;
239 #size-cells = <0>;
240 interrupt-parent = <&i
241 interrupts = <38 0x8>;
242 phy_type = "ulpi";
243 sleep = <&pmc 0x00c000
244 };
245
246 enet0: ethernet@24000 {
247 #address-cells = <1>;
248 #size-cells = <1>;
249 cell-index = <0>;
250 device_type = "network
251 model = "eTSEC";
252 compatible = "gianfar"
253 reg = <0x24000 0x1000>
254 ranges = <0x0 0x24000
255 local-mac-address = [
256 interrupts = <32 0x8 3
257 phy-connection-type =
258 interrupt-parent = <&i
259 tbi-handle = <&tbi0>;
260 phy-handle = <&phy2>;
261 sleep = <&pmc 0xc00000
262 fsl,magic-packet;
263
264 mdio@520 {
265 #address-cells
266 #size-cells =
267 compatible = "
268 reg = <0x520 0
269
270 phy2: ethernet
271 interr
272 interr
273 reg =
274 };
275
276 tbi0: tbi-phy@
277 reg =
278 device
279 };
280 };
281 };
282
283 enet1: ethernet@25000 {
284 #address-cells = <1>;
285 #size-cells = <1>;
286 cell-index = <1>;
287 device_type = "network
288 model = "eTSEC";
289 compatible = "gianfar"
290 reg = <0x25000 0x1000>
291 ranges = <0x0 0x25000
292 local-mac-address = [
293 interrupts = <35 0x8 3
294 phy-connection-type =
295 interrupt-parent = <&i
296 fixed-link = <1 1 1000
297 tbi-handle = <&tbi1>;
298 sleep = <&pmc 0x300000
299 fsl,magic-packet;
300
301 mdio@520 {
302 #address-cells
303 #size-cells =
304 compatible = "
305 reg = <0x520 0
306
307 tbi1: tbi-phy@
308 reg =
309 device
310 };
311 };
312 };
313
314 serial0: serial@4500 {
315 cell-index = <0>;
316 device_type = "serial"
317 compatible = "fsl,ns16
318 reg = <0x4500 0x100>;
319 clock-frequency = <0>;
320 interrupts = <9 0x8>;
321 interrupt-parent = <&i
322 };
323
324 serial1: serial@4600 {
325 cell-index = <1>;
326 device_type = "serial"
327 compatible = "fsl,ns16
328 reg = <0x4600 0x100>;
329 clock-frequency = <0>;
330 interrupts = <10 0x8>;
331 interrupt-parent = <&i
332 };
333
334 crypto@30000 {
335 compatible = "fsl,sec3
336 "fsl,sec2
337 reg = <0x30000 0x10000
338 interrupts = <11 0x8>;
339 interrupt-parent = <&i
340 fsl,num-channels = <4>
341 fsl,channel-fifo-len =
342 fsl,exec-units-mask =
343 fsl,descriptor-types-m
344 sleep = <&pmc 0x030000
345 };
346
347 sata@18000 {
348 compatible = "fsl,mpc8
349 reg = <0x18000 0x1000>
350 interrupts = <44 0x8>;
351 interrupt-parent = <&i
352 sleep = <&pmc 0x000000
353 };
354
355 sata@19000 {
356 compatible = "fsl,mpc8
357 reg = <0x19000 0x1000>
358 interrupts = <45 0x8>;
359 interrupt-parent = <&i
360 sleep = <&pmc 0x000000
361 };
362
363 sata@1a000 {
364 compatible = "fsl,mpc8
365 reg = <0x1a000 0x1000>
366 interrupts = <46 0x8>;
367 interrupt-parent = <&i
368 sleep = <&pmc 0x000000
369 };
370
371 sata@1b000 {
372 compatible = "fsl,mpc8
373 reg = <0x1b000 0x1000>
374 interrupts = <47 0x8>;
375 interrupt-parent = <&i
376 sleep = <&pmc 0x000000
377 };
378
379 /* IPIC
380 * interrupts cell = <intr #,
381 * sense values match linux IO
382 * sense == 8: Level, low asse
383 * sense == 2: Edge, high-to-l
384 */
385 ipic: interrupt-controller@700
386 compatible = "fsl,ipic
387 interrupt-controller;
388 #address-cells = <0>;
389 #interrupt-cells = <2>
390 reg = <0x700 0x100>;
391 };
392
393 pmc: power@b00 {
394 compatible = "fsl,mpc8
395 reg = <0xb00 0x100 0xa
396 interrupts = <80 0x8>;
397 interrupt-parent = <&i
398 };
399 };
400
401 pci0: pci@e0008500 {
402 interrupt-map-mask = <0xf800 0
403 interrupt-map = <
404 /* IRQ5 = 21 =
405
406 /* IDSEL AD14
407 0x7000 0x0 0x
408
409 /* IDSEL AD15
410 0x7800 0x0 0x
411 0x7800 0x0 0x
412 0x7800 0x0 0x
413
414 /* IDSEL AD28
415 0xE000 0x0 0x
416 0xE000 0x0 0x
417 0xE000 0x0 0x
418 interrupt-parent = <&ipic>;
419 interrupts = <66 0x8>;
420 bus-range = <0x0 0x0>;
421 ranges = <0x02000000 0x0 0x900
422 0x42000000 0x0 0x800
423 0x01000000 0x0 0x000
424 sleep = <&pmc 0x00010000>;
425 clock-frequency = <66666666>;
426 #interrupt-cells = <1>;
427 #size-cells = <2>;
428 #address-cells = <3>;
429 reg = <0xe0008500 0x100
430 0xe0008300 0x8>;
431 compatible = "fsl,mpc8349-pci"
432 device_type = "pci";
433 };
434
435 leds {
436 compatible = "gpio-leds";
437
438 pwr {
439 gpios = <&mcu_pio 0 0>
440 default-state = "on";
441 };
442
443 hdd {
444 gpios = <&mcu_pio 1 0>
445 linux,default-trigger
446 };
447 };
448 };
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