1 /*
2 * Device Tree Source for IBM/AMCC Taishan
3 *
4 * Copyright 2007 IBM Corp.
5 * Hugh Blemings <hugh@au.ibm.com> based off co
6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, Dav
7 *
8 * This file is licensed under the terms of th
9 * License version 2. This program is license
10 * any warranty of any kind, whether express o
11 */
12
13 /dts-v1/;
14
15 / {
16 #address-cells = <2>;
17 #size-cells = <1>;
18 model = "amcc,taishan";
19 compatible = "amcc,taishan";
20 dcr-parent = <&{/cpus/cpu@0}>;
21
22 aliases {
23 ethernet0 = &EMAC2;
24 ethernet1 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 model = "PowerPC,440GX
36 reg = <0x00000000>;
37 clock-frequency = <800
38 timebase-frequency = <
39 i-cache-line-size = <5
40 d-cache-line-size = <5
41 i-cache-size = <32768>
42 d-cache-size = <32768>
43 dcr-controller;
44 dcr-access-method = "n
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000 0
51 };
52
53
54 UICB0: interrupt-controller-base {
55 compatible = "ibm,uic-440gx",
56 interrupt-controller;
57 cell-index = <3>;
58 dcr-reg = <0x200 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
62 };
63
64
65 UIC0: interrupt-controller0 {
66 compatible = "ibm,uic-440gx",
67 interrupt-controller;
68 cell-index = <0>;
69 dcr-reg = <0x0c0 0x009>;
70 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
73 interrupts = <0x1 0x4 0x0 0x4>
74 interrupt-parent = <&UICB0>;
75
76 };
77
78 UIC1: interrupt-controller1 {
79 compatible = "ibm,uic-440gx",
80 interrupt-controller;
81 cell-index = <1>;
82 dcr-reg = <0x0d0 0x009>;
83 #address-cells = <0>;
84 #size-cells = <0>;
85 #interrupt-cells = <2>;
86 interrupts = <0x3 0x4 0x2 0x4>
87 interrupt-parent = <&UICB0>;
88 };
89
90 UIC2: interrupt-controller2 {
91 compatible = "ibm,uic-440gx",
92 interrupt-controller;
93 cell-index = <2>; /* was 1 */
94 dcr-reg = <0x210 0x009>;
95 #address-cells = <0>;
96 #size-cells = <0>;
97 #interrupt-cells = <2>;
98 interrupts = <0x5 0x4 0x4 0x4>
99 interrupt-parent = <&UICB0>;
100 };
101
102
103 CPC0: cpc {
104 compatible = "ibm,cpc-440gp";
105 dcr-reg = <0x0b0 0x003 0x0e0 0
106 // FIXME: anything else?
107 };
108
109 L2C0: l2c {
110 compatible = "ibm,l2-cache-440
111 dcr-reg = <0x020 0x008
112 0x030 0x008>;
113 cache-line-size = <32>;
114 cache-size = <262144>;
115 interrupt-parent = <&UIC2>;
116 interrupts = <0x17 0x1>;
117 };
118
119 plb {
120 compatible = "ibm,plb-440gx",
121 #address-cells = <2>;
122 #size-cells = <1>;
123 ranges;
124 clock-frequency = <160000000>;
125
126 SDRAM0: memory-controller {
127 compatible = "ibm,sdra
128 dcr-reg = <0x010 0x002
129 // FIXME: anything els
130 };
131
132 SRAM0: sram {
133 compatible = "ibm,sram
134 dcr-reg = <0x020 0x008
135 };
136
137 DMA0: dma {
138 // FIXME: ???
139 compatible = "ibm,dma-
140 dcr-reg = <0x100 0x027
141 };
142
143 MAL0: mcmal {
144 compatible = "ibm,mcma
145 dcr-reg = <0x180 0x062
146 num-tx-chans = <4>;
147 num-rx-chans = <4>;
148 interrupt-parent = <&M
149 interrupts = <0x0 0x1
150 #interrupt-cells = <1>
151 #address-cells = <0>;
152 #size-cells = <0>;
153 interrupt-map = </*TXE
154 /*RXE
155 /*SER
156 /*TXD
157 /*RXD
158 interrupt-map-mask = <
159 };
160
161 POB0: opb {
162 compatible = "ibm,opb-
163 #address-cells = <1>;
164 #size-cells = <1>;
165 /* Wish there was a ni
166 range */
167 ranges = <0x00000000 0
168 0x80000000 0
169 dcr-reg = <0x090 0x00b
170 interrupt-parent = <&U
171 interrupts = <0x7 0x4>
172 clock-frequency = <800
173
174
175 EBC0: ebc {
176 compatible = "
177 dcr-reg = <0x0
178 #address-cells
179 #size-cells =
180 clock-frequenc
181
182 /* ranges prop
183 * based on fi
184 * EBC bridge
185
186 interrupts = <
187 interrupt-pare
188
189 nor_flash@0,0
190 compat
191 bank-w
192 device
193 reg =
194 #addre
195 #size-
196 partit
197
198
199 };
200 partit
201
202
203 };
204 partit
205
206
207 };
208 partit
209
210
211 };
212 partit
213
214
215 };
216 };
217 };
218
219
220
221 UART0: serial@40000200
222 device_type =
223 compatible = "
224 reg = <0x40000
225 virtual-reg =
226 clock-frequenc
227 current-speed
228 interrupt-pare
229 interrupts = <
230 };
231
232 UART1: serial@40000300
233 device_type =
234 compatible = "
235 reg = <0x40000
236 virtual-reg =
237 clock-frequenc
238 current-speed
239 interrupt-pare
240 interrupts = <
241 };
242
243 IIC0: i2c@40000400 {
244 /* FIXME */
245 compatible = "
246 reg = <0x40000
247 interrupt-pare
248 interrupts = <
249 };
250 IIC1: i2c@40000500 {
251 /* FIXME */
252 compatible = "
253 reg = <0x40000
254 interrupt-pare
255 interrupts = <
256 };
257
258 GPIO0: gpio@40000700 {
259 /* FIXME */
260 compatible = "
261 reg = <0x40000
262 };
263
264 ZMII0: emac-zmii@40000
265 compatible = "
266 reg = <0x40000
267 };
268
269 RGMII0: emac-rgmii@400
270 compatible = "
271 reg = <0x40000
272 };
273
274 TAH0: emac-tah@40000b5
275 compatible = "
276 reg = <0x40000
277 };
278
279 TAH1: emac-tah@40000d5
280 compatible = "
281 reg = <0x40000
282 };
283
284 EMAC0: ethernet@400008
285 unused = <0x1>
286 device_type =
287 compatible = "
288 interrupt-pare
289 interrupts = <
290 reg = <0x40000
291 local-mac-addr
292 mal-device = <
293 mal-tx-channel
294 mal-rx-channel
295 cell-index = <
296 max-frame-size
297 rx-fifo-size =
298 tx-fifo-size =
299 phy-mode = "rm
300 phy-map = <0x0
301 zmii-device =
302 zmii-channel =
303 };
304 EMAC1: ethernet@400009
305 unused = <0x1>
306 device_type =
307 compatible = "
308 interrupt-pare
309 interrupts = <
310 reg = <0x40000
311 local-mac-addr
312 mal-device = <
313 mal-tx-channel
314 mal-rx-channel
315 cell-index = <
316 max-frame-size
317 rx-fifo-size =
318 tx-fifo-size =
319 phy-mode = "rm
320 phy-map = <0x0
321 zmii-device =
322 zmii-channel =
323 };
324
325 EMAC2: ethernet@40000c
326 device_type =
327 compatible = "
328 interrupt-pare
329 interrupts = <
330 reg = <0x40000
331 local-mac-addr
332 mal-device = <
333 mal-tx-channel
334 mal-rx-channel
335 cell-index = <
336 max-frame-size
337 rx-fifo-size =
338 tx-fifo-size =
339 phy-mode = "rg
340 phy-address =
341 rgmii-device =
342 rgmii-channel
343 zmii-device =
344 zmii-channel =
345 tah-device = <
346 tah-channel =
347 };
348
349 EMAC3: ethernet@40000e
350 device_type =
351 compatible = "
352 interrupt-pare
353 interrupts = <
354 reg = <0x40000
355 local-mac-addr
356 mal-device = <
357 mal-tx-channel
358 mal-rx-channel
359 cell-index = <
360 max-frame-size
361 rx-fifo-size =
362 tx-fifo-size =
363 phy-mode = "rg
364 phy-address =
365 rgmii-device =
366 rgmii-channel
367 zmii-device =
368 zmii-channel =
369 tah-device = <
370 tah-channel =
371 };
372
373
374 GPT0: gpt@40000a00 {
375 /* FIXME */
376 reg = <0x40000
377 interrupt-pare
378 interrupts = <
379 };
380
381 };
382
383 PCIX0: pci@20ec00000 {
384 device_type = "pci";
385 #interrupt-cells = <1>
386 #size-cells = <2>;
387 #address-cells = <3>;
388 compatible = "ibm,plb4
389 primary;
390 large-inbound-windows;
391 enable-msi-hole;
392 reg = <0x00000002 0x0e
393 0x00000000 0x00
394 0x00000002 0x0e
395 0x00000002 0x0e
396 0x00000002 0x0e
397
398 /* Outbound ranges, on
399 * later cannot be cha
400 */
401 ranges = <0x02000000 0
402 0x01000000 0
403
404 /* Inbound 2GB range s
405 dma-ranges = <0x420000
406
407 interrupt-map-mask = <
408 interrupt-map = <
409 /* IDSEL 1 */
410 0x800 0x0 0x0
411 0x800 0x0 0x0
412 0x800 0x0 0x0
413 0x800 0x0 0x0
414
415 /* IDSEL 2 */
416 0x1000 0x0 0x0
417 0x1000 0x0 0x0
418 0x1000 0x0 0x0
419 0x1000 0x0 0x0
420 >;
421 };
422 };
423
424 chosen {
425 stdout-path = "/plb/opb/serial
426 };
427 };
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