1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TQM 8540 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 */
7
8 /dts-v1/;
9
10 /include/ "fsl/e500v1_power_isa.dtsi"
11
12 / {
13 model = "tqc,tqm8540";
14 compatible = "tqc,tqm8540";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8540@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <3
35 i-cache-line-size = <3
36 d-cache-size = <32768>
37 i-cache-size = <32768>
38 timebase-frequency = <
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 next-level-cache = <&L
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x10000000>;
48 };
49
50 soc@e0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 device_type = "soc";
54 ranges = <0x0 0xe0000000 0x100
55 bus-frequency = <0>;
56 compatible = "fsl,mpc8540-immr
57
58 ecm-law@0 {
59 compatible = "fsl,ecm-
60 reg = <0x0 0x1000>;
61 fsl,num-laws = <8>;
62 };
63
64 ecm@1000 {
65 compatible = "fsl,mpc8
66 reg = <0x1000 0x1000>;
67 interrupts = <17 2>;
68 interrupt-parent = <&m
69 };
70
71 memory-controller@2000 {
72 compatible = "fsl,mpc8
73 reg = <0x2000 0x1000>;
74 interrupt-parent = <&m
75 interrupts = <18 2>;
76 };
77
78 L2: l2-cache-controller@20000
79 compatible = "fsl,mpc8
80 reg = <0x20000 0x1000>
81 cache-line-size = <32>
82 cache-size = <0x40000>
83 interrupt-parent = <&m
84 interrupts = <16 2>;
85 };
86
87 i2c@3000 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <0>;
91 compatible = "fsl-i2c"
92 reg = <0x3000 0x100>;
93 interrupts = <43 2>;
94 interrupt-parent = <&m
95 dfsrr;
96
97 dtt@48 {
98 compatible = "
99 reg = <0x48>;
100 };
101
102 rtc@68 {
103 compatible = "
104 reg = <0x68>;
105 };
106 };
107
108 dma@21300 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "fsl,mpc8
112 reg = <0x21300 0x4>;
113 ranges = <0x0 0x21100
114 cell-index = <0>;
115 dma-channel@0 {
116 compatible = "
117
118 reg = <0x0 0x8
119 cell-index = <
120 interrupt-pare
121 interrupts = <
122 };
123 dma-channel@80 {
124 compatible = "
125
126 reg = <0x80 0x
127 cell-index = <
128 interrupt-pare
129 interrupts = <
130 };
131 dma-channel@100 {
132 compatible = "
133
134 reg = <0x100 0
135 cell-index = <
136 interrupt-pare
137 interrupts = <
138 };
139 dma-channel@180 {
140 compatible = "
141
142 reg = <0x180 0
143 cell-index = <
144 interrupt-pare
145 interrupts = <
146 };
147 };
148
149 enet0: ethernet@24000 {
150 #address-cells = <1>;
151 #size-cells = <1>;
152 cell-index = <0>;
153 device_type = "network
154 model = "TSEC";
155 compatible = "gianfar"
156 reg = <0x24000 0x1000>
157 ranges = <0x0 0x24000
158 local-mac-address = [
159 interrupts = <29 2 30
160 interrupt-parent = <&m
161 phy-handle = <&phy2>;
162
163 mdio@520 {
164 #address-cells
165 #size-cells =
166 compatible = "
167 reg = <0x520 0
168
169 phy1: ethernet
170 interr
171 interr
172 reg =
173 };
174 phy2: ethernet
175 interr
176 interr
177 reg =
178 };
179 phy3: ethernet
180 interr
181 interr
182 reg =
183 };
184 tbi0: tbi-phy@
185 reg =
186 device
187 };
188 };
189 };
190
191 enet1: ethernet@25000 {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 cell-index = <1>;
195 device_type = "network
196 model = "TSEC";
197 compatible = "gianfar"
198 reg = <0x25000 0x1000>
199 ranges = <0x0 0x25000
200 local-mac-address = [
201 interrupts = <35 2 36
202 interrupt-parent = <&m
203 phy-handle = <&phy1>;
204
205 mdio@520 {
206 #address-cells
207 #size-cells =
208 compatible = "
209 reg = <0x520 0
210
211 tbi1: tbi-phy@
212 reg =
213 device
214 };
215 };
216 };
217
218 enet2: ethernet@26000 {
219 #address-cells = <1>;
220 #size-cells = <1>;
221 cell-index = <2>;
222 device_type = "network
223 model = "FEC";
224 compatible = "gianfar"
225 reg = <0x26000 0x1000>
226 ranges = <0x0 0x26000
227 local-mac-address = [
228 interrupts = <41 2>;
229 interrupt-parent = <&m
230 phy-handle = <&phy3>;
231
232 mdio@520 {
233 #address-cells
234 #size-cells =
235 compatible = "
236 reg = <0x520 0
237
238 tbi2: tbi-phy@
239 reg =
240 device
241 };
242 };
243 };
244
245 serial0: serial@4500 {
246 cell-index = <0>;
247 device_type = "serial"
248 compatible = "fsl,ns16
249 reg = <0x4500 0x100>;
250 clock-frequency = <0>;
251 interrupts = <42 2>;
252 interrupt-parent = <&m
253 };
254
255 serial1: serial@4600 {
256 cell-index = <1>;
257 device_type = "serial"
258 compatible = "fsl,ns16
259 reg = <0x4600 0x100>;
260 clock-frequency = <0>;
261 interrupts = <42 2>;
262 interrupt-parent = <&m
263 };
264
265 mpic: pic@40000 {
266 interrupt-controller;
267 #address-cells = <0>;
268 #interrupt-cells = <2>
269 reg = <0x40000 0x40000
270 device_type = "open-pi
271 compatible = "chrp,ope
272 };
273 };
274
275 localbus@e0005000 {
276 #address-cells = <2>;
277 #size-cells = <1>;
278 compatible = "fsl,mpc8540-loca
279 "simple-bus";
280 reg = <0xe0005000 0x1000>;
281 interrupt-parent = <&mpic>;
282 interrupts = <19 2>;
283
284 ranges = <0x0 0x0 0xfe000000 0
285
286 nor@0,0 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "cfi-flas
290 reg = <0x0 0x0 0x02000
291 bank-width = <4>;
292 device-width = <2>;
293 partition@0 {
294 label = "kerne
295 reg = <0x00000
296 };
297 partition@180000 {
298 label = "root"
299 reg = <0x00180
300 };
301 partition@1f40000 {
302 label = "env1"
303 reg = <0x01f40
304 };
305 partition@1f80000 {
306 label = "env2"
307 reg = <0x01f80
308 };
309 partition@1fc0000 {
310 label = "u-boo
311 reg = <0x01fc0
312 read-only;
313 };
314 };
315 };
316
317 pci0: pci@e0008000 {
318 #interrupt-cells = <1>;
319 #size-cells = <2>;
320 #address-cells = <3>;
321 compatible = "fsl,mpc8540-pcix
322 device_type = "pci";
323 reg = <0xe0008000 0x1000>;
324 clock-frequency = <66666666>;
325 interrupt-map-mask = <0xf800 0
326 interrupt-map = <
327 /* IDSEL 28 */
328 0xe000 0 0 1
329 0xe000 0 0 2
330 0xe000 0 0 3
331 0xe000 0 0 4
332
333 /* IDSEL 11 */
334 0x5800 0 0 1
335 0x5800 0 0 2
336 >;
337
338 interrupt-parent = <&mpic>;
339 interrupts = <24 2>;
340 bus-range = <0 0>;
341 ranges = <0x02000000 0 0x80000
342 0x01000000 0 0x00000
343 };
344 };
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