1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TQM 8541 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 */
7
8 /dts-v1/;
9
10 /include/ "fsl/e500v1_power_isa.dtsi"
11
12 / {
13 model = "tqc,tqm8541";
14 compatible = "tqc,tqm8541";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 serial0 = &serial0;
22 serial1 = &serial1;
23 pci0 = &pci0;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,8541@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <3
34 i-cache-line-size = <3
35 d-cache-size = <32768>
36 i-cache-size = <32768>
37 timebase-frequency = <
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 next-level-cache = <&L
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x10000000>;
47 };
48
49 soc@e0000000 {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 device_type = "soc";
53 ranges = <0x0 0xe0000000 0x100
54 bus-frequency = <0>;
55 compatible = "fsl,mpc8541-immr
56
57 ecm-law@0 {
58 compatible = "fsl,ecm-
59 reg = <0x0 0x1000>;
60 fsl,num-laws = <8>;
61 };
62
63 ecm@1000 {
64 compatible = "fsl,mpc8
65 reg = <0x1000 0x1000>;
66 interrupts = <17 2>;
67 interrupt-parent = <&m
68 };
69
70 memory-controller@2000 {
71 compatible = "fsl,mpc8
72 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m
74 interrupts = <18 2>;
75 };
76
77 L2: l2-cache-controller@20000
78 compatible = "fsl,mpc8
79 reg = <0x20000 0x1000>
80 cache-line-size = <32>
81 cache-size = <0x40000>
82 interrupt-parent = <&m
83 interrupts = <16 2>;
84 };
85
86 i2c@3000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c"
91 reg = <0x3000 0x100>;
92 interrupts = <43 2>;
93 interrupt-parent = <&m
94 dfsrr;
95
96 dtt@48 {
97 compatible = "
98 reg = <0x48>;
99 };
100
101 rtc@68 {
102 compatible = "
103 reg = <0x68>;
104 };
105 };
106
107 dma@21300 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc8
111 reg = <0x21300 0x4>;
112 ranges = <0x0 0x21100
113 cell-index = <0>;
114 dma-channel@0 {
115 compatible = "
116
117 reg = <0x0 0x8
118 cell-index = <
119 interrupt-pare
120 interrupts = <
121 };
122 dma-channel@80 {
123 compatible = "
124
125 reg = <0x80 0x
126 cell-index = <
127 interrupt-pare
128 interrupts = <
129 };
130 dma-channel@100 {
131 compatible = "
132
133 reg = <0x100 0
134 cell-index = <
135 interrupt-pare
136 interrupts = <
137 };
138 dma-channel@180 {
139 compatible = "
140
141 reg = <0x180 0
142 cell-index = <
143 interrupt-pare
144 interrupts = <
145 };
146 };
147
148 enet0: ethernet@24000 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 cell-index = <0>;
152 device_type = "network
153 model = "TSEC";
154 compatible = "gianfar"
155 reg = <0x24000 0x1000>
156 ranges = <0x0 0x24000
157 local-mac-address = [
158 interrupts = <29 2 30
159 interrupt-parent = <&m
160 tbi-handle = <&tbi0>;
161 phy-handle = <&phy2>;
162
163 mdio@520 {
164 #address-cells
165 #size-cells =
166 compatible = "
167 reg = <0x520 0
168
169 phy1: ethernet
170 interr
171 interr
172 reg =
173 };
174 phy2: ethernet
175 interr
176 interr
177 reg =
178 };
179 phy3: ethernet
180 interr
181 interr
182 reg =
183 };
184 tbi0: tbi-phy@
185 reg =
186 device
187 };
188 };
189 };
190
191 enet1: ethernet@25000 {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 cell-index = <1>;
195 device_type = "network
196 model = "TSEC";
197 compatible = "gianfar"
198 reg = <0x25000 0x1000>
199 ranges = <0x0 0x25000
200 local-mac-address = [
201 interrupts = <35 2 36
202 interrupt-parent = <&m
203 tbi-handle = <&tbi1>;
204 phy-handle = <&phy1>;
205
206 mdio@520 {
207 #address-cells
208 #size-cells =
209 compatible = "
210 reg = <0x520 0
211
212 tbi1: tbi-phy@
213 reg =
214 device
215 };
216 };
217 };
218
219 serial0: serial@4500 {
220 cell-index = <0>;
221 device_type = "serial"
222 compatible = "fsl,ns16
223 reg = <0x4500 0x100>;
224 clock-frequency = <0>;
225 interrupts = <42 2>;
226 interrupt-parent = <&m
227 };
228
229 serial1: serial@4600 {
230 cell-index = <1>;
231 device_type = "serial"
232 compatible = "fsl,ns16
233 reg = <0x4600 0x100>;
234 clock-frequency = <0>;
235 interrupts = <42 2>;
236 interrupt-parent = <&m
237 };
238
239 crypto@30000 {
240 compatible = "fsl,sec2
241 reg = <0x30000 0x10000
242 interrupts = <45 2>;
243 interrupt-parent = <&m
244 fsl,num-channels = <4>
245 fsl,channel-fifo-len =
246 fsl,exec-units-mask =
247 fsl,descriptor-types-m
248 };
249
250 mpic: pic@40000 {
251 interrupt-controller;
252 #address-cells = <0>;
253 #interrupt-cells = <2>
254 reg = <0x40000 0x40000
255 device_type = "open-pi
256 compatible = "chrp,ope
257 };
258
259 cpm@919c0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 compatible = "fsl,mpc8
263 reg = <0x919c0 0x30>;
264 ranges;
265
266 muram@80000 {
267 #address-cells
268 #size-cells =
269 ranges = <0 0x
270
271 data@0 {
272 compat
273 reg =
274 };
275 };
276
277 brg@919f0 {
278 compatible = "
279 "
280 "
281 reg = <0x919f0
282 clock-frequenc
283 };
284
285 cpmpic: pic@90c00 {
286 interrupt-cont
287 #address-cells
288 #interrupt-cel
289 interrupts = <
290 interrupt-pare
291 reg = <0x90c00
292 compatible = "
293 };
294 };
295 };
296
297 pci0: pci@e0008000 {
298 #interrupt-cells = <1>;
299 #size-cells = <2>;
300 #address-cells = <3>;
301 compatible = "fsl,mpc8540-pcix
302 device_type = "pci";
303 reg = <0xe0008000 0x1000>;
304 clock-frequency = <66666666>;
305 interrupt-map-mask = <0xf800 0
306 interrupt-map = <
307 /* IDSEL 28 */
308 0xe000 0 0 1
309 0xe000 0 0 2
310 0xe000 0 0 3
311 0xe000 0 0 4
312
313 /* IDSEL 11 */
314 0x5800 0 0 1
315 0x5800 0 0 2
316 >;
317
318 interrupt-parent = <&mpic>;
319 interrupts = <24 2>;
320 bus-range = <0 0>;
321 ranges = <0x02000000 0 0x80000
322 0x01000000 0 0x00000
323 };
324 };
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