1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TQM 8560 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@grand
7 */
8
9 /dts-v1/;
10
11 /include/ "fsl/e500v1_power_isa.dtsi"
12
13 / {
14 model = "tqc,tqm8560";
15 compatible = "tqc,tqm8560";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8560@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <3
36 i-cache-line-size = <3
37 d-cache-size = <32768>
38 i-cache-size = <32768>
39 timebase-frequency = <
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
50
51 soc@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8560-immr
58
59 ecm-law@0 {
60 compatible = "fsl,ecm-
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&m
70 };
71
72 memory-controller@2000 {
73 compatible = "fsl,mpc8
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&m
76 interrupts = <18 2>;
77 };
78
79 L2: l2-cache-controller@20000
80 compatible = "fsl,mpc8
81 reg = <0x20000 0x1000>
82 cache-line-size = <32>
83 cache-size = <0x40000>
84 interrupt-parent = <&m
85 interrupts = <16 2>;
86 };
87
88 i2c@3000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c"
93 reg = <0x3000 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&m
96 dfsrr;
97
98 dtt@48 {
99 compatible = "
100 reg = <0x48>;
101 };
102
103 rtc@68 {
104 compatible = "
105 reg = <0x68>;
106 };
107 };
108
109 dma@21300 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,mpc8
113 reg = <0x21300 0x4>;
114 ranges = <0x0 0x21100
115 cell-index = <0>;
116 dma-channel@0 {
117 compatible = "
118
119 reg = <0x0 0x8
120 cell-index = <
121 interrupt-pare
122 interrupts = <
123 };
124 dma-channel@80 {
125 compatible = "
126
127 reg = <0x80 0x
128 cell-index = <
129 interrupt-pare
130 interrupts = <
131 };
132 dma-channel@100 {
133 compatible = "
134
135 reg = <0x100 0
136 cell-index = <
137 interrupt-pare
138 interrupts = <
139 };
140 dma-channel@180 {
141 compatible = "
142
143 reg = <0x180 0
144 cell-index = <
145 interrupt-pare
146 interrupts = <
147 };
148 };
149
150 enet0: ethernet@24000 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 cell-index = <0>;
154 device_type = "network
155 model = "TSEC";
156 compatible = "gianfar"
157 reg = <0x24000 0x1000>
158 ranges = <0x0 0x24000
159 local-mac-address = [
160 interrupts = <29 2 30
161 interrupt-parent = <&m
162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>;
164
165 mdio@520 {
166 #address-cells
167 #size-cells =
168 compatible = "
169 reg = <0x520 0
170
171 phy1: ethernet
172 interr
173 interr
174 reg =
175 };
176 phy2: ethernet
177 interr
178 interr
179 reg =
180 };
181 phy3: ethernet
182 interr
183 interr
184 reg =
185 };
186 tbi0: tbi-phy@
187 reg =
188 device
189 };
190 };
191 };
192
193 enet1: ethernet@25000 {
194 #address-cells = <1>;
195 #size-cells = <1>;
196 cell-index = <1>;
197 device_type = "network
198 model = "TSEC";
199 compatible = "gianfar"
200 reg = <0x25000 0x1000>
201 ranges = <0x0 0x25000
202 local-mac-address = [
203 interrupts = <35 2 36
204 interrupt-parent = <&m
205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>;
207
208 mdio@520 {
209 #address-cells
210 #size-cells =
211 compatible = "
212 reg = <0x520 0
213
214 tbi1: tbi-phy@
215 reg =
216 device
217 };
218 };
219 };
220
221 mpic: pic@40000 {
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>
225 reg = <0x40000 0x40000
226 device_type = "open-pi
227 compatible = "chrp,ope
228 };
229
230 cpm@919c0 {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 compatible = "fsl,mpc8
234 reg = <0x919c0 0x30>;
235 ranges;
236
237 muram@80000 {
238 #address-cells
239 #size-cells =
240 ranges = <0 0x
241
242 data@0 {
243 compat
244 reg =
245 };
246 };
247
248 brg@919f0 {
249 compatible = "
250 "
251 "
252 reg = <0x919f0
253 clock-frequenc
254 };
255
256 cpmpic: pic@90c00 {
257 interrupt-cont
258 #address-cells
259 #interrupt-cel
260 interrupts = <
261 interrupt-pare
262 reg = <0x90c00
263 compatible = "
264 };
265
266 serial0: serial@91a00
267 device_type =
268 compatible = "
269 "
270 reg = <0x91a00
271 fsl,cpm-brg =
272 fsl,cpm-comman
273 current-speed
274 interrupts = <
275 interrupt-pare
276 };
277
278 serial1: serial@91a20
279 device_type =
280 compatible = "
281 "
282 reg = <0x91a20
283 fsl,cpm-brg =
284 fsl,cpm-comman
285 current-speed
286 interrupts = <
287 interrupt-pare
288 };
289
290 enet2: ethernet@91340
291 device_type =
292 compatible = "
293 "
294 reg = <0x91340
295 local-mac-addr
296 fsl,cpm-comman
297 interrupts = <
298 interrupt-pare
299 phy-handle = <
300 };
301 };
302 };
303
304 localbus@e0005000 {
305 compatible = "fsl,mpc8560-loca
306 "simple-bus";
307 #address-cells = <2>;
308 #size-cells = <1>;
309 reg = <0xe0005000 0x100>;
310 interrupt-parent = <&mpic>;
311 interrupts = <19 2>;
312
313 ranges = <
314 0 0x0 0xfc000000 0x040
315 1 0x0 0xf8000000 0x080
316 2 0x0 0xe3000000 0x000
317 >;
318
319 flash@1,0 {
320 #address-cells = <1>;
321 #size-cells = <1>;
322 compatible = "cfi-flas
323 reg = <1 0x0 0x8000000
324 bank-width = <4>;
325 device-width = <1>;
326
327 partition@0 {
328 label = "kerne
329 reg = <0x00000
330 };
331 partition@200000 {
332 label = "root"
333 reg = <0x00200
334 };
335 partition@500000 {
336 label = "user"
337 reg = <0x00500
338 };
339 partition@7f00000 {
340 label = "env1"
341 reg = <0x07f00
342 };
343 partition@7f40000 {
344 label = "env2"
345 reg = <0x07f40
346 };
347 partition@7f80000 {
348 label = "u-boo
349 reg = <0x07f80
350 read-only;
351 };
352 };
353
354 /* Note: CAN support needs be
355 can0@2,0 {
356 compatible = "intel,82
357 reg = <2 0x0 0x100>;
358 interrupts = <4 1>;
359 interrupt-parent = <&m
360 };
361
362 can1@2,100 {
363 compatible = "intel,82
364 reg = <2 0x100 0x100>;
365 interrupts = <4 1>;
366 interrupt-parent = <&m
367 };
368 };
369
370 pci0: pci@e0008000 {
371 #interrupt-cells = <1>;
372 #size-cells = <2>;
373 #address-cells = <3>;
374 compatible = "fsl,mpc8540-pcix
375 device_type = "pci";
376 reg = <0xe0008000 0x1000>;
377 clock-frequency = <66666666>;
378 interrupt-map-mask = <0xf800 0
379 interrupt-map = <
380 /* IDSEL 28 */
381 0xe000 0 0 1
382 0xe000 0 0 2
383 0xe000 0 0 3
384 0xe000 0 0 4
385
386 /* IDSEL 11 */
387 0x5800 0 0 1
388 0x5800 0 0 2
389 >;
390
391 interrupt-parent = <&mpic>;
392 interrupts = <24 2>;
393 bus-range = <0 0>;
394 ranges = <0x02000000 0 0x80000
395 0x01000000 0 0x00000
396 };
397 };
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