1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Turris 1.x Device Tree Source
4 *
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http
6 *
7 * Pinout, Schematics and Altium hardware desi
8 * and available at: https://docs.turris.cz/hw
9 */
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
15
16 / {
17 model = "Turris 1.x";
18 compatible = "cznic,turris1x";
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 spi0 = &spi0;
30 };
31
32 memory {
33 device_type = "memory";
34 };
35
36 soc: soc@ffe00000 {
37 ranges = <0x0 0x0 0xffe00000 0
38
39 i2c@3000 {
40 /* PCA9557PW GPIO cont
41 gpio-controller@18 {
42 compatible = "
43 label = "bootc
44 reg = <0x18>;
45 #gpio-cells =
46 gpio-controlle
47 polarity = <0x
48 };
49
50 /* STM32F030R8T6 MCU f
51 power-control@2a {
52 /*
53 * Turris Powe
54 * This firmwa
55 * https://git
56 */
57 reg = <0x2a>;
58 };
59
60 /* DDR3 SPD/EEPROM PSW
61 eeprom@32 {
62 reg = <0x32>;
63 };
64
65 /* SA56004ED temperatu
66 temperature-sensor@4c
67 compatible = "
68 reg = <0x4c>;
69 interrupt-pare
70 interrupts = <
71 <
72 #address-cells
73 #size-cells =
74
75 /* Local tempe
76 channel@0 {
77 reg =
78 label
79 };
80
81 /* Remote temp
82 channel@1 {
83 reg =
84 label
85 };
86 };
87
88 /* DDR3 SPD/EEPROM */
89 eeprom@52 {
90 compatible = "
91 reg = <0x52>;
92 };
93
94 /* MCP79402-I/ST Prote
95 eeprom@57 {
96 reg = <0x57>;
97 };
98
99 /* ATSHA204-TH-DA-T cr
100 crypto@64 {
101 compatible = "
102 reg = <0x64>;
103 };
104
105 /* IDT6V49205BNLGI clo
106 clock-generator@69 {
107 compatible = "
108 reg = <0x69>;
109 };
110
111 /* MCP79402-I/ST RTC *
112 rtc@6f {
113 compatible = "
114 reg = <0x6f>;
115 interrupt-pare
116 interrupts = <
117 };
118 };
119
120 /* SPI on connector P1 */
121 spi0: spi@7000 {
122 };
123
124 gpio: gpio-controller@fc00 {
125 #interrupt-cells = <2>
126 interrupt-controller;
127 };
128
129 /* Connected to SMSC USB2412-D
130 usb@22000 {
131 phy_type = "ulpi";
132 dr_mode = "host";
133 };
134
135 enet0: ethernet@24000 {
136 /* Connected to port 6
137 phy-connection-type =
138
139 fixed-link {
140 speed = <1000>
141 full-duplex;
142 };
143 };
144
145 mdio@24520 {
146 /* KSZ9031RNXCA ethern
147 phy: ethernet-phy@7 {
148 interrupts = <
149 reg = <0x7>;
150 };
151
152 /* QCA8337N-AL3C switc
153 switch@10 {
154 compatible = "
155 interrupts = <
156 reg = <0x10>;
157
158 ports {
159 #addre
160 #size-
161
162 port@0
163
164
165
166
167
168
169
170
171
172 };
173
174 port@1
175
176
177 };
178
179 port@2
180
181
182 };
183
184 port@3
185
186
187 };
188
189 port@4
190
191
192 };
193
194 port@5
195
196
197 };
198
199 port@6
200
201
202
203
204
205
206
207
208
209 };
210 };
211 };
212 };
213
214 ptp_clock@24e00 {
215 fsl,tclk-period = <5>;
216 fsl,tmr-prsc = <200>;
217 fsl,tmr-add = <0xccccc
218 fsl,tmr-fiper1 = <0x3b
219 fsl,tmr-fiper2 = <0x00
220 fsl,max-adj = <2499999
221 };
222
223 enet1: ethernet@25000 {
224 /* Connected to port 0
225 phy-connection-type =
226
227 fixed-link {
228 speed = <1000>
229 full-duplex;
230 };
231 };
232
233 mdio@25520 {
234 status = "disabled";
235 };
236
237 enet2: ethernet@26000 {
238 /* Connected to KSZ903
239 label = "wan";
240 phy-handle = <&phy>;
241 phy-connection-type =
242 };
243
244 mdio@26520 {
245 status = "disabled";
246 };
247
248 sdhc@2e000 {
249 bus-width = <4>;
250 cd-gpios = <&gpio 8 GP
251 };
252 };
253
254 lbc: localbus@ffe05000 {
255 reg = <0 0xffe05000 0 0x1000>;
256
257 ranges = <0x0 0x0 0x0 0xef0000
258 <0x1 0x0 0x0 0xff8000
259 <0x3 0x0 0x0 0xffa000
260
261 /* S29GL128P90TFIR10 NOR */
262 nor@0,0 {
263 compatible = "cfi-flas
264 reg = <0x0 0x0 0x01000
265 bank-width = <2>;
266 device-width = <1>;
267
268 partitions {
269 compatible = "
270 #address-cells
271 #size-cells =
272
273 partition@0 {
274 /* 128
275 reg =
276 label
277 };
278
279 partition@2000
280 /* 1.7
281 reg =
282 label
283 };
284
285 partition@1c00
286 /* 1.5
287 reg =
288 label
289 };
290
291 partition@3400
292 /* 11
293 reg =
294 label
295 };
296
297 partition@e400
298 /* 768
299 reg =
300 label
301 };
302
303 /* free unused
304
305 partition@f200
306 /* 128
307 reg =
308 label
309 };
310
311 partition@f400
312 /* 768
313 reg =
314 label
315 };
316 };
317 };
318
319 /* MT29F2G08ABAEAWP:E NAND */
320 nand@1,0 {
321 compatible = "fsl,p202
322 reg = <0x1 0x0 0x00040
323 nand-ecc-mode = "soft"
324 nand-ecc-algo = "bch";
325
326 partitions {
327 compatible = "
328 #address-cells
329 #size-cells =
330
331 partition@0 {
332 /* 256
333 reg =
334 label
335 };
336 };
337 };
338
339 /* LCMXO1200C-3FTN256C FPGA */
340 cpld@3,0 {
341 /*
342 * Turris CPLD firmwar
343 * is extended version
344 * It is backward comp
345 * and the only extens
346 * Turris CPLD firmwar
347 * https://gitlab.nic.
348 */
349 compatible = "cznic,tu
350 reg = <0x3 0x0 0x30>;
351 #address-cells = <1>;
352 #size-cells = <1>;
353 ranges = <0x0 0x3 0x0
354
355 /* MAX6370KA+T watchdo
356 watchdog@2 {
357 /*
358 * CPLD firmwa
359 * input logic
360 * memory spac
361 * input logic
362 * connected v
363 */
364 compatible = "
365 reg = <0x02 0x
366 gpios = <&gpio
367 };
368
369 reboot@d {
370 /*
371 * CPLD firmwa
372 * watchdog re
373 * autoclear s
374 * and watchdo
375 * succeeding
376 * These bugs
377 * bootloader.
378 * a last reso
379 * do not have
380 *
381 * Reset metho
382 * (the prefer
383 * watchdog ha
384 * syscon-rebo
385 *
386 * So define s
387 * level 64 (b
388 * rstcr shoul
389 * method and
390 * than system
391 */
392 compatible = "
393 reg = <0x0d 0x
394 offset = <0x0d
395 mask = <0x01>;
396 value = <0x01>
397 priority = <64
398 };
399
400 led-controller@13 {
401 /*
402 * LEDs are co
403 * All five LA
404 * and so it i
405 * colors on d
406 */
407 compatible = "
408 reg = <0x13 0x
409 #address-cells
410 #size-cells =
411
412 multi-led@0 {
413 reg =
414 color
415 functi
416 };
417
418 multi-led@1 {
419 reg =
420 color
421 functi
422 functi
423 };
424
425 multi-led@2 {
426 reg =
427 color
428 functi
429 functi
430 };
431
432 multi-led@3 {
433 reg =
434 color
435 functi
436 functi
437 };
438
439 multi-led@4 {
440 reg =
441 color
442 functi
443 functi
444 };
445
446 multi-led@5 {
447 reg =
448 color
449 functi
450 functi
451 };
452
453 multi-led@6 {
454 reg =
455 color
456 functi
457 };
458
459 multi-led@7 {
460 reg =
461 color
462 functi
463 };
464 };
465 };
466 };
467
468 pci2: pcie@ffe08000 {
469 /*
470 * PCIe bus for on-board TUSB7
471 * This xHCI controller is ava
472 * Turris 1.0 boards have noth
473 * so system would see only PC
474 * Complex. TUSB7340RKM xHCI c
475 * channels. Channel 0 is conn
476 * channel 1 (but only USB 2.0
477 * slot 1 (CN5), channels 2 an
478 *
479 * P2020 PCIe Root Port does n
480 * uses 64kB + 8kB of PCIe MEM
481 * So allocate 128kB of PCIe M
482 */
483 reg = <0 0xffe08000 0 0x1000>;
484 ranges = <0x02000000 0x0 0xc00
485 <0x01000000 0x0 0x000
486
487 pcie@0 {
488 ranges;
489 };
490 };
491
492 pci1: pcie@ffe09000 {
493 /* PCIe bus on mPCIe slot 2 (C
494 reg = <0 0xffe09000 0 0x1000>;
495 ranges = <0x02000000 0x0 0xa00
496 <0x01000000 0x0 0x000
497
498 pcie@0 {
499 ranges;
500 };
501 };
502
503 pci0: pcie@ffe0a000 {
504 /*
505 * PCIe bus on mPCIe slot 1 (C
506 * Turris 1.1 boards have in t
507 * pins via channel 1 of TUSB7
508 * additional SIM card slot, b
509 */
510 reg = <0 0xffe0a000 0 0x1000>;
511 ranges = <0x02000000 0x0 0x800
512 <0x01000000 0x0 0x000
513
514 pcie@0 {
515 ranges;
516 };
517 };
518 };
519
520 /include/ "fsl/p2020si-post.dtsi"
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