1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2008 Extreme Engineering Solu
4 * Based on MPC8572DS device tree from Freesca
5 *
6 * XCalibur1501 6U CompactPCI single-board com
7 */
8
9 /dts-v1/;
10 / {
11 model = "xes,xcalibur1501";
12 compatible = "xes,xcalibur1501", "xes,
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 ethernet2 = &enet2;
20 ethernet3 = &enet3;
21 serial0 = &serial0;
22 serial1 = &serial1;
23 pci2 = &pci2;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,8572@0 {
31 device_type = "cpu";
32 reg = <0x0>;
33 d-cache-line-size = <3
34 i-cache-line-size = <3
35 d-cache-size = <0x8000
36 i-cache-size = <0x8000
37 timebase-frequency = <
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 next-level-cache = <&L
41 };
42
43 PowerPC,8572@1 {
44 device_type = "cpu";
45 reg = <0x1>;
46 d-cache-line-size = <3
47 i-cache-line-size = <3
48 d-cache-size = <0x8000
49 i-cache-size = <0x8000
50 timebase-frequency = <
51 bus-frequency = <0>;
52 clock-frequency = <0>;
53 next-level-cache = <&L
54 };
55 };
56
57 memory {
58 device_type = "memory";
59 reg = <0x0 0x0 0x0 0x0>;
60 };
61
62 localbus@ef005000 {
63 #address-cells = <2>;
64 #size-cells = <1>;
65 compatible = "fsl,mpc8572-elbc
66 reg = <0 0xef005000 0 0x1000>;
67 interrupts = <19 2>;
68 interrupt-parent = <&mpic>;
69 /* Local bus region mappings *
70 ranges = <0 0 0 0xf8000000 0x8
71 1 0 0 0xf0000000 0x8
72 2 0 0 0xef800000 0x4
73 3 0 0 0xef840000 0x4
74 4 0 0 0xe9000000 0x1
75
76 nor-boot@0,0 {
77 compatible = "amd,s29g
78 bank-width = <2>;
79 reg = <0 0 0x8000000>;
80 #address-cells = <1>;
81 #size-cells = <1>;
82 partition@0 {
83 label = "Prima
84 reg = <0x00000
85 };
86 partition@6f00000 {
87 label = "Prima
88 reg = <0x6f000
89 };
90 partition@7f00000 {
91 label = "Prima
92 reg = <0x7f000
93 };
94 partition@7f40000 {
95 label = "Prima
96 reg = <0x7f400
97 };
98 partition@7f80000 {
99 label = "Prima
100 reg = <0x7f800
101 read-only;
102 };
103 };
104
105 nor-alternate@1,0 {
106 compatible = "amd,s29g
107 bank-width = <2>;
108 //reg = <0xf0000000 0x
109 reg = <1 0 0x8000000>;
110 #address-cells = <1>;
111 #size-cells = <1>;
112 partition@0 {
113 label = "Secon
114 reg = <0x00000
115 };
116 partition@6f00000 {
117 label = "Secon
118 reg = <0x6f000
119 };
120 partition@7f00000 {
121 label = "Secon
122 reg = <0x7f000
123 };
124 partition@7f40000 {
125 label = "Secon
126 reg = <0x7f400
127 };
128 partition@7f80000 {
129 label = "Secon
130 reg = <0x7f800
131 read-only;
132 };
133 };
134
135 nand@2,0 {
136 #address-cells = <1>;
137 #size-cells = <1>;
138 /*
139 * Actual part could b
140 * Micron MT29F8G08DAA
141 * MT29F16G08FAA (2x 1
142 * configuration
143 */
144 compatible = "fsl,mpc8
145 "fsl,elbc
146 reg = <2 0 0x40000>;
147 /* U-Boot should fix t
148 partition@0 {
149 label = "NAND
150 reg = <0 0x400
151 };
152 };
153
154 usb@4,0 {
155 compatible = "nxp,usb-
156 reg = <4 0 0x100000>;
157 bus-width = <32>;
158 interrupt-parent = <&m
159 interrupts = <10 1>;
160 };
161 };
162
163 soc8572@ef000000 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 device_type = "soc";
167 compatible = "fsl,mpc8572-immr
168 ranges = <0x0 0 0xef000000 0x1
169 bus-frequency = <0>;
170
171 ecm-law@0 {
172 compatible = "fsl,ecm-
173 reg = <0x0 0x1000>;
174 fsl,num-laws = <12>;
175 };
176
177 ecm@1000 {
178 compatible = "fsl,mpc8
179 reg = <0x1000 0x1000>;
180 interrupts = <17 2>;
181 interrupt-parent = <&m
182 };
183
184 memory-controller@2000 {
185 compatible = "fsl,mpc8
186 reg = <0x2000 0x1000>;
187 interrupt-parent = <&m
188 interrupts = <18 2>;
189 };
190
191 memory-controller@6000 {
192 compatible = "fsl,mpc8
193 reg = <0x6000 0x1000>;
194 interrupt-parent = <&m
195 interrupts = <18 2>;
196 };
197
198 L2: l2-cache-controller@20000
199 compatible = "fsl,mpc8
200 reg = <0x20000 0x1000>
201 cache-line-size = <32>
202 cache-size = <0x100000
203 interrupt-parent = <&m
204 interrupts = <16 2>;
205 };
206
207 i2c@3000 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 cell-index = <0>;
211 compatible = "fsl-i2c"
212 reg = <0x3000 0x100>;
213 interrupts = <43 2>;
214 interrupt-parent = <&m
215 dfsrr;
216
217 temp-sensor@48 {
218 compatible = "
219 reg = <0x48>;
220 };
221
222 temp-sensor@4c {
223 compatible = "
224 reg = <0x4c>;
225 };
226
227 cpu-supervisor@51 {
228 compatible = "
229 reg = <0x51>;
230 };
231
232 eeprom@54 {
233 compatible = "
234 reg = <0x54>;
235 };
236
237 rtc@68 {
238 compatible = "
239 "
240 reg = <0x68>;
241 };
242
243 pcie-switch@6a {
244 compatible = "
245 reg = <0x6a>;
246 };
247
248 /* On-board signals fo
249 gpio1: gpio@18 {
250 compatible = "
251 reg = <0x18>;
252 #gpio-cells =
253 gpio-controlle
254 polarity = <0x
255 };
256
257 /* PMC0/XMC0 signals *
258 gpio2: gpio@1c {
259 compatible = "
260 reg = <0x1c>;
261 #gpio-cells =
262 gpio-controlle
263 polarity = <0x
264 };
265
266 /* PMC1/XMC1 signals *
267 gpio3: gpio@1d {
268 compatible = "
269 reg = <0x1d>;
270 #gpio-cells =
271 gpio-controlle
272 polarity = <0x
273 };
274
275 /* CompactPCI signals
276 gpio4: gpio@1e {
277 compatible = "
278 reg = <0x1e>;
279 #gpio-cells =
280 gpio-controlle
281 polarity = <0x
282 };
283
284 /* CompactPCI J5 GPIO
285 gpio5: gpio@1f {
286 compatible = "
287 reg = <0x1f>;
288 #gpio-cells =
289 gpio-controlle
290 polarity = <0x
291 };
292 };
293
294 i2c@3100 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 cell-index = <1>;
298 compatible = "fsl-i2c"
299 reg = <0x3100 0x100>;
300 interrupts = <43 2>;
301 interrupt-parent = <&m
302 dfsrr;
303 };
304
305 dma@c300 {
306 #address-cells = <1>;
307 #size-cells = <1>;
308 compatible = "fsl,mpc8
309 reg = <0xc300 0x4>;
310 ranges = <0x0 0xc100 0
311 cell-index = <1>;
312 dma-channel@0 {
313 compatible = "
314
315 reg = <0x0 0x8
316 cell-index = <
317 interrupt-pare
318 interrupts = <
319 };
320 dma-channel@80 {
321 compatible = "
322
323 reg = <0x80 0x
324 cell-index = <
325 interrupt-pare
326 interrupts = <
327 };
328 dma-channel@100 {
329 compatible = "
330
331 reg = <0x100 0
332 cell-index = <
333 interrupt-pare
334 interrupts = <
335 };
336 dma-channel@180 {
337 compatible = "
338
339 reg = <0x180 0
340 cell-index = <
341 interrupt-pare
342 interrupts = <
343 };
344 };
345
346 dma@21300 {
347 #address-cells = <1>;
348 #size-cells = <1>;
349 compatible = "fsl,mpc8
350 reg = <0x21300 0x4>;
351 ranges = <0x0 0x21100
352 cell-index = <0>;
353 dma-channel@0 {
354 compatible = "
355
356 reg = <0x0 0x8
357 cell-index = <
358 interrupt-pare
359 interrupts = <
360 };
361 dma-channel@80 {
362 compatible = "
363
364 reg = <0x80 0x
365 cell-index = <
366 interrupt-pare
367 interrupts = <
368 };
369 dma-channel@100 {
370 compatible = "
371
372 reg = <0x100 0
373 cell-index = <
374 interrupt-pare
375 interrupts = <
376 };
377 dma-channel@180 {
378 compatible = "
379
380 reg = <0x180 0
381 cell-index = <
382 interrupt-pare
383 interrupts = <
384 };
385 };
386
387 /* eTSEC 1 front panel 0 */
388 enet0: ethernet@24000 {
389 #address-cells = <1>;
390 #size-cells = <1>;
391 cell-index = <0>;
392 device_type = "network
393 model = "eTSEC";
394 compatible = "gianfar"
395 reg = <0x24000 0x1000>
396 ranges = <0x0 0x24000
397 local-mac-address = [
398 interrupts = <29 2 30
399 interrupt-parent = <&m
400 tbi-handle = <&tbi0>;
401 phy-handle = <&phy0>;
402 phy-connection-type =
403
404 mdio@520 {
405 #address-cells
406 #size-cells =
407 compatible = "
408 reg = <0x520 0
409
410 phy0: ethernet
411 interr
412 interr
413 reg =
414 };
415 phy1: ethernet
416 interr
417 interr
418 reg =
419 };
420 phy2: ethernet
421 interr
422 interr
423 reg =
424 };
425 phy3: ethernet
426 interr
427 interr
428 reg =
429 };
430 tbi0: tbi-phy@
431 reg =
432 device
433 };
434 };
435 };
436
437 /* eTSEC 2 front panel 1 */
438 enet1: ethernet@25000 {
439 #address-cells = <1>;
440 #size-cells = <1>;
441 cell-index = <1>;
442 device_type = "network
443 model = "eTSEC";
444 compatible = "gianfar"
445 reg = <0x25000 0x1000>
446 ranges = <0x0 0x25000
447 local-mac-address = [
448 interrupts = <35 2 36
449 interrupt-parent = <&m
450 tbi-handle = <&tbi1>;
451 phy-handle = <&phy1>;
452 phy-connection-type =
453
454 mdio@520 {
455 #address-cells
456 #size-cells =
457 compatible = "
458 reg = <0x520 0
459
460 tbi1: tbi-phy@
461 reg =
462 device
463 };
464 };
465 };
466
467 /* eTSEC 3 PICMG2.16 backplane
468 enet2: ethernet@26000 {
469 #address-cells = <1>;
470 #size-cells = <1>;
471 cell-index = <2>;
472 device_type = "network
473 model = "eTSEC";
474 compatible = "gianfar"
475 reg = <0x26000 0x1000>
476 ranges = <0x0 0x26000
477 local-mac-address = [
478 interrupts = <31 2 32
479 interrupt-parent = <&m
480 tbi-handle = <&tbi2>;
481 phy-handle = <&phy2>;
482 phy-connection-type =
483
484 mdio@520 {
485 #address-cells
486 #size-cells =
487 compatible = "
488 reg = <0x520 0
489
490 tbi2: tbi-phy@
491 reg =
492 device
493 };
494 };
495 };
496
497 /* eTSEC 4 PICMG2.16 backplane
498 enet3: ethernet@27000 {
499 #address-cells = <1>;
500 #size-cells = <1>;
501 cell-index = <3>;
502 device_type = "network
503 model = "eTSEC";
504 compatible = "gianfar"
505 reg = <0x27000 0x1000>
506 ranges = <0x0 0x27000
507 local-mac-address = [
508 interrupts = <37 2 38
509 interrupt-parent = <&m
510 tbi-handle = <&tbi3>;
511 phy-handle = <&phy3>;
512 phy-connection-type =
513
514 mdio@520 {
515 #address-cells
516 #size-cells =
517 compatible = "
518 reg = <0x520 0
519
520 tbi3: tbi-phy@
521 reg =
522 device
523 };
524 };
525 };
526
527 /* UART0 */
528 serial0: serial@4500 {
529 cell-index = <0>;
530 device_type = "serial"
531 compatible = "fsl,ns16
532 reg = <0x4500 0x100>;
533 clock-frequency = <0>;
534 interrupts = <42 2>;
535 interrupt-parent = <&m
536 };
537
538 /* UART1 */
539 serial1: serial@4600 {
540 cell-index = <1>;
541 device_type = "serial"
542 compatible = "fsl,ns16
543 reg = <0x4600 0x100>;
544 clock-frequency = <0>;
545 interrupts = <42 2>;
546 interrupt-parent = <&m
547 };
548
549 global-utilities@e0000 {
550 compatible = "fsl,mpc8
551 reg = <0xe0000 0x1000>
552 fsl,has-rstcr;
553 };
554
555 msi@41600 {
556 compatible = "fsl,mpc8
557 reg = <0x41600 0x80>;
558 msi-available-ranges =
559 interrupts = <
560 0xe0 0
561 0xe1 0
562 0xe2 0
563 0xe3 0
564 0xe4 0
565 0xe5 0
566 0xe6 0
567 0xe7 0>;
568 interrupt-parent = <&m
569 };
570
571 crypto@30000 {
572 compatible = "fsl,sec3
573 "fsl,sec2
574 reg = <0x30000 0x10000
575 interrupts = <45 2 58
576 interrupt-parent = <&m
577 fsl,num-channels = <4>
578 fsl,channel-fifo-len =
579 fsl,exec-units-mask =
580 fsl,descriptor-types-m
581 };
582
583 mpic: pic@40000 {
584 interrupt-controller;
585 #address-cells = <0>;
586 #interrupt-cells = <2>
587 reg = <0x40000 0x40000
588 compatible = "chrp,ope
589 device_type = "open-pi
590 };
591
592 gpio0: gpio@f000 {
593 compatible = "fsl,mpc8
594 reg = <0xf000 0x1000>;
595 interrupts = <47 2>;
596 interrupt-parent = <&m
597 #gpio-cells = <2>;
598 gpio-controller;
599 };
600
601 gpio-leds {
602 compatible = "gpio-led
603
604 heartbeat {
605 label = "Heart
606 gpios = <&gpio
607 linux,default-
608 };
609
610 yellow {
611 label = "Yello
612 gpios = <&gpio
613 };
614
615 red {
616 label = "Red";
617 gpios = <&gpio
618 };
619
620 green {
621 label = "Green
622 gpios = <&gpio
623 };
624 };
625
626 /* PME (pattern-matcher) */
627 pme@10000 {
628 compatible = "fsl,mpc8
629 reg = <0x10000 0x5000>
630 interrupts = <57 2 64
631 interrupt-parent = <&m
632 };
633
634 tlu@2f000 {
635 compatible = "fsl,mpc8
636 reg = <0x2f000 0x1000>
637 interrupts = <61 2>;
638 interrupt-parent = <&m
639 };
640
641 tlu@15000 {
642 compatible = "fsl,mpc8
643 reg = <0x15000 0x1000>
644 interrupts = <75 2>;
645 interrupt-parent = <&m
646 };
647 };
648
649 /*
650 * PCI Express controller 3 @ ef008000
651 * This would have been pci0 on other
652 *
653 * PCI Express controller 2 @ ef009000
654 * This would have been pci1 on other
655 */
656
657 /* PCI Express controller 1, wired to
658 pci2: pcie@ef00a000 {
659 compatible = "fsl,mpc8548-pcie
660 device_type = "pci";
661 #interrupt-cells = <1>;
662 #size-cells = <2>;
663 #address-cells = <3>;
664 reg = <0 0xef00a000 0 0x1000>;
665 bus-range = <0 255>;
666 ranges = <0x2000000 0x0 0x8000
667 0x1000000 0x0 0x0000
668 clock-frequency = <33333333>;
669 interrupt-parent = <&mpic>;
670 interrupts = <26 2>;
671 interrupt-map-mask = <0xf800 0
672 interrupt-map = <
673 /* IDSEL 0x0 */
674 0x0 0x0 0x0 0x1 &mpic
675 0x0 0x0 0x0 0x2 &mpic
676 0x0 0x0 0x0 0x3 &mpic
677 0x0 0x0 0x0 0x4 &mpic
678 >;
679 pcie@0 {
680 reg = <0x0 0x0 0x0 0x0
681 #size-cells = <2>;
682 #address-cells = <3>;
683 device_type = "pci";
684 ranges = <0x2000000 0x
685 0x2000000 0x
686 0x0 0x400000
687
688 0x1000000 0x
689 0x1000000 0x
690 0x0 0x100000
691 };
692 };
693 };
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