1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2009 Extreme Engineering Solu
4 * Based on TQM8548 device tree
5 *
6 * XPedite5200 PrPMC/XMC module based on MPC85
7 * xMon boot loader memory map which differs f
8 */
9
10 /dts-v1/;
11
12 / {
13 model = "xes,xpedite5200";
14 compatible = "xes,xpedite5200", "xes,M
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 pci1 = &pci1;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8548@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <3
40 i-cache-line-size = <3
41 d-cache-size = <0x8000
42 i-cache-size = <0x8000
43 next-level-cache = <&L
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x0>; // Fil
50 };
51
52 soc@ef000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 device_type = "soc";
56 ranges = <0x0 0xef000000 0x100
57 bus-frequency = <0>;
58 compatible = "fsl,mpc8548-immr
59
60 ecm-law@0 {
61 compatible = "fsl,ecm-
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <12>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&m
71 };
72
73 memory-controller@2000 {
74 compatible = "fsl,mpc8
75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&m
77 interrupts = <18 2>;
78 };
79
80 L2: l2-cache-controller@20000
81 compatible = "fsl,mpc8
82 reg = <0x20000 0x1000>
83 cache-line-size = <32>
84 cache-size = <0x80000>
85 interrupt-parent = <&m
86 interrupts = <16 2>;
87 };
88
89 /* On-card I2C */
90 i2c@3000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <0>;
94 compatible = "fsl-i2c"
95 reg = <0x3000 0x100>;
96 interrupts = <43 2>;
97 interrupt-parent = <&m
98 dfsrr;
99
100 /*
101 * Board GPIO:
102 * 0: BRD_CFG0 (1
103 * 1: BRD_CFG1 (1
104 * 2: BRD_CFG2 (1
105 * 3: XMC root co
106 * 4: Flash boot
107 * 5: Flash write
108 * 6: PMC monarch
109 * 7: PMC EREADY
110 */
111 gpio1: gpio@18 {
112 compatible = "
113 reg = <0x18>;
114 #gpio-cells =
115 gpio-controlle
116 polarity = <0x
117 };
118
119 /* P14 GPIO */
120 gpio2: gpio@19 {
121 compatible = "
122 reg = <0x19>;
123 #gpio-cells =
124 gpio-controlle
125 polarity = <0x
126 };
127
128 eeprom@50 {
129 compatible = "
130 reg = <0x50>;
131 };
132
133 rtc@68 {
134 compatible = "
135 "
136 reg = <0x68>;
137 };
138
139 dtt@34 {
140 compatible = "
141 reg = <0x34>;
142 };
143 };
144
145 /* Off-card I2C */
146 i2c@3100 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 cell-index = <1>;
150 compatible = "fsl-i2c"
151 reg = <0x3100 0x100>;
152 interrupts = <43 2>;
153 interrupt-parent = <&m
154 dfsrr;
155 };
156
157 dma@21300 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "fsl,mpc8
161 reg = <0x21300 0x4>;
162 ranges = <0x0 0x21100
163 cell-index = <0>;
164 dma-channel@0 {
165 compatible = "
166
167 reg = <0x0 0x8
168 cell-index = <
169 interrupt-pare
170 interrupts = <
171 };
172 dma-channel@80 {
173 compatible = "
174
175 reg = <0x80 0x
176 cell-index = <
177 interrupt-pare
178 interrupts = <
179 };
180 dma-channel@100 {
181 compatible = "
182
183 reg = <0x100 0
184 cell-index = <
185 interrupt-pare
186 interrupts = <
187 };
188 dma-channel@180 {
189 compatible = "
190
191 reg = <0x180 0
192 cell-index = <
193 interrupt-pare
194 interrupts = <
195 };
196 };
197
198 /* eTSEC1: Front panel port 0
199 enet0: ethernet@24000 {
200 #address-cells = <1>;
201 #size-cells = <1>;
202 cell-index = <0>;
203 device_type = "network
204 model = "eTSEC";
205 compatible = "gianfar"
206 reg = <0x24000 0x1000>
207 ranges = <0x0 0x24000
208 local-mac-address = [
209 interrupts = <29 2 30
210 interrupt-parent = <&m
211 tbi-handle = <&tbi0>;
212 phy-handle = <&phy0>;
213
214 mdio@520 {
215 #address-cells
216 #size-cells =
217 compatible = "
218 reg = <0x520 0
219
220 phy0: ethernet
221 interr
222 interr
223 reg =
224 };
225 phy1: ethernet
226 interr
227 interr
228 reg =
229 };
230 phy2: ethernet
231 interr
232 interr
233 reg =
234 };
235 phy3: ethernet
236 interr
237 interr
238 reg =
239 };
240 tbi0: tbi-phy@
241 reg =
242 device
243 };
244 };
245 };
246
247 /* eTSEC2: Front panel port 1
248 enet1: ethernet@25000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <1>;
252 device_type = "network
253 model = "eTSEC";
254 compatible = "gianfar"
255 reg = <0x25000 0x1000>
256 ranges = <0x0 0x25000
257 local-mac-address = [
258 interrupts = <35 2 36
259 interrupt-parent = <&m
260 tbi-handle = <&tbi1>;
261 phy-handle = <&phy1>;
262
263 mdio@520 {
264 #address-cells
265 #size-cells =
266 compatible = "
267 reg = <0x520 0
268
269 tbi1: tbi-phy@
270 reg =
271 device
272 };
273 };
274 };
275
276 /* eTSEC3: Rear panel port 2 *
277 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network
282 model = "eTSEC";
283 compatible = "gianfar"
284 reg = <0x26000 0x1000>
285 ranges = <0x0 0x26000
286 local-mac-address = [
287 interrupts = <31 2 32
288 interrupt-parent = <&m
289 tbi-handle = <&tbi2>;
290 phy-handle = <&phy2>;
291
292 mdio@520 {
293 #address-cells
294 #size-cells =
295 compatible = "
296 reg = <0x520 0
297
298 tbi2: tbi-phy@
299 reg =
300 device
301 };
302 };
303 };
304
305 /* eTSEC4: Rear panel port 3 *
306 enet3: ethernet@27000 {
307 #address-cells = <1>;
308 #size-cells = <1>;
309 cell-index = <3>;
310 device_type = "network
311 model = "eTSEC";
312 compatible = "gianfar"
313 reg = <0x27000 0x1000>
314 ranges = <0x0 0x27000
315 local-mac-address = [
316 interrupts = <37 2 38
317 interrupt-parent = <&m
318 tbi-handle = <&tbi3>;
319 phy-handle = <&phy3>;
320
321 mdio@520 {
322 #address-cells
323 #size-cells =
324 compatible = "
325 reg = <0x520 0
326
327 tbi3: tbi-phy@
328 reg =
329 device
330 };
331 };
332 };
333
334 serial0: serial@4500 {
335 cell-index = <0>;
336 device_type = "serial"
337 compatible = "fsl,ns16
338 reg = <0x4500 0x100>;
339 clock-frequency = <0>;
340 current-speed = <9600>
341 interrupts = <42 2>;
342 interrupt-parent = <&m
343 };
344
345 serial1: serial@4600 {
346 cell-index = <1>;
347 device_type = "serial"
348 compatible = "fsl,ns16
349 reg = <0x4600 0x100>;
350 clock-frequency = <0>;
351 current-speed = <9600>
352 interrupts = <42 2>;
353 interrupt-parent = <&m
354 };
355
356 global-utilities@e0000 {
357 compatible = "fsl,mpc8
358 reg = <0xe0000 0x1000>
359 fsl,has-rstcr;
360 };
361
362 mpic: pic@40000 {
363 interrupt-controller;
364 #address-cells = <0>;
365 #interrupt-cells = <2>
366 reg = <0x40000 0x40000
367 compatible = "chrp,ope
368 device_type = "open-pi
369 };
370 };
371
372 localbus@ef005000 {
373 compatible = "fsl,mpc8548-loca
374 "simple-bus";
375 #address-cells = <2>;
376 #size-cells = <1>;
377 reg = <0xef005000 0x100>;
378 interrupt-parent = <&mpic>;
379 interrupts = <19 2>;
380
381 ranges = <
382 0 0x0 0xf8000000 0x080
383 1 0x0 0xf0000000 0x080
384 2 0x0 0xe8000000 0x000
385 3 0x0 0xe8010000 0x000
386 >;
387
388 nor-boot@0,0 {
389 #address-cells = <1>;
390 #size-cells = <1>;
391 compatible = "cfi-flas
392 reg = <0 0x0 0x4000000
393 bank-width = <2>;
394
395 partition@0 {
396 label = "Prima
397 reg = <0x00000
398 };
399 partition@180000 {
400 label = "Secon
401 reg = <0x00180
402 };
403 partition@300000 {
404 label = "User"
405 reg = <0x00300
406 };
407 partition@3f80000 {
408 label = "Boot
409 reg = <0x03f80
410 };
411 };
412
413 nor-alternate@1,0 {
414 #address-cells = <1>;
415 #size-cells = <1>;
416 compatible = "cfi-flas
417 reg = <1 0x0 0x4000000
418 bank-width = <2>;
419
420 partition@0 {
421 label = "Files
422 reg = <0x00000
423 };
424 partition@3f80000 {
425 label = "Alter
426 reg = <0x03f80
427 };
428 };
429
430 nand@2,0 {
431 #address-cells = <1>;
432 #size-cells = <1>;
433 compatible = "xes,addr
434 reg = <2 0x0 0x10000>;
435 cle-line = <0x8>;
436 ale-line = <0x10>;
437
438 partition@0 {
439 label = "NAND
440 reg = <0 0x400
441 };
442 };
443 };
444
445 /* PMC interface */
446 pci0: pci@ef008000 {
447 #interrupt-cells = <1>;
448 #size-cells = <2>;
449 #address-cells = <3>;
450 compatible = "fsl,mpc8540-pcix
451 device_type = "pci";
452 reg = <0xef008000 0x1000>;
453 clock-frequency = <33333333>;
454 interrupt-map-mask = <0xf800 0
455 interrupt-map = <
456 /* IDSEL */
457 0xe000 0 0 1
458 0xe000 0 0 2
459
460 interrupt-parent = <&mpic>;
461 interrupts = <24 2>;
462 bus-range = <0 0>;
463 ranges = <0x02000000 0 0x80000
464 0x01000000 0 0x00000
465 };
466
467 /* XMC PCIe */
468 pci1: pcie@ef00a000 {
469 interrupt-map-mask = <0xf800 0
470 interrupt-map = <
471 /* IDSEL 0x0 */
472 0x00000 0 0 1 &mpic 0
473 0x00000 0 0 2 &mpic 1
474 0x00000 0 0 3 &mpic 2
475 0x00000 0 0 4 &mpic 3
476
477 interrupt-parent = <&mpic>;
478 interrupts = <26 2>;
479 bus-range = <0 0xff>;
480 ranges = <0x02000000 0 0xa0000
481 0x01000000 0 0x00000
482 clock-frequency = <33333333>;
483 #interrupt-cells = <1>;
484 #size-cells = <2>;
485 #address-cells = <3>;
486 reg = <0xef00a000 0x1000>;
487 compatible = "fsl,mpc8548-pcie
488 device_type = "pci";
489 pcie@0 {
490 reg = <0 0 0 0 0>;
491 #size-cells = <2>;
492 #address-cells = <3>;
493 device_type = "pci";
494 ranges = <0x02000000 0
495 0xc0000000 0
496 0x01000000 0
497 0x00000000 0
498 };
499 };
500
501 /* Needed for dtbImage boot wrapper co
502 chosen {
503 stdout-path = &serial0;
504 };
505 };
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