1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2008 Extreme Engineering Solu
4 * Based on MPC8572DS device tree from Freesca
5 *
6 * XPedite5330 3U CompactPCI module based on M
7 */
8
9 /dts-v1/;
10 / {
11 model = "xes,xpedite5330";
12 compatible = "xes,xpedite5330", "xes,M
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary
17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 serial0 = &serial0;
22 serial1 = &serial1;
23 pci0 = &pci0;
24 pci1 = &pci1;
25 pci2 = &pci2;
26 };
27
28 pmcslots {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 pmcslot@0 {
33 cell-index = <0>;
34 /*
35 * boolean properties
36 * monarch;
37 * module-present;
38 */
39 };
40 };
41
42 xmcslots {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 xmcslot@0 {
47 cell-index = <0>;
48 /*
49 * boolean properties
50 * module-present;
51 */
52 };
53 };
54
55 cpci {
56 /*
57 * boolean properties (true if
58 * system-controller;
59 */
60 system-controller;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 PowerPC,8572@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 d-cache-line-size = <3
71 i-cache-line-size = <3
72 d-cache-size = <0x8000
73 i-cache-size = <0x8000
74 timebase-frequency = <
75 bus-frequency = <0>;
76 clock-frequency = <0>;
77 next-level-cache = <&L
78 };
79
80 PowerPC,8572@1 {
81 device_type = "cpu";
82 reg = <0x1>;
83 d-cache-line-size = <3
84 i-cache-line-size = <3
85 d-cache-size = <0x8000
86 i-cache-size = <0x8000
87 timebase-frequency = <
88 bus-frequency = <0>;
89 clock-frequency = <0>;
90 next-level-cache = <&L
91 };
92 };
93
94 memory {
95 device_type = "memory";
96 reg = <0x0 0x0 0x0 0x0>;
97 };
98
99 localbus@ef005000 {
100 #address-cells = <2>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8572-elbc
103 reg = <0 0xef005000 0 0x1000>;
104 interrupts = <19 2>;
105 interrupt-parent = <&mpic>;
106 /* Local bus region mappings *
107 ranges = <0 0 0 0xf8000000 0x8
108 1 0 0 0xf0000000 0x8
109 2 0 0 0xef800000 0x4
110 3 0 0 0xef840000 0x4
111
112 nor-boot@0,0 {
113 compatible = "amd,s29g
114 bank-width = <2>;
115 reg = <0 0 0x8000000>;
116 #address-cells = <1>;
117 #size-cells = <1>;
118 partition@0 {
119 label = "Prima
120 reg = <0x00000
121 };
122 partition@6f00000 {
123 label = "Prima
124 reg = <0x6f000
125 };
126 partition@7f00000 {
127 label = "Prima
128 reg = <0x7f000
129 };
130 partition@7f40000 {
131 label = "Prima
132 reg = <0x7f400
133 };
134 partition@7f80000 {
135 label = "Prima
136 reg = <0x7f800
137 read-only;
138 };
139 };
140
141 nor-alternate@1,0 {
142 compatible = "amd,s29g
143 bank-width = <2>;
144 //reg = <0xf0000000 0x
145 reg = <1 0 0x8000000>;
146 #address-cells = <1>;
147 #size-cells = <1>;
148 partition@0 {
149 label = "Secon
150 reg = <0x00000
151 };
152 partition@6f00000 {
153 label = "Secon
154 reg = <0x6f000
155 };
156 partition@7f00000 {
157 label = "Secon
158 reg = <0x7f000
159 };
160 partition@7f40000 {
161 label = "Secon
162 reg = <0x7f400
163 };
164 partition@7f80000 {
165 label = "Secon
166 reg = <0x7f800
167 read-only;
168 };
169 };
170
171 nand@2,0 {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 /*
175 * Actual part could b
176 * Micron MT29F8G08DAA
177 * MT29F16G08FAA (2x 1
178 * configuration
179 */
180 compatible = "fsl,mpc8
181 "fsl,elbc
182 reg = <2 0 0x40000>;
183 /* U-Boot should fix t
184 partition@0 {
185 label = "NAND
186 reg = <0 0x400
187 };
188 };
189
190 };
191
192 soc8572@ef000000 {
193 #address-cells = <1>;
194 #size-cells = <1>;
195 device_type = "soc";
196 compatible = "fsl,mpc8572-immr
197 ranges = <0x0 0 0xef000000 0x1
198 bus-frequency = <0>;
199
200 ecm-law@0 {
201 compatible = "fsl,ecm-
202 reg = <0x0 0x1000>;
203 fsl,num-laws = <12>;
204 };
205
206 ecm@1000 {
207 compatible = "fsl,mpc8
208 reg = <0x1000 0x1000>;
209 interrupts = <17 2>;
210 interrupt-parent = <&m
211 };
212
213 memory-controller@2000 {
214 compatible = "fsl,mpc8
215 reg = <0x2000 0x1000>;
216 interrupt-parent = <&m
217 interrupts = <18 2>;
218 };
219
220 memory-controller@6000 {
221 compatible = "fsl,mpc8
222 reg = <0x6000 0x1000>;
223 interrupt-parent = <&m
224 interrupts = <18 2>;
225 };
226
227 L2: l2-cache-controller@20000
228 compatible = "fsl,mpc8
229 reg = <0x20000 0x1000>
230 cache-line-size = <32>
231 cache-size = <0x100000
232 interrupt-parent = <&m
233 interrupts = <16 2>;
234 };
235
236 i2c@3000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 cell-index = <0>;
240 compatible = "fsl-i2c"
241 reg = <0x3000 0x100>;
242 interrupts = <43 2>;
243 interrupt-parent = <&m
244 dfsrr;
245
246 temp-sensor@48 {
247 compatible = "
248 reg = <0x48>;
249 };
250
251 temp-sensor@4c {
252 compatible = "
253 reg = <0x4c>;
254 };
255
256 cpu-supervisor@51 {
257 compatible = "
258 reg = <0x51>;
259 };
260
261 eeprom@54 {
262 compatible = "
263 reg = <0x54>;
264 };
265
266 rtc@68 {
267 compatible = "
268 "
269 reg = <0x68>;
270 };
271
272 pcie-switch@70 {
273 compatible = "
274 reg = <0x70>;
275 };
276
277 gpio1: gpio@18 {
278 compatible = "
279 reg = <0x18>;
280 #gpio-cells =
281 gpio-controlle
282 polarity = <0x
283 };
284
285 gpio2: gpio@1c {
286 compatible = "
287 reg = <0x1c>;
288 #gpio-cells =
289 gpio-controlle
290 polarity = <0x
291 };
292
293 gpio3: gpio@1e {
294 compatible = "
295 reg = <0x1e>;
296 #gpio-cells =
297 gpio-controlle
298 polarity = <0x
299 };
300
301 gpio4: gpio@1f {
302 compatible = "
303 reg = <0x1f>;
304 #gpio-cells =
305 gpio-controlle
306 polarity = <0x
307 };
308 };
309
310 i2c@3100 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 cell-index = <1>;
314 compatible = "fsl-i2c"
315 reg = <0x3100 0x100>;
316 interrupts = <43 2>;
317 interrupt-parent = <&m
318 dfsrr;
319 };
320
321 dma@c300 {
322 #address-cells = <1>;
323 #size-cells = <1>;
324 compatible = "fsl,mpc8
325 reg = <0xc300 0x4>;
326 ranges = <0x0 0xc100 0
327 cell-index = <1>;
328 dma-channel@0 {
329 compatible = "
330
331 reg = <0x0 0x8
332 cell-index = <
333 interrupt-pare
334 interrupts = <
335 };
336 dma-channel@80 {
337 compatible = "
338
339 reg = <0x80 0x
340 cell-index = <
341 interrupt-pare
342 interrupts = <
343 };
344 dma-channel@100 {
345 compatible = "
346
347 reg = <0x100 0
348 cell-index = <
349 interrupt-pare
350 interrupts = <
351 };
352 dma-channel@180 {
353 compatible = "
354
355 reg = <0x180 0
356 cell-index = <
357 interrupt-pare
358 interrupts = <
359 };
360 };
361
362 dma@21300 {
363 #address-cells = <1>;
364 #size-cells = <1>;
365 compatible = "fsl,mpc8
366 reg = <0x21300 0x4>;
367 ranges = <0x0 0x21100
368 cell-index = <0>;
369 dma-channel@0 {
370 compatible = "
371
372 reg = <0x0 0x8
373 cell-index = <
374 interrupt-pare
375 interrupts = <
376 };
377 dma-channel@80 {
378 compatible = "
379
380 reg = <0x80 0x
381 cell-index = <
382 interrupt-pare
383 interrupts = <
384 };
385 dma-channel@100 {
386 compatible = "
387
388 reg = <0x100 0
389 cell-index = <
390 interrupt-pare
391 interrupts = <
392 };
393 dma-channel@180 {
394 compatible = "
395
396 reg = <0x180 0
397 cell-index = <
398 interrupt-pare
399 interrupts = <
400 };
401 };
402
403 /* eTSEC 1 */
404 enet0: ethernet@24000 {
405 #address-cells = <1>;
406 #size-cells = <1>;
407 cell-index = <0>;
408 device_type = "network
409 model = "eTSEC";
410 compatible = "gianfar"
411 reg = <0x24000 0x1000>
412 ranges = <0x0 0x24000
413 local-mac-address = [
414 interrupts = <29 2 30
415 interrupt-parent = <&m
416 tbi-handle = <&tbi0>;
417 phy-handle = <&phy0>;
418 phy-connection-type =
419
420 mdio@520 {
421 #address-cells
422 #size-cells =
423 compatible = "
424 reg = <0x520 0
425
426 phy0: ethernet
427 interr
428 interr
429 reg =
430 };
431 phy1: ethernet
432 interr
433 interr
434 reg =
435 };
436 tbi0: tbi-phy@
437 reg =
438 device
439 };
440 };
441 };
442
443 /* eTSEC 2 */
444 enet1: ethernet@25000 {
445 #address-cells = <1>;
446 #size-cells = <1>;
447 cell-index = <1>;
448 device_type = "network
449 model = "eTSEC";
450 compatible = "gianfar"
451 reg = <0x25000 0x1000>
452 ranges = <0x0 0x25000
453 local-mac-address = [
454 interrupts = <35 2 36
455 interrupt-parent = <&m
456 tbi-handle = <&tbi1>;
457 phy-handle = <&phy1>;
458 phy-connection-type =
459
460 mdio@520 {
461 #address-cells
462 #size-cells =
463 compatible = "
464 reg = <0x520 0
465
466 tbi1: tbi-phy@
467 reg =
468 device
469 };
470 };
471 };
472
473 /* UART0 */
474 serial0: serial@4500 {
475 cell-index = <0>;
476 device_type = "serial"
477 compatible = "fsl,ns16
478 reg = <0x4500 0x100>;
479 clock-frequency = <0>;
480 interrupts = <42 2>;
481 interrupt-parent = <&m
482 };
483
484 /* UART1 */
485 serial1: serial@4600 {
486 cell-index = <1>;
487 device_type = "serial"
488 compatible = "fsl,ns16
489 reg = <0x4600 0x100>;
490 clock-frequency = <0>;
491 interrupts = <42 2>;
492 interrupt-parent = <&m
493 };
494
495 global-utilities@e0000 {
496 compatible = "fsl,mpc8
497 reg = <0xe0000 0x1000>
498 fsl,has-rstcr;
499 };
500
501 msi@41600 {
502 compatible = "fsl,mpc8
503 reg = <0x41600 0x80>;
504 msi-available-ranges =
505 interrupts = <
506 0xe0 0
507 0xe1 0
508 0xe2 0
509 0xe3 0
510 0xe4 0
511 0xe5 0
512 0xe6 0
513 0xe7 0>;
514 interrupt-parent = <&m
515 };
516
517 crypto@30000 {
518 compatible = "fsl,sec3
519 "fsl,sec2
520 reg = <0x30000 0x10000
521 interrupts = <45 2 58
522 interrupt-parent = <&m
523 fsl,num-channels = <4>
524 fsl,channel-fifo-len =
525 fsl,exec-units-mask =
526 fsl,descriptor-types-m
527 };
528
529 mpic: pic@40000 {
530 interrupt-controller;
531 #address-cells = <0>;
532 #interrupt-cells = <2>
533 reg = <0x40000 0x40000
534 compatible = "chrp,ope
535 device_type = "open-pi
536 };
537
538 gpio0: gpio@f000 {
539 compatible = "fsl,mpc8
540 reg = <0xf000 0x1000>;
541 interrupts = <47 2>;
542 interrupt-parent = <&m
543 #gpio-cells = <2>;
544 gpio-controller;
545 };
546
547 gpio-leds {
548 compatible = "gpio-led
549
550 heartbeat {
551 label = "Heart
552 gpios = <&gpio
553 linux,default-
554 };
555
556 yellow {
557 label = "Yello
558 gpios = <&gpio
559 };
560
561 red {
562 label = "Red";
563 gpios = <&gpio
564 };
565
566 green {
567 label = "Green
568 gpios = <&gpio
569 };
570 };
571
572 /* PME (pattern-matcher) */
573 pme@10000 {
574 compatible = "fsl,mpc8
575 reg = <0x10000 0x5000>
576 interrupts = <57 2 64
577 interrupt-parent = <&m
578 };
579
580 tlu@2f000 {
581 compatible = "fsl,mpc8
582 reg = <0x2f000 0x1000>
583 interrupts = <61 2>;
584 interrupt-parent = <&m
585 };
586
587 tlu@15000 {
588 compatible = "fsl,mpc8
589 reg = <0x15000 0x1000>
590 interrupts = <75 2>;
591 interrupt-parent = <&m
592 };
593 };
594
595 /* PCI Express controller 3 - CompactP
596 pci0: pcie@ef008000 {
597 compatible = "fsl,mpc8548-pcie
598 device_type = "pci";
599 #interrupt-cells = <1>;
600 #size-cells = <2>;
601 #address-cells = <3>;
602 reg = <0 0xef008000 0 0x1000>;
603 bus-range = <0 255>;
604 ranges = <0x2000000 0x0 0xe000
605 0x1000000 0x0 0x0000
606 clock-frequency = <33333333>;
607 interrupt-parent = <&mpic>;
608 interrupts = <24 2>;
609 interrupt-map-mask = <0xff00 0
610 interrupt-map = <
611 0x0 0x0 0x0 0x1 &mpic
612 0x0 0x0 0x0 0x2 &mpic
613 0x0 0x0 0x0 0x3 &mpic
614 0x0 0x0 0x0 0x4 &mpic
615 >;
616 pcie@0 {
617 reg = <0x0 0x0 0x0 0x0
618 #size-cells = <2>;
619 #address-cells = <3>;
620 device_type = "pci";
621 ranges = <0x02000000 0
622 0x02000000 0
623 0x0 0x100000
624
625 0x01000000 0
626 0x01000000 0
627 0x0 0x100000
628 };
629 };
630
631 /* PCI Express controller 2, PMC modul
632 pci1: pcie@ef009000 {
633 compatible = "fsl,mpc8548-pcie
634 device_type = "pci";
635 #interrupt-cells = <1>;
636 #size-cells = <2>;
637 #address-cells = <3>;
638 reg = <0 0xef009000 0 0x1000>;
639 bus-range = <0 255>;
640 ranges = <0x2000000 0x0 0xc000
641 0x1000000 0x0 0x0000
642 clock-frequency = <33333333>;
643 interrupt-parent = <&mpic>;
644 interrupts = <25 2>;
645 interrupt-map-mask = <0xf800 0
646 interrupt-map = <
647 /* IDSEL 0x0 */
648 0x0 0x0 0x0 0x1 &mpic
649 0x0 0x0 0x0 0x2 &mpic
650 0x0 0x0 0x0 0x3 &mpic
651 0x0 0x0 0x0 0x4 &mpic
652 >;
653 pcie@0 {
654 reg = <0x0 0x0 0x0 0x0
655 #size-cells = <2>;
656 #address-cells = <3>;
657 device_type = "pci";
658 ranges = <0x2000000 0x
659 0x2000000 0x
660 0x0 0x100000
661
662 0x1000000 0x
663 0x1000000 0x
664 0x0 0x100000
665 };
666 };
667
668 /* PCI Express controller 1, XMC P15 *
669 pci2: pcie@ef00a000 {
670 compatible = "fsl,mpc8548-pcie
671 device_type = "pci";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xef00a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0x8000
678 0x1000000 0x0 0x0000
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
681 interrupts = <26 2>;
682 interrupt-map-mask = <0xf800 0
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0x0 0x0 0x0 0x1 &mpic
686 0x0 0x0 0x0 0x2 &mpic
687 0x0 0x0 0x0 0x3 &mpic
688 0x0 0x0 0x0 0x4 &mpic
689 >;
690 pcie@0 {
691 reg = <0x0 0x0 0x0 0x0
692 #size-cells = <2>;
693 #address-cells = <3>;
694 device_type = "pci";
695 ranges = <0x2000000 0x
696 0x2000000 0x
697 0x0 0x400000
698
699 0x1000000 0x
700 0x1000000 0x
701 0x0 0x100000
702 };
703 };
704 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.