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Linux/arch/powerpc/boot/gamecube-head.S

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Diff markup

Differences between /arch/powerpc/boot/gamecube-head.S (Version linux-6.12-rc7) and /arch/m68k/boot/gamecube-head.S (Version linux-6.7.12)


  1 /* SPDX-License-Identifier: GPL-2.0-or-later *    
  2 /*                                                
  3  * arch/powerpc/boot/gamecube-head.S              
  4  *                                                
  5  * Nintendo GameCube bootwrapper entry.           
  6  * Copyright (C) 2004-2009 The GameCube Linux     
  7  * Copyright (C) 2008,2009 Albert Herranz         
  8  */                                               
  9                                                   
 10 #include "ppc_asm.h"                              
 11                                                   
 12 /*                                                
 13  * The entry code does no assumptions regardin    
 14  * - if the data and instruction caches are en    
 15  * - if the MMU is enabled or not                 
 16  *                                                
 17  * We enable the caches if not already enabled    
 18  * identity mapping scheme and jump to the sta    
 19  */                                               
 20                                                   
 21         .text                                     
 22                                                   
 23         .globl _zimage_start                      
 24 _zimage_start:                                    
 25                                                   
 26         /* turn the MMU off */                    
 27         mfmsr   9                                 
 28         rlwinm  9, 9, 0, ~((1<<4)|(1<<5)) /* M    
 29         bcl     20, 31, 1f                        
 30 1:                                                
 31         mflr    8                                 
 32         clrlwi  8, 8, 3         /* convert to     
 33         addi    8, 8, _mmu_off - 1b               
 34         mtsrr0  8                                 
 35         mtsrr1  9                                 
 36         rfi                                       
 37 _mmu_off:                                         
 38         /* MMU disabled */                        
 39                                                   
 40         /* setup BATs */                          
 41         isync                                     
 42         li      8, 0                              
 43         mtspr   0x210, 8        /* IBAT0U */      
 44         mtspr   0x212, 8        /* IBAT1U */      
 45         mtspr   0x214, 8        /* IBAT2U */      
 46         mtspr   0x216, 8        /* IBAT3U */      
 47         mtspr   0x218, 8        /* DBAT0U */      
 48         mtspr   0x21a, 8        /* DBAT1U */      
 49         mtspr   0x21c, 8        /* DBAT2U */      
 50         mtspr   0x21e, 8        /* DBAT3U */      
 51                                                   
 52         li      8, 0x01ff       /* first 16MiB    
 53         li      9, 0x0002       /* rw */          
 54         mtspr   0x211, 9        /* IBAT0L */      
 55         mtspr   0x210, 8        /* IBAT0U */      
 56         mtspr   0x219, 9        /* DBAT0L */      
 57         mtspr   0x218, 8        /* DBAT0U */      
 58                                                   
 59         lis     8, 0x0c00       /* I/O mem */     
 60         ori     8, 8, 0x3ff     /* 32MiB */       
 61         lis     9, 0x0c00                         
 62         ori     9, 9, 0x002a    /* uncached, g    
 63         mtspr   0x21b, 9        /* DBAT1L */      
 64         mtspr   0x21a, 8        /* DBAT1U */      
 65                                                   
 66         lis     8, 0x0100       /* next 8MiB *    
 67         ori     8, 8, 0x00ff    /* 8MiB */        
 68         lis     9, 0x0100                         
 69         ori     9, 9, 0x0002    /* rw */          
 70         mtspr   0x215, 9        /* IBAT2L */      
 71         mtspr   0x214, 8        /* IBAT2U */      
 72         mtspr   0x21d, 9        /* DBAT2L */      
 73         mtspr   0x21c, 8        /* DBAT2U */      
 74                                                   
 75         /* enable and invalidate the caches if    
 76         mfspr   8, 0x3f0        /* HID0 */        
 77         andi.   0, 8, (1<<15)           /* HID    
 78         bne     1f                                
 79         ori     8, 8, (1<<15)|(1<<11)   /* HID    
 80 1:                                                
 81         andi.   0, 8, (1<<14)           /* HID    
 82         bne     1f                                
 83         ori     8, 8, (1<<14)|(1<<10)   /* HID    
 84 1:                                                
 85         mtspr   0x3f0, 8        /* HID0 */        
 86         isync                                     
 87                                                   
 88         /* initialize arguments */                
 89         li      3, 0                              
 90         li      4, 0                              
 91         li      5, 0                              
 92                                                   
 93         /* turn the MMU on */                     
 94         bcl     20, 31, 1f                        
 95 1:                                                
 96         mflr    8                                 
 97         addi    8, 8, _mmu_on - 1b                
 98         mfmsr   9                                 
 99         ori     9, 9, (1<<4)|(1<<5) /* MSR_DR|    
100         mtsrr0  8                                 
101         mtsrr1  9                                 
102         sync                                      
103         rfi                                       
104 _mmu_on:                                          
105         b _zimage_start_lib                       
106                                                   
                                                      

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