1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* 3 * Definitions for use by exception code on B 4 * 5 * Copyright (C) 2008 Ben. Herrenschmidt (ben 6 */ 7 #ifndef _ASM_POWERPC_EXCEPTION_64E_H 8 #define _ASM_POWERPC_EXCEPTION_64E_H 9 10 /* 11 * SPRGs usage an other considerations... 12 * 13 * Since TLB miss and other standard exception 14 * critical exceptions which can themselves be 15 * checks, and since the two later can themsel 16 * hitting the linear mapping for the kernel s 17 * creative on how we use SPRGs. 18 * 19 * The base idea is that we have one SRPG rese 20 * for machine check interrupts. Those are use 21 * then be used to get the PACA, and store as 22 * to save in there. That includes saving the 23 * handler for linear mapping misses and the a 24 * the above re-entrancy issue. 25 * 26 * So here's the current usage pattern. It's d 27 * SPRGs are user-readable though, thus we mig 28 * this later. In order to do that more easily 29 * for naming them 30 * 31 * WARNING: Some of these SPRGs are user reada 32 * about it as some point by making sure they 33 * critical data 34 */ 35 36 #define PACA_EXGDBELL PACA_EXGEN 37 38 /* We are out of SPRGs so we save some things 39 * exception frame is smaller than the CRIT or 40 */ 41 #define EX_R1 (0 * 8) 42 #define EX_CR (1 * 8) 43 #define EX_R10 (2 * 8) 44 #define EX_R11 (3 * 8) 45 #define EX_R14 (4 * 8) 46 #define EX_R15 (5 * 8) 47 48 /* 49 * The TLB miss exception uses different slots 50 * 51 * The bolted variant uses only the first six 52 * which in combination with pgd and kernel_pg 53 * one 64-byte cache line. 54 */ 55 56 #define EX_TLB_R10 ( 0 * 8) 57 #define EX_TLB_R11 ( 1 * 8) 58 #define EX_TLB_R14 ( 2 * 8) 59 #define EX_TLB_R15 ( 3 * 8) 60 #define EX_TLB_R16 ( 4 * 8) 61 #define EX_TLB_CR ( 5 * 8) 62 #define EX_TLB_R12 ( 6 * 8) 63 #define EX_TLB_R13 ( 7 * 8) 64 #define EX_TLB_DEAR ( 8 * 8) /* Level 0 an 65 #define EX_TLB_ESR ( 9 * 8) /* Level 0 an 66 #define EX_TLB_SRR0 (10 * 8) 67 #define EX_TLB_SRR1 (11 * 8) 68 #define EX_TLB_R7 (12 * 8) 69 #define EX_TLB_SIZE (13 * 8) 70 71 #define START_EXCEPTION(label) 72 .globl exc_##label##_book3e; 73 exc_##label##_book3e: 74 75 /* TLB miss exception prolog 76 * 77 * This prolog handles re-entrancy (up to 3 le 78 * though we currently don't test for overflow 79 * re-entrancy safe working space of r10...r16 80 * as the exception area pointer in the PACA f 81 * and r13 containing the PACA pointer. 82 * 83 * SRR0 and SRR1 are saved, but DEAR and ESR a 84 * as-is for instruction exceptions. It's up t 85 * to save them as well if required. 86 */ 87 #define TLB_MISS_PROLOG 88 mtspr SPRN_SPRG_TLB_SCRATCH,r12; 89 mfspr r12,SPRN_SPRG_TLB_EXFRAME; 90 std r10,EX_TLB_R10(r12); 91 mfcr r10; 92 std r11,EX_TLB_R11(r12); 93 mfspr r11,SPRN_SPRG_TLB_SCRATCH; 94 std r13,EX_TLB_R13(r12); 95 mfspr r13,SPRN_SPRG_PACA; 96 std r14,EX_TLB_R14(r12); 97 addi r14,r12,EX_TLB_SIZE; 98 std r15,EX_TLB_R15(r12); 99 mfspr r15,SPRN_SRR1; 100 std r16,EX_TLB_R16(r12); 101 mfspr r16,SPRN_SRR0; 102 std r10,EX_TLB_CR(r12); 103 std r11,EX_TLB_R12(r12); 104 mtspr SPRN_SPRG_TLB_EXFRAME,r14; 105 std r15,EX_TLB_SRR1(r12); 106 std r16,EX_TLB_SRR0(r12); 107 108 /* And these are the matching epilogs that res 109 * 110 * There are 3 epilogs: 111 * 112 * - SUCCESS : Unwinds one level 113 * - ERROR : restore from level 0 and 114 * - ERROR_SPECIAL : restore from current leve 115 * 116 * Normal errors use ERROR, that is, they rest 117 * and trigger a fault. However, there is a sp 118 * errors. Those should basically never happen 119 * want the error to point out the context tha 120 * fault, not the initial level 0 (basically, 121 * like that). For userland errors on the line 122 * difference since those are always level 0 a 123 */ 124 125 #define TLB_MISS_RESTORE(freg) 126 ld r14,EX_TLB_CR(r12); 127 ld r10,EX_TLB_R10(r12); 128 ld r15,EX_TLB_SRR0(r12); 129 ld r16,EX_TLB_SRR1(r12); 130 mtspr SPRN_SPRG_TLB_EXFRAME,freg; 131 ld r11,EX_TLB_R11(r12); 132 mtcr r14; 133 ld r13,EX_TLB_R13(r12); 134 ld r14,EX_TLB_R14(r12); 135 mtspr SPRN_SRR0,r15; 136 ld r15,EX_TLB_R15(r12); 137 mtspr SPRN_SRR1,r16; 138 ld r16,EX_TLB_R16(r12); 139 ld r12,EX_TLB_R12(r12); 140 141 #define TLB_MISS_EPILOG_SUCCESS 142 TLB_MISS_RESTORE(r12) 143 144 #define TLB_MISS_EPILOG_ERROR 145 addi r12,r13,PACA_EXTLB; 146 TLB_MISS_RESTORE(r12) 147 148 #define TLB_MISS_EPILOG_ERROR_SPECIAL 149 addi r11,r13,PACA_EXTLB; 150 TLB_MISS_RESTORE(r11) 151 152 #ifndef __ASSEMBLY__ 153 extern unsigned int interrupt_base_book3e; 154 #endif 155 156 #define SET_IVOR(vector_number, vector_offset) 157 LOAD_REG_ADDR(r3,interrupt_base_book3e 158 ori r3,r3,vector_offset@l; 159 mtspr SPRN_IVOR##vector_number,r3; 160 /* 161 * powerpc relies on return from interrupt/sys 162 * (which rfi is) to support ARCH_HAS_MEMBARRI 163 * synchronisation instructions. 164 */ 165 #define RFI_TO_KERNEL 166 rfi 167 168 #define RFI_TO_USER 169 rfi 170 171 #endif /* _ASM_POWERPC_EXCEPTION_64E_H */ 172 173
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